Commit bb5aa085 authored by Neil Armstrong's avatar Neil Armstrong Committed by Jerome Brunet

clk: meson: add vclk driver

The VCLK and VCLK_DIV clocks have supplementary bits.

The VCLK gate has a "SOFT RESET" bit to toggle after the whole
VCLK sub-tree rate has been set, this is implemented in
the gate enable callback.

The VCLK_DIV clocks as enable and reset bits used to disable
and reset the divider, associated with CLK_SET_RATE_GATE it ensures
the rate is set while the divider is disabled and in reset mode.

The VCLK_DIV enable bit isn't implemented as a gate since it's part
of the divider logic and vendor does this exact sequence to ensure
the divider is correctly set.
Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-2-99ecdfdc87fc@linaro.orgSigned-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 16182ac3
...@@ -30,6 +30,10 @@ config COMMON_CLK_MESON_VID_PLL_DIV ...@@ -30,6 +30,10 @@ config COMMON_CLK_MESON_VID_PLL_DIV
tristate tristate
select COMMON_CLK_MESON_REGMAP select COMMON_CLK_MESON_REGMAP
config COMMON_CLK_MESON_VCLK
tristate
select COMMON_CLK_MESON_REGMAP
config COMMON_CLK_MESON_CLKC_UTILS config COMMON_CLK_MESON_CLKC_UTILS
tristate tristate
......
...@@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o ...@@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o
obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o
obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
obj-$(CONFIG_COMMON_CLK_MESON_VCLK) += vclk.o
# Amlogic Clock controllers # Amlogic Clock controllers
......
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2024 Neil Armstrong <neil.armstrong@linaro.org>
*/
#include <linux/module.h>
#include "vclk.h"
/* The VCLK gate has a supplementary reset bit to pulse after ungating */
static inline struct meson_vclk_gate_data *
clk_get_meson_vclk_gate_data(struct clk_regmap *clk)
{
return (struct meson_vclk_gate_data *)clk->data;
}
static int meson_vclk_gate_enable(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
meson_parm_write(clk->map, &vclk->enable, 1);
/* Do a reset pulse */
meson_parm_write(clk->map, &vclk->reset, 1);
meson_parm_write(clk->map, &vclk->reset, 0);
return 0;
}
static void meson_vclk_gate_disable(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
meson_parm_write(clk->map, &vclk->enable, 0);
}
static int meson_vclk_gate_is_enabled(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
return meson_parm_read(clk->map, &vclk->enable);
}
const struct clk_ops meson_vclk_gate_ops = {
.enable = meson_vclk_gate_enable,
.disable = meson_vclk_gate_disable,
.is_enabled = meson_vclk_gate_is_enabled,
};
EXPORT_SYMBOL_GPL(meson_vclk_gate_ops);
/* The VCLK Divider has supplementary reset & enable bits */
static inline struct meson_vclk_div_data *
clk_get_meson_vclk_div_data(struct clk_regmap *clk)
{
return (struct meson_vclk_div_data *)clk->data;
}
static unsigned long meson_vclk_div_recalc_rate(struct clk_hw *hw,
unsigned long prate)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
return divider_recalc_rate(hw, prate, meson_parm_read(clk->map, &vclk->div),
vclk->table, vclk->flags, vclk->div.width);
}
static int meson_vclk_div_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
return divider_determine_rate(hw, req, vclk->table, vclk->div.width,
vclk->flags);
}
static int meson_vclk_div_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
int ret;
ret = divider_get_val(rate, parent_rate, vclk->table, vclk->div.width,
vclk->flags);
if (ret < 0)
return ret;
meson_parm_write(clk->map, &vclk->div, ret);
return 0;
};
static int meson_vclk_div_enable(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
/* Unreset the divider when ungating */
meson_parm_write(clk->map, &vclk->reset, 0);
meson_parm_write(clk->map, &vclk->enable, 1);
return 0;
}
static void meson_vclk_div_disable(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
/* Reset the divider when gating */
meson_parm_write(clk->map, &vclk->enable, 0);
meson_parm_write(clk->map, &vclk->reset, 1);
}
static int meson_vclk_div_is_enabled(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
return meson_parm_read(clk->map, &vclk->enable);
}
const struct clk_ops meson_vclk_div_ops = {
.recalc_rate = meson_vclk_div_recalc_rate,
.determine_rate = meson_vclk_div_determine_rate,
.set_rate = meson_vclk_div_set_rate,
.enable = meson_vclk_div_enable,
.disable = meson_vclk_div_disable,
.is_enabled = meson_vclk_div_is_enabled,
};
EXPORT_SYMBOL_GPL(meson_vclk_div_ops);
MODULE_DESCRIPTION("Amlogic vclk clock driver");
MODULE_AUTHOR("Neil Armstrong <neil.armstrong@linaro.org>");
MODULE_LICENSE("GPL v2");
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2024 Neil Armstrong <neil.armstrong@linaro.org>
*/
#ifndef __VCLK_H
#define __VCLK_H
#include "clk-regmap.h"
#include "parm.h"
/**
* struct meson_vclk_gate_data - vclk_gate regmap backed specific data
*
* @enable: vclk enable field
* @reset: vclk reset field
* @flags: hardware-specific flags
*
* Flags:
* Same as clk_gate except CLK_GATE_HIWORD_MASK which is ignored
*/
struct meson_vclk_gate_data {
struct parm enable;
struct parm reset;
u8 flags;
};
extern const struct clk_ops meson_vclk_gate_ops;
/**
* struct meson_vclk_div_data - vclk_div regmap back specific data
*
* @div: divider field
* @enable: vclk divider enable field
* @reset: vclk divider reset field
* @table: array of value/divider pairs, last entry should have div = 0
*
* Flags:
* Same as clk_divider except CLK_DIVIDER_HIWORD_MASK which is ignored
*/
struct meson_vclk_div_data {
struct parm div;
struct parm enable;
struct parm reset;
const struct clk_div_table *table;
u8 flags;
};
extern const struct clk_ops meson_vclk_div_ops;
#endif /* __VCLK_H */
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