Commit bc2eca9a authored by Nicolas Pitre's avatar Nicolas Pitre Committed by Russell King

ARM: 8811/1: always list both ldrd/strd registers explicitly

The ldrd and strd instructions work on a pair of consecutive registers.
It is possible to specify either the first register in the pair, or both
registers explicitly. Let's always do the later to make things clearer.
Signed-off-by: default avatarNicolas Pitre <nico@linaro.org>
Suggested-by: default avatarRobin Murphy <robin.murphy@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
parent 82c08c3e
......@@ -398,7 +398,7 @@ ENTRY(secondary_startup)
ldmia r4, {r5, r7, r12} @ address to jump to after
sub lr, r4, r5 @ mmu has been enabled
add r3, r7, lr
ldrd r4, [r3, #0] @ get secondary_data.pgdir
ldrd r4, r5, [r3, #0] @ get secondary_data.pgdir
ARM_BE8(eor r4, r4, r5) @ Swap r5 and r4 in BE:
ARM_BE8(eor r5, r4, r5) @ it can be done in 3 steps
ARM_BE8(eor r4, r4, r5) @ without using a temp reg.
......
......@@ -37,25 +37,25 @@ static void xsc3_mc_copy_user_page(void *kto, const void *kfrom)
1: pld [%1, #64] \n\
pld [%1, #96] \n\
\n\
2: ldrd r2, [%1], #8 \n\
ldrd r4, [%1], #8 \n\
2: ldrd r2, r3, [%1], #8 \n\
ldrd r4, r5, [%1], #8 \n\
mcr p15, 0, %0, c7, c6, 1 @ invalidate\n\
strd r2, [%0], #8 \n\
ldrd r2, [%1], #8 \n\
strd r4, [%0], #8 \n\
ldrd r4, [%1], #8 \n\
strd r2, [%0], #8 \n\
strd r4, [%0], #8 \n\
ldrd r2, [%1], #8 \n\
ldrd r4, [%1], #8 \n\
strd r2, r3, [%0], #8 \n\
ldrd r2, r3, [%1], #8 \n\
strd r4, r5, [%0], #8 \n\
ldrd r4, r5, [%1], #8 \n\
strd r2, r3, [%0], #8 \n\
strd r4, r5, [%0], #8 \n\
ldrd r2, r3, [%1], #8 \n\
ldrd r4, r5, [%1], #8 \n\
mcr p15, 0, %0, c7, c6, 1 @ invalidate\n\
strd r2, [%0], #8 \n\
ldrd r2, [%1], #8 \n\
strd r2, r3, [%0], #8 \n\
ldrd r2, r3, [%1], #8 \n\
subs %2, %2, #1 \n\
strd r4, [%0], #8 \n\
ldrd r4, [%1], #8 \n\
strd r2, [%0], #8 \n\
strd r4, [%0], #8 \n\
strd r4, r5, [%0], #8 \n\
ldrd r4, r5, [%1], #8 \n\
strd r2, r3, [%0], #8 \n\
strd r4, r5, [%0], #8 \n\
bgt 1b \n\
beq 2b "
: "+&r" (kto), "+&r" (kfrom), "=&r" (tmp)
......@@ -87,10 +87,10 @@ void xsc3_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
mov r2, #0 \n\
mov r3, #0 \n\
1: mcr p15, 0, %0, c7, c6, 1 @ invalidate line\n\
strd r2, [%0], #8 \n\
strd r2, [%0], #8 \n\
strd r2, [%0], #8 \n\
strd r2, [%0], #8 \n\
strd r2, r3, [%0], #8 \n\
strd r2, r3, [%0], #8 \n\
strd r2, r3, [%0], #8 \n\
strd r2, r3, [%0], #8 \n\
subs r1, r1, #1 \n\
bne 1b"
: "=r" (ptr)
......
......@@ -53,26 +53,26 @@ static void mc_copy_user_page(void *from, void *to)
pld [%0, #96] \n\
pld [%1, #64] \n\
pld [%1, #96] \n\
2: ldrd r2, [%0], #8 \n\
ldrd r4, [%0], #8 \n\
2: ldrd r2, r3, [%0], #8 \n\
ldrd r4, r5, [%0], #8 \n\
mov ip, %1 \n\
strd r2, [%1], #8 \n\
ldrd r2, [%0], #8 \n\
strd r4, [%1], #8 \n\
ldrd r4, [%0], #8 \n\
strd r2, [%1], #8 \n\
strd r4, [%1], #8 \n\
strd r2, r3, [%1], #8 \n\
ldrd r2, r3, [%0], #8 \n\
strd r4, r5, [%1], #8 \n\
ldrd r4, r5, [%0], #8 \n\
strd r2, r3, [%1], #8 \n\
strd r4, r5, [%1], #8 \n\
mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
ldrd r2, [%0], #8 \n\
ldrd r2, r3, [%0], #8 \n\
mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
ldrd r4, [%0], #8 \n\
ldrd r4, r5, [%0], #8 \n\
mov ip, %1 \n\
strd r2, [%1], #8 \n\
ldrd r2, [%0], #8 \n\
strd r4, [%1], #8 \n\
ldrd r4, [%0], #8 \n\
strd r2, [%1], #8 \n\
strd r4, [%1], #8 \n\
strd r2, r3, [%1], #8 \n\
ldrd r2, r3, [%0], #8 \n\
strd r4, r5, [%1], #8 \n\
ldrd r4, r5, [%0], #8 \n\
strd r2, r3, [%1], #8 \n\
strd r4, r5, [%1], #8 \n\
mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
subs %2, %2, #1 \n\
mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
......@@ -114,10 +114,10 @@ xscale_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
mov r2, #0 \n\
mov r3, #0 \n\
1: mov ip, %0 \n\
strd r2, [%0], #8 \n\
strd r2, [%0], #8 \n\
strd r2, [%0], #8 \n\
strd r2, [%0], #8 \n\
strd r2, r3, [%0], #8 \n\
strd r2, r3, [%0], #8 \n\
strd r2, r3, [%0], #8 \n\
strd r2, r3, [%0], #8 \n\
mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
subs r1, r1, #1 \n\
mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
......
......@@ -33,10 +33,10 @@ ENTRY(lpae_pgtables_remap_asm)
add r7, r2, #0x1000
add r6, r7, r6, lsr #SECTION_SHIFT - L2_ORDER
add r7, r7, #PAGE_OFFSET >> (SECTION_SHIFT - L2_ORDER)
1: ldrd r4, [r7]
1: ldrd r4, r5, [r7]
adds r4, r4, r0
adc r5, r5, r1
strd r4, [r7], #1 << L2_ORDER
strd r4, r5, [r7], #1 << L2_ORDER
cmp r7, r6
bls 1b
......@@ -44,22 +44,22 @@ ENTRY(lpae_pgtables_remap_asm)
add r7, r2, #0x1000
add r7, r7, r3, lsr #SECTION_SHIFT - L2_ORDER
bic r7, r7, #(1 << L2_ORDER) - 1
ldrd r4, [r7]
ldrd r4, r5, [r7]
adds r4, r4, r0
adc r5, r5, r1
strd r4, [r7], #1 << L2_ORDER
ldrd r4, [r7]
strd r4, r5, [r7], #1 << L2_ORDER
ldrd r4, r5, [r7]
adds r4, r4, r0
adc r5, r5, r1
strd r4, [r7]
strd r4, r5, [r7]
/* Update level 1 entries */
mov r6, #4
mov r7, r2
2: ldrd r4, [r7]
2: ldrd r4, r5, [r7]
adds r4, r4, r0
adc r5, r5, r1
strd r4, [r7], #1 << L1_ORDER
strd r4, r5, [r7], #1 << L1_ORDER
subs r6, r6, #1
bne 2b
......
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