Commit bca2bf2a authored by Pandiyan, Dhinakaran's avatar Pandiyan, Dhinakaran Committed by Tvrtko Ursulin

drm/i915: s/INTEL_INFO(dev_priv)->gen/INTEL_GEN(dev_priv) in i915_irq

INTEL_GEN() appears to be the new way of doing these platform checks, so
convert this i915_irq.c too.
Signed-off-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1500402480-30741-1-git-send-email-dhinakaran.pandiyan@intel.com
parent ce87ea15
...@@ -275,17 +275,17 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) ...@@ -275,17 +275,17 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv) static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
{ {
return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
} }
static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv) static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
{ {
return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
} }
static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv) static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
{ {
return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
} }
/** /**
...@@ -1661,7 +1661,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) ...@@ -1661,7 +1661,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
spin_unlock(&dev_priv->irq_lock); spin_unlock(&dev_priv->irq_lock);
} }
if (INTEL_INFO(dev_priv)->gen >= 8) if (INTEL_GEN(dev_priv) >= 8)
return; return;
if (HAS_VEBOX(dev_priv)) { if (HAS_VEBOX(dev_priv)) {
...@@ -2440,7 +2440,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) ...@@ -2440,7 +2440,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
ret = IRQ_HANDLED; ret = IRQ_HANDLED;
tmp_mask = GEN8_AUX_CHANNEL_A; tmp_mask = GEN8_AUX_CHANNEL_A;
if (INTEL_INFO(dev_priv)->gen >= 9) if (INTEL_GEN(dev_priv) >= 9)
tmp_mask |= GEN9_AUX_CHANNEL_B | tmp_mask |= GEN9_AUX_CHANNEL_B |
GEN9_AUX_CHANNEL_C | GEN9_AUX_CHANNEL_C |
GEN9_AUX_CHANNEL_D; GEN9_AUX_CHANNEL_D;
...@@ -2498,7 +2498,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) ...@@ -2498,7 +2498,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
intel_check_page_flip(dev_priv, pipe); intel_check_page_flip(dev_priv, pipe);
flip_done = iir; flip_done = iir;
if (INTEL_INFO(dev_priv)->gen >= 9) if (INTEL_GEN(dev_priv) >= 9)
flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE; flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
else else
flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE; flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
...@@ -2513,7 +2513,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) ...@@ -2513,7 +2513,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
fault_errors = iir; fault_errors = iir;
if (INTEL_INFO(dev_priv)->gen >= 9) if (INTEL_GEN(dev_priv) >= 9)
fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS; fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
else else
fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS; fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
...@@ -3492,7 +3492,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) ...@@ -3492,7 +3492,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
u32 de_misc_masked = GEN8_DE_MISC_GSE; u32 de_misc_masked = GEN8_DE_MISC_GSE;
enum pipe pipe; enum pipe pipe;
if (INTEL_INFO(dev_priv)->gen >= 9) { if (INTEL_GEN(dev_priv) >= 9) {
de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
GEN9_DE_PIPE_IRQ_FAULT_ERRORS; GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
...@@ -4290,16 +4290,16 @@ void intel_irq_init(struct drm_i915_private *dev_priv) ...@@ -4290,16 +4290,16 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
* *
* TODO: verify if this can be reproduced on VLV,CHV. * TODO: verify if this can be reproduced on VLV,CHV.
*/ */
if (INTEL_INFO(dev_priv)->gen <= 7) if (INTEL_GEN(dev_priv) <= 7)
dev_priv->rps.pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED; dev_priv->rps.pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
if (INTEL_INFO(dev_priv)->gen >= 8) if (INTEL_GEN(dev_priv) >= 8)
dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
if (IS_GEN2(dev_priv)) { if (IS_GEN2(dev_priv)) {
/* Gen2 doesn't have a hardware frame counter */ /* Gen2 doesn't have a hardware frame counter */
dev->max_vblank_count = 0; dev->max_vblank_count = 0;
} else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
dev->driver->get_vblank_counter = g4x_get_vblank_counter; dev->driver->get_vblank_counter = g4x_get_vblank_counter;
} else { } else {
...@@ -4346,7 +4346,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) ...@@ -4346,7 +4346,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev->driver->enable_vblank = i965_enable_vblank; dev->driver->enable_vblank = i965_enable_vblank;
dev->driver->disable_vblank = i965_disable_vblank; dev->driver->disable_vblank = i965_disable_vblank;
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
} else if (INTEL_INFO(dev_priv)->gen >= 8) { } else if (INTEL_GEN(dev_priv) >= 8) {
dev->driver->irq_handler = gen8_irq_handler; dev->driver->irq_handler = gen8_irq_handler;
dev->driver->irq_preinstall = gen8_irq_reset; dev->driver->irq_preinstall = gen8_irq_reset;
dev->driver->irq_postinstall = gen8_irq_postinstall; dev->driver->irq_postinstall = gen8_irq_postinstall;
......
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