Commit bd5196b6 authored by David S. Miller's avatar David S. Miller

Merge branch 'hns3-hwgro'

Salil Mehta says:

====================
net: hns3: Add support of hardware GRO to HNS3 Driver

This patch-set adds support of hardware assisted GRO feature to
HNS3 driver on Rev B(=0x21) platform. Current hardware only
supports TCP/IPv{4|6} flows.

Change Log:
V1->V2:
1. Remove redundant print reported by Leon Romanovsky.
   Link: https://lkml.org/lkml/2018/11/13/715
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents ba2f55b0 a6d53b97
...@@ -52,6 +52,7 @@ ...@@ -52,6 +52,7 @@
#define HNAE3_UNIC_CLIENT_INITED_B 0x4 #define HNAE3_UNIC_CLIENT_INITED_B 0x4
#define HNAE3_ROCE_CLIENT_INITED_B 0x5 #define HNAE3_ROCE_CLIENT_INITED_B 0x5
#define HNAE3_DEV_SUPPORT_FD_B 0x6 #define HNAE3_DEV_SUPPORT_FD_B 0x6
#define HNAE3_DEV_SUPPORT_GRO_B 0x7
#define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\ #define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\
BIT(HNAE3_DEV_SUPPORT_ROCE_B)) BIT(HNAE3_DEV_SUPPORT_ROCE_B))
...@@ -65,6 +66,9 @@ ...@@ -65,6 +66,9 @@
#define hnae3_dev_fd_supported(hdev) \ #define hnae3_dev_fd_supported(hdev) \
hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B) hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B)
#define hnae3_dev_gro_supported(hdev) \
hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B)
#define ring_ptr_move_fw(ring, p) \ #define ring_ptr_move_fw(ring, p) \
((ring)->p = ((ring)->p + 1) % (ring)->desc_num) ((ring)->p = ((ring)->p + 1) % (ring)->desc_num)
#define ring_ptr_move_bw(ring, p) \ #define ring_ptr_move_bw(ring, p) \
...@@ -301,6 +305,8 @@ struct hnae3_ae_dev { ...@@ -301,6 +305,8 @@ struct hnae3_ae_dev {
* Set vlan filter config of vf * Set vlan filter config of vf
* enable_hw_strip_rxvtag() * enable_hw_strip_rxvtag()
* Enable/disable hardware strip vlan tag of packets received * Enable/disable hardware strip vlan tag of packets received
* set_gro_en
* Enable/disable HW GRO
*/ */
struct hnae3_ae_ops { struct hnae3_ae_ops {
int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev); int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev);
...@@ -445,6 +451,7 @@ struct hnae3_ae_ops { ...@@ -445,6 +451,7 @@ struct hnae3_ae_ops {
bool (*get_hw_reset_stat)(struct hnae3_handle *handle); bool (*get_hw_reset_stat)(struct hnae3_handle *handle);
bool (*ae_dev_resetting)(struct hnae3_handle *handle); bool (*ae_dev_resetting)(struct hnae3_handle *handle);
unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle); unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle);
int (*set_gro_en)(struct hnae3_handle *handle, int enable);
}; };
struct hnae3_dcb_ops { struct hnae3_dcb_ops {
......
...@@ -109,6 +109,10 @@ enum hns3_nic_state { ...@@ -109,6 +109,10 @@ enum hns3_nic_state {
#define HNS3_RXD_DOI_B 21 #define HNS3_RXD_DOI_B 21
#define HNS3_RXD_OL3E_B 22 #define HNS3_RXD_OL3E_B 22
#define HNS3_RXD_OL4E_B 23 #define HNS3_RXD_OL4E_B 23
#define HNS3_RXD_GRO_COUNT_S 24
#define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
#define HNS3_RXD_GRO_FIXID_B 30
#define HNS3_RXD_GRO_ECN_B 31
#define HNS3_RXD_ODMAC_S 0 #define HNS3_RXD_ODMAC_S 0
#define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S) #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
...@@ -135,9 +139,8 @@ enum hns3_nic_state { ...@@ -135,9 +139,8 @@ enum hns3_nic_state {
#define HNS3_RXD_TSIND_S 12 #define HNS3_RXD_TSIND_S 12
#define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S) #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
#define HNS3_RXD_LKBK_B 15 #define HNS3_RXD_LKBK_B 15
#define HNS3_RXD_HDL_S 16 #define HNS3_RXD_GRO_SIZE_S 16
#define HNS3_RXD_HDL_M (0x7ff << HNS3_RXD_HDL_S) #define HNS3_RXD_GRO_SIZE_M (0x3ff << HNS3_RXD_GRO_SIZE_S)
#define HNS3_RXD_HSIND_B 31
#define HNS3_TXD_L3T_S 0 #define HNS3_TXD_L3T_S 0
#define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S) #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
...@@ -401,11 +404,19 @@ struct hns3_enet_ring { ...@@ -401,11 +404,19 @@ struct hns3_enet_ring {
*/ */
int next_to_clean; int next_to_clean;
int pull_len; /* head length for current packet */
u32 frag_num;
unsigned char *va; /* first buffer address for current packet */
u32 flag; /* ring attribute */ u32 flag; /* ring attribute */
int irq_init_flag; int irq_init_flag;
int numa_node; int numa_node;
cpumask_t affinity_mask; cpumask_t affinity_mask;
int pending_buf;
struct sk_buff *skb;
struct sk_buff *tail_skb;
}; };
struct hns_queue; struct hns_queue;
......
...@@ -152,6 +152,7 @@ enum hclge_opcode_type { ...@@ -152,6 +152,7 @@ enum hclge_opcode_type {
/* TSO command */ /* TSO command */
HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01,
HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10,
/* RSS commands */ /* RSS commands */
HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01,
...@@ -758,6 +759,12 @@ struct hclge_cfg_tso_status_cmd { ...@@ -758,6 +759,12 @@ struct hclge_cfg_tso_status_cmd {
u8 rsv[20]; u8 rsv[20];
}; };
#define HCLGE_GRO_EN_B 0
struct hclge_cfg_gro_status_cmd {
__le16 gro_en;
u8 rsv[22];
};
#define HCLGE_TSO_MSS_MIN 256 #define HCLGE_TSO_MSS_MIN 256
#define HCLGE_TSO_MSS_MAX 9668 #define HCLGE_TSO_MSS_MAX 9668
......
...@@ -921,6 +921,28 @@ static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min, ...@@ -921,6 +921,28 @@ static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
return hclge_cmd_send(&hdev->hw, &desc, 1); return hclge_cmd_send(&hdev->hw, &desc, 1);
} }
static int hclge_config_gro(struct hclge_dev *hdev, bool en)
{
struct hclge_cfg_gro_status_cmd *req;
struct hclge_desc desc;
int ret;
if (!hnae3_dev_gro_supported(hdev))
return 0;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false);
req = (struct hclge_cfg_gro_status_cmd *)desc.data;
req->gro_en = cpu_to_le16(en ? 1 : 0);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
dev_err(&hdev->pdev->dev,
"GRO hardware config cmd failed, ret = %d\n", ret);
return ret;
}
static int hclge_alloc_tqps(struct hclge_dev *hdev) static int hclge_alloc_tqps(struct hclge_dev *hdev)
{ {
struct hclge_tqp *tqp; struct hclge_tqp *tqp;
...@@ -7090,6 +7112,10 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) ...@@ -7090,6 +7112,10 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
goto err_mdiobus_unreg; goto err_mdiobus_unreg;
} }
ret = hclge_config_gro(hdev, true);
if (ret)
goto err_mdiobus_unreg;
ret = hclge_init_vlan_config(hdev); ret = hclge_init_vlan_config(hdev);
if (ret) { if (ret) {
dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
...@@ -7221,6 +7247,10 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) ...@@ -7221,6 +7247,10 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
return ret; return ret;
} }
ret = hclge_config_gro(hdev, true);
if (ret)
return ret;
ret = hclge_init_vlan_config(hdev); ret = hclge_init_vlan_config(hdev);
if (ret) { if (ret) {
dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
...@@ -7637,6 +7667,14 @@ static void hclge_get_link_mode(struct hnae3_handle *handle, ...@@ -7637,6 +7667,14 @@ static void hclge_get_link_mode(struct hnae3_handle *handle,
} }
} }
static int hclge_gro_en(struct hnae3_handle *handle, int enable)
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
return hclge_config_gro(hdev, enable);
}
static const struct hnae3_ae_ops hclge_ops = { static const struct hnae3_ae_ops hclge_ops = {
.init_ae_dev = hclge_init_ae_dev, .init_ae_dev = hclge_init_ae_dev,
.uninit_ae_dev = hclge_uninit_ae_dev, .uninit_ae_dev = hclge_uninit_ae_dev,
...@@ -7708,6 +7746,7 @@ static const struct hnae3_ae_ops hclge_ops = { ...@@ -7708,6 +7746,7 @@ static const struct hnae3_ae_ops hclge_ops = {
.get_hw_reset_stat = hclge_get_hw_reset_stat, .get_hw_reset_stat = hclge_get_hw_reset_stat,
.ae_dev_resetting = hclge_ae_dev_resetting, .ae_dev_resetting = hclge_ae_dev_resetting,
.ae_dev_reset_cnt = hclge_ae_dev_reset_cnt, .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt,
.set_gro_en = hclge_gro_en,
}; };
static struct hnae3_ae_algo ae_algo = { static struct hnae3_ae_algo ae_algo = {
......
...@@ -87,6 +87,8 @@ enum hclgevf_opcode_type { ...@@ -87,6 +87,8 @@ enum hclgevf_opcode_type {
HCLGEVF_OPC_QUERY_TX_STATUS = 0x0B03, HCLGEVF_OPC_QUERY_TX_STATUS = 0x0B03,
HCLGEVF_OPC_QUERY_RX_STATUS = 0x0B13, HCLGEVF_OPC_QUERY_RX_STATUS = 0x0B13,
HCLGEVF_OPC_CFG_COM_TQP_QUEUE = 0x0B20, HCLGEVF_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
/* GRO command */
HCLGEVF_OPC_GRO_GENERIC_CONFIG = 0x0C10,
/* RSS cmd */ /* RSS cmd */
HCLGEVF_OPC_RSS_GENERIC_CONFIG = 0x0D01, HCLGEVF_OPC_RSS_GENERIC_CONFIG = 0x0D01,
HCLGEVF_OPC_RSS_INPUT_TUPLE = 0x0D02, HCLGEVF_OPC_RSS_INPUT_TUPLE = 0x0D02,
...@@ -149,6 +151,12 @@ struct hclgevf_query_res_cmd { ...@@ -149,6 +151,12 @@ struct hclgevf_query_res_cmd {
__le16 rsv[7]; __le16 rsv[7];
}; };
#define HCLGEVF_GRO_EN_B 0
struct hclgevf_cfg_gro_status_cmd {
__le16 gro_en;
u8 rsv[22];
};
#define HCLGEVF_RSS_DEFAULT_OUTPORT_B 4 #define HCLGEVF_RSS_DEFAULT_OUTPORT_B 4
#define HCLGEVF_RSS_HASH_KEY_OFFSET_B 4 #define HCLGEVF_RSS_HASH_KEY_OFFSET_B 4
#define HCLGEVF_RSS_HASH_KEY_NUM 16 #define HCLGEVF_RSS_HASH_KEY_NUM 16
......
...@@ -1655,6 +1655,29 @@ static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) ...@@ -1655,6 +1655,29 @@ static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
return 0; return 0;
} }
static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en)
{
struct hclgevf_cfg_gro_status_cmd *req;
struct hclgevf_desc desc;
int ret;
if (!hnae3_dev_gro_supported(hdev))
return 0;
hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG,
false);
req = (struct hclgevf_cfg_gro_status_cmd *)desc.data;
req->gro_en = cpu_to_le16(en ? 1 : 0);
ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
if (ret)
dev_err(&hdev->pdev->dev,
"VF GRO hardware config cmd failed, ret = %d.\n", ret);
return ret;
}
static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)
{ {
struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
...@@ -2122,6 +2145,10 @@ static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) ...@@ -2122,6 +2145,10 @@ static int hclgevf_reset_hdev(struct hclgevf_dev *hdev)
return ret; return ret;
} }
ret = hclgevf_config_gro(hdev, true);
if (ret)
return ret;
ret = hclgevf_init_vlan_config(hdev); ret = hclgevf_init_vlan_config(hdev);
if (ret) { if (ret) {
dev_err(&hdev->pdev->dev, dev_err(&hdev->pdev->dev,
...@@ -2199,6 +2226,10 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev) ...@@ -2199,6 +2226,10 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
goto err_config; goto err_config;
} }
ret = hclgevf_config_gro(hdev, true);
if (ret)
goto err_config;
/* Initialize RSS for this VF */ /* Initialize RSS for this VF */
ret = hclgevf_rss_init_hw(hdev); ret = hclgevf_rss_init_hw(hdev);
if (ret) { if (ret) {
...@@ -2337,6 +2368,13 @@ void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, ...@@ -2337,6 +2368,13 @@ void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
hdev->hw.mac.duplex = duplex; hdev->hw.mac.duplex = duplex;
} }
static int hclgevf_gro_en(struct hnae3_handle *handle, int enable)
{
struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
return hclgevf_config_gro(hdev, enable);
}
static void hclgevf_get_media_type(struct hnae3_handle *handle, static void hclgevf_get_media_type(struct hnae3_handle *handle,
u8 *media_type) u8 *media_type)
{ {
...@@ -2411,6 +2449,7 @@ static const struct hnae3_ae_ops hclgevf_ops = { ...@@ -2411,6 +2449,7 @@ static const struct hnae3_ae_ops hclgevf_ops = {
.get_hw_reset_stat = hclgevf_get_hw_reset_stat, .get_hw_reset_stat = hclgevf_get_hw_reset_stat,
.ae_dev_resetting = hclgevf_ae_dev_resetting, .ae_dev_resetting = hclgevf_ae_dev_resetting,
.ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt,
.set_gro_en = hclgevf_gro_en,
}; };
static struct hnae3_ae_algo ae_algovf = { static struct hnae3_ae_algo ae_algovf = {
......
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