Commit bda65b42 authored by David S. Miller's avatar David S. Miller

Merge tag 'mlx5-4kuar-for-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux

Saeed Mahameed says:

====================
mlx5 4K UAR

The following series of patches optimizes the usage of the UAR area which is
contained within the BAR 0-1. Previous versions of the firmware and the driver
assumed each system page contains a single UAR. This patch set will query the
firmware for a new capability that if published, means that the firmware can
support UARs of fixed 4K regardless of system page size. In the case of
powerpc, where page size equals 64KB, this means we can utilize 16 UARs per
system page. Since user space processes by default consume eight UARs per
context this means that with this change a process will need a single system
page to fulfill that requirement and in fact make use of more UARs which is
better in terms of performance.

In addition to optimizing user-space processes, we introduce an allocator
that can be used by kernel consumers to allocate blue flame registers
(which are areas within a UAR that are used to write doorbells). This provides
further optimization on using the UAR area since the Ethernet driver makes
use of a single blue flame register per system page and now it will use two
blue flame registers per 4K.

The series also makes changes to naming conventions and now the terms used in
the driver code match the terms used in the PRM (programmers reference manual).
Thus, what used to be called UUAR (micro UAR) is now called BFREG (blue flame
register).

In order to support compatibility between different versions of
library/driver/firmware, the library has now means to notify the kernel driver
that it supports the new scheme and the kernel can notify the library if it
supports this extension. So mixed versions of libraries can run concurrently
without any issues.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents b369e7fd f502d834
...@@ -689,7 +689,7 @@ int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) ...@@ -689,7 +689,7 @@ int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
{ {
struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev; struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev;
struct mlx5_ib_cq *cq = to_mcq(ibcq); struct mlx5_ib_cq *cq = to_mcq(ibcq);
void __iomem *uar_page = mdev->priv.uuari.uars[0].map; void __iomem *uar_page = mdev->priv.uar->map;
unsigned long irq_flags; unsigned long irq_flags;
int ret = 0; int ret = 0;
...@@ -704,9 +704,7 @@ int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) ...@@ -704,9 +704,7 @@ int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
mlx5_cq_arm(&cq->mcq, mlx5_cq_arm(&cq->mcq,
(flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT, MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT,
uar_page, uar_page, to_mcq(ibcq)->mcq.cons_index);
MLX5_GET_DOORBELL_LOCK(&mdev->priv.cq_uar_lock),
to_mcq(ibcq)->mcq.cons_index);
return ret; return ret;
} }
...@@ -790,7 +788,7 @@ static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata, ...@@ -790,7 +788,7 @@ static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
MLX5_SET(cqc, cqc, log_page_size, MLX5_SET(cqc, cqc, log_page_size,
page_shift - MLX5_ADAPTER_PAGE_SHIFT); page_shift - MLX5_ADAPTER_PAGE_SHIFT);
*index = to_mucontext(context)->uuari.uars[0].index; *index = to_mucontext(context)->bfregi.sys_pages[0];
if (ucmd.cqe_comp_en == 1) { if (ucmd.cqe_comp_en == 1) {
if (unlikely((*cqe_size != 64) || if (unlikely((*cqe_size != 64) ||
...@@ -886,7 +884,7 @@ static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, ...@@ -886,7 +884,7 @@ static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
MLX5_SET(cqc, cqc, log_page_size, MLX5_SET(cqc, cqc, log_page_size,
cq->buf.buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); cq->buf.buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
*index = dev->mdev->priv.uuari.uars[0].index; *index = dev->mdev->priv.uar->index;
return 0; return 0;
......
This diff is collapsed.
...@@ -90,7 +90,6 @@ enum mlx5_ib_latency_class { ...@@ -90,7 +90,6 @@ enum mlx5_ib_latency_class {
MLX5_IB_LATENCY_CLASS_LOW, MLX5_IB_LATENCY_CLASS_LOW,
MLX5_IB_LATENCY_CLASS_MEDIUM, MLX5_IB_LATENCY_CLASS_MEDIUM,
MLX5_IB_LATENCY_CLASS_HIGH, MLX5_IB_LATENCY_CLASS_HIGH,
MLX5_IB_LATENCY_CLASS_FAST_PATH
}; };
enum mlx5_ib_mad_ifc_flags { enum mlx5_ib_mad_ifc_flags {
...@@ -100,7 +99,7 @@ enum mlx5_ib_mad_ifc_flags { ...@@ -100,7 +99,7 @@ enum mlx5_ib_mad_ifc_flags {
}; };
enum { enum {
MLX5_CROSS_CHANNEL_UUAR = 0, MLX5_CROSS_CHANNEL_BFREG = 0,
}; };
enum { enum {
...@@ -120,7 +119,7 @@ struct mlx5_ib_ucontext { ...@@ -120,7 +119,7 @@ struct mlx5_ib_ucontext {
/* protect doorbell record alloc/free /* protect doorbell record alloc/free
*/ */
struct mutex db_page_mutex; struct mutex db_page_mutex;
struct mlx5_uuar_info uuari; struct mlx5_bfreg_info bfregi;
u8 cqe_version; u8 cqe_version;
/* Transport Domain number */ /* Transport Domain number */
u32 tdn; u32 tdn;
...@@ -129,6 +128,7 @@ struct mlx5_ib_ucontext { ...@@ -129,6 +128,7 @@ struct mlx5_ib_ucontext {
unsigned long upd_xlt_page; unsigned long upd_xlt_page;
/* protect ODP/KSM */ /* protect ODP/KSM */
struct mutex upd_xlt_page_mutex; struct mutex upd_xlt_page_mutex;
u64 lib_caps;
}; };
static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
...@@ -324,6 +324,12 @@ struct mlx5_ib_raw_packet_qp { ...@@ -324,6 +324,12 @@ struct mlx5_ib_raw_packet_qp {
struct mlx5_ib_rq rq; struct mlx5_ib_rq rq;
}; };
struct mlx5_bf {
int buf_size;
unsigned long offset;
struct mlx5_sq_bfreg *bfreg;
};
struct mlx5_ib_qp { struct mlx5_ib_qp {
struct ib_qp ibqp; struct ib_qp ibqp;
union { union {
...@@ -349,13 +355,13 @@ struct mlx5_ib_qp { ...@@ -349,13 +355,13 @@ struct mlx5_ib_qp {
int wq_sig; int wq_sig;
int scat_cqe; int scat_cqe;
int max_inline_data; int max_inline_data;
struct mlx5_bf *bf; struct mlx5_bf bf;
int has_rq; int has_rq;
/* only for user space QPs. For kernel /* only for user space QPs. For kernel
* we have it from the bf object * we have it from the bf object
*/ */
int uuarn; int bfregn;
int create_type; int create_type;
...@@ -591,7 +597,6 @@ struct mlx5_ib_dev { ...@@ -591,7 +597,6 @@ struct mlx5_ib_dev {
struct ib_device ib_dev; struct ib_device ib_dev;
struct mlx5_core_dev *mdev; struct mlx5_core_dev *mdev;
struct mlx5_roce roce; struct mlx5_roce roce;
MLX5_DECLARE_DOORBELL_LOCK(uar_lock);
int num_ports; int num_ports;
/* serialize update of capability mask /* serialize update of capability mask
*/ */
...@@ -621,6 +626,8 @@ struct mlx5_ib_dev { ...@@ -621,6 +626,8 @@ struct mlx5_ib_dev {
struct list_head qp_list; struct list_head qp_list;
/* Array with num_ports elements */ /* Array with num_ports elements */
struct mlx5_ib_port *port; struct mlx5_ib_port *port;
struct mlx5_sq_bfreg bfreg;
struct mlx5_sq_bfreg fp_bfreg;
}; };
static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
...@@ -968,4 +975,17 @@ static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, ...@@ -968,4 +975,17 @@ static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext,
return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
} }
static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support)
{
return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ?
MLX5_UARS_IN_PAGE : 1;
}
static inline int get_num_uars(struct mlx5_ib_dev *dev,
struct mlx5_bfreg_info *bfregi)
{
return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_sys_pages;
}
#endif /* MLX5_IB_H */ #endif /* MLX5_IB_H */
This diff is collapsed.
...@@ -179,6 +179,8 @@ int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, ...@@ -179,6 +179,8 @@ int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
mlx5_core_dbg(dev, "failed adding CP 0x%x to debug file system\n", mlx5_core_dbg(dev, "failed adding CP 0x%x to debug file system\n",
cq->cqn); cq->cqn);
cq->uar = dev->priv.uar;
return 0; return 0;
err_cmd: err_cmd:
......
...@@ -465,7 +465,6 @@ struct mlx5e_sq { ...@@ -465,7 +465,6 @@ struct mlx5e_sq {
/* read only */ /* read only */
struct mlx5_wq_cyc wq; struct mlx5_wq_cyc wq;
u32 dma_fifo_mask; u32 dma_fifo_mask;
void __iomem *uar_map;
struct netdev_queue *txq; struct netdev_queue *txq;
u32 sqn; u32 sqn;
u16 bf_buf_size; u16 bf_buf_size;
...@@ -479,7 +478,7 @@ struct mlx5e_sq { ...@@ -479,7 +478,7 @@ struct mlx5e_sq {
/* control path */ /* control path */
struct mlx5_wq_ctrl wq_ctrl; struct mlx5_wq_ctrl wq_ctrl;
struct mlx5_uar uar; struct mlx5_sq_bfreg bfreg;
struct mlx5e_channel *channel; struct mlx5e_channel *channel;
int tc; int tc;
u32 rate_limit; u32 rate_limit;
...@@ -806,7 +805,7 @@ void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, ...@@ -806,7 +805,7 @@ void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz) struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
{ {
u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; u16 ofst = sq->bf_offset;
/* ensure wqe is visible to device before updating doorbell record */ /* ensure wqe is visible to device before updating doorbell record */
dma_wmb(); dma_wmb();
...@@ -818,9 +817,9 @@ static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, ...@@ -818,9 +817,9 @@ static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
*/ */
wmb(); wmb();
if (bf_sz) if (bf_sz)
__iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz); __iowrite64_copy(sq->bfreg.map + ofst, ctrl, bf_sz);
else else
mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL); mlx5_write64((__be32 *)ctrl, sq->bfreg.map + ofst, NULL);
/* flush the write-combining mapped buffer */ /* flush the write-combining mapped buffer */
wmb(); wmb();
...@@ -832,7 +831,7 @@ static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) ...@@ -832,7 +831,7 @@ static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
struct mlx5_core_cq *mcq; struct mlx5_core_cq *mcq;
mcq = &cq->mcq; mcq = &cq->mcq;
mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc); mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
} }
static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix) static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)
......
...@@ -89,16 +89,10 @@ int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev) ...@@ -89,16 +89,10 @@ int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev)
struct mlx5e_resources *res = &mdev->mlx5e_res; struct mlx5e_resources *res = &mdev->mlx5e_res;
int err; int err;
err = mlx5_alloc_map_uar(mdev, &res->cq_uar, false);
if (err) {
mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
return err;
}
err = mlx5_core_alloc_pd(mdev, &res->pdn); err = mlx5_core_alloc_pd(mdev, &res->pdn);
if (err) { if (err) {
mlx5_core_err(mdev, "alloc pd failed, %d\n", err); mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
goto err_unmap_free_uar; return err;
} }
err = mlx5_core_alloc_transport_domain(mdev, &res->td.tdn); err = mlx5_core_alloc_transport_domain(mdev, &res->td.tdn);
...@@ -121,9 +115,6 @@ int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev) ...@@ -121,9 +115,6 @@ int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev)
mlx5_core_dealloc_transport_domain(mdev, res->td.tdn); mlx5_core_dealloc_transport_domain(mdev, res->td.tdn);
err_dealloc_pd: err_dealloc_pd:
mlx5_core_dealloc_pd(mdev, res->pdn); mlx5_core_dealloc_pd(mdev, res->pdn);
err_unmap_free_uar:
mlx5_unmap_free_uar(mdev, &res->cq_uar);
return err; return err;
} }
...@@ -134,7 +125,6 @@ void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev) ...@@ -134,7 +125,6 @@ void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev)
mlx5_core_destroy_mkey(mdev, &res->mkey); mlx5_core_destroy_mkey(mdev, &res->mkey);
mlx5_core_dealloc_transport_domain(mdev, res->td.tdn); mlx5_core_dealloc_transport_domain(mdev, res->td.tdn);
mlx5_core_dealloc_pd(mdev, res->pdn); mlx5_core_dealloc_pd(mdev, res->pdn);
mlx5_unmap_free_uar(mdev, &res->cq_uar);
} }
int mlx5e_refresh_tirs_self_loopback(struct mlx5_core_dev *mdev, int mlx5e_refresh_tirs_self_loopback(struct mlx5_core_dev *mdev,
......
...@@ -967,7 +967,7 @@ static int mlx5e_create_sq(struct mlx5e_channel *c, ...@@ -967,7 +967,7 @@ static int mlx5e_create_sq(struct mlx5e_channel *c,
sq->channel = c; sq->channel = c;
sq->tc = tc; sq->tc = tc;
err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf)); err = mlx5_alloc_bfreg(mdev, &sq->bfreg, MLX5_CAP_GEN(mdev, bf), false);
if (err) if (err)
return err; return err;
...@@ -979,12 +979,9 @@ static int mlx5e_create_sq(struct mlx5e_channel *c, ...@@ -979,12 +979,9 @@ static int mlx5e_create_sq(struct mlx5e_channel *c,
goto err_unmap_free_uar; goto err_unmap_free_uar;
sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
if (sq->uar.bf_map) { if (sq->bfreg.wc)
set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state); set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
sq->uar_map = sq->uar.bf_map;
} else {
sq->uar_map = sq->uar.map;
}
sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
sq->max_inline = param->max_inline; sq->max_inline = param->max_inline;
sq->min_inline_mode = sq->min_inline_mode =
...@@ -1012,7 +1009,7 @@ static int mlx5e_create_sq(struct mlx5e_channel *c, ...@@ -1012,7 +1009,7 @@ static int mlx5e_create_sq(struct mlx5e_channel *c,
mlx5_wq_destroy(&sq->wq_ctrl); mlx5_wq_destroy(&sq->wq_ctrl);
err_unmap_free_uar: err_unmap_free_uar:
mlx5_unmap_free_uar(mdev, &sq->uar); mlx5_free_bfreg(mdev, &sq->bfreg);
return err; return err;
} }
...@@ -1024,7 +1021,7 @@ static void mlx5e_destroy_sq(struct mlx5e_sq *sq) ...@@ -1024,7 +1021,7 @@ static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
mlx5e_free_sq_db(sq); mlx5e_free_sq_db(sq);
mlx5_wq_destroy(&sq->wq_ctrl); mlx5_wq_destroy(&sq->wq_ctrl);
mlx5_unmap_free_uar(priv->mdev, &sq->uar); mlx5_free_bfreg(priv->mdev, &sq->bfreg);
} }
static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param) static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
...@@ -1058,7 +1055,7 @@ static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param) ...@@ -1058,7 +1055,7 @@ static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
MLX5_SET(sqc, sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1); MLX5_SET(sqc, sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
MLX5_SET(wq, wq, uar_page, sq->uar.index); MLX5_SET(wq, wq, uar_page, sq->bfreg.index);
MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
MLX5_ADAPTER_PAGE_SHIFT); MLX5_ADAPTER_PAGE_SHIFT);
MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
...@@ -1216,7 +1213,6 @@ static int mlx5e_create_cq(struct mlx5e_channel *c, ...@@ -1216,7 +1213,6 @@ static int mlx5e_create_cq(struct mlx5e_channel *c,
mcq->comp = mlx5e_completion_event; mcq->comp = mlx5e_completion_event;
mcq->event = mlx5e_cq_error_event; mcq->event = mlx5e_cq_error_event;
mcq->irqn = irqn; mcq->irqn = irqn;
mcq->uar = &mdev->mlx5e_res.cq_uar;
for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
...@@ -1265,7 +1261,7 @@ static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param) ...@@ -1265,7 +1261,7 @@ static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode); MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
MLX5_SET(cqc, cqc, c_eqn, eqn); MLX5_SET(cqc, cqc, c_eqn, eqn);
MLX5_SET(cqc, cqc, uar_page, mcq->uar->index); MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift - MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
MLX5_ADAPTER_PAGE_SHIFT); MLX5_ADAPTER_PAGE_SHIFT);
MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
...@@ -1677,7 +1673,7 @@ static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv, ...@@ -1677,7 +1673,7 @@ static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
{ {
void *cqc = param->cqc; void *cqc = param->cqc;
MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index); MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
} }
static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
...@@ -2296,7 +2292,6 @@ static int mlx5e_create_drop_cq(struct mlx5e_priv *priv, ...@@ -2296,7 +2292,6 @@ static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
mcq->comp = mlx5e_completion_event; mcq->comp = mlx5e_completion_event;
mcq->event = mlx5e_cq_error_event; mcq->event = mlx5e_cq_error_event;
mcq->irqn = irqn; mcq->irqn = irqn;
mcq->uar = &mdev->mlx5e_res.cq_uar;
cq->priv = priv; cq->priv = priv;
......
...@@ -512,7 +512,7 @@ static void init_eq_buf(struct mlx5_eq *eq) ...@@ -512,7 +512,7 @@ static void init_eq_buf(struct mlx5_eq *eq)
int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
int nent, u64 mask, const char *name, int nent, u64 mask, const char *name,
struct mlx5_uar *uar, enum mlx5_eq_type type) enum mlx5_eq_type type)
{ {
u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0}; u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0};
struct mlx5_priv *priv = &dev->priv; struct mlx5_priv *priv = &dev->priv;
...@@ -556,7 +556,7 @@ int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, ...@@ -556,7 +556,7 @@ int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry); eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry);
MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent)); MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent));
MLX5_SET(eqc, eqc, uar_page, uar->index); MLX5_SET(eqc, eqc, uar_page, priv->uar->index);
MLX5_SET(eqc, eqc, intr, vecidx); MLX5_SET(eqc, eqc, intr, vecidx);
MLX5_SET(eqc, eqc, log_page_size, MLX5_SET(eqc, eqc, log_page_size,
eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
...@@ -571,7 +571,7 @@ int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, ...@@ -571,7 +571,7 @@ int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
eq->eqn = MLX5_GET(create_eq_out, out, eq_number); eq->eqn = MLX5_GET(create_eq_out, out, eq_number);
eq->irqn = priv->msix_arr[vecidx].vector; eq->irqn = priv->msix_arr[vecidx].vector;
eq->dev = dev; eq->dev = dev;
eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET; eq->doorbell = priv->uar->map + MLX5_EQ_DOORBEL_OFFSET;
err = request_irq(eq->irqn, handler, 0, err = request_irq(eq->irqn, handler, 0,
priv->irq_info[vecidx].name, eq); priv->irq_info[vecidx].name, eq);
if (err) if (err)
...@@ -686,8 +686,7 @@ int mlx5_start_eqs(struct mlx5_core_dev *dev) ...@@ -686,8 +686,7 @@ int mlx5_start_eqs(struct mlx5_core_dev *dev)
err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD, err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD, MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
"mlx5_cmd_eq", &dev->priv.uuari.uars[0], "mlx5_cmd_eq", MLX5_EQ_TYPE_ASYNC);
MLX5_EQ_TYPE_ASYNC);
if (err) { if (err) {
mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err); mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
return err; return err;
...@@ -697,8 +696,7 @@ int mlx5_start_eqs(struct mlx5_core_dev *dev) ...@@ -697,8 +696,7 @@ int mlx5_start_eqs(struct mlx5_core_dev *dev)
err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC, err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
MLX5_NUM_ASYNC_EQE, async_event_mask, MLX5_NUM_ASYNC_EQE, async_event_mask,
"mlx5_async_eq", &dev->priv.uuari.uars[0], "mlx5_async_eq", MLX5_EQ_TYPE_ASYNC);
MLX5_EQ_TYPE_ASYNC);
if (err) { if (err) {
mlx5_core_warn(dev, "failed to create async EQ %d\n", err); mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
goto err1; goto err1;
...@@ -708,7 +706,6 @@ int mlx5_start_eqs(struct mlx5_core_dev *dev) ...@@ -708,7 +706,6 @@ int mlx5_start_eqs(struct mlx5_core_dev *dev)
MLX5_EQ_VEC_PAGES, MLX5_EQ_VEC_PAGES,
/* TODO: sriov max_vf + */ 1, /* TODO: sriov max_vf + */ 1,
1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq", 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq",
&dev->priv.uuari.uars[0],
MLX5_EQ_TYPE_ASYNC); MLX5_EQ_TYPE_ASYNC);
if (err) { if (err) {
mlx5_core_warn(dev, "failed to create pages EQ %d\n", err); mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
...@@ -722,7 +719,6 @@ int mlx5_start_eqs(struct mlx5_core_dev *dev) ...@@ -722,7 +719,6 @@ int mlx5_start_eqs(struct mlx5_core_dev *dev)
MLX5_NUM_ASYNC_EQE, MLX5_NUM_ASYNC_EQE,
1 << MLX5_EVENT_TYPE_PAGE_FAULT, 1 << MLX5_EVENT_TYPE_PAGE_FAULT,
"mlx5_page_fault_eq", "mlx5_page_fault_eq",
&dev->priv.uuari.uars[0],
MLX5_EQ_TYPE_PF); MLX5_EQ_TYPE_PF);
if (err) { if (err) {
mlx5_core_warn(dev, "failed to create page fault EQ %d\n", mlx5_core_warn(dev, "failed to create page fault EQ %d\n",
......
...@@ -537,6 +537,10 @@ static int handle_hca_cap(struct mlx5_core_dev *dev) ...@@ -537,6 +537,10 @@ static int handle_hca_cap(struct mlx5_core_dev *dev)
/* disable cmdif checksum */ /* disable cmdif checksum */
MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
/* If the HCA supports 4K UARs use it */
if (MLX5_CAP_GEN_MAX(dev, uar_4k))
MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
err = set_caps(dev, set_ctx, set_sz, err = set_caps(dev, set_ctx, set_sz,
...@@ -759,8 +763,7 @@ static int alloc_comp_eqs(struct mlx5_core_dev *dev) ...@@ -759,8 +763,7 @@ static int alloc_comp_eqs(struct mlx5_core_dev *dev)
snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i); snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
err = mlx5_create_map_eq(dev, eq, err = mlx5_create_map_eq(dev, eq,
i + MLX5_EQ_VEC_COMP_BASE, nent, 0, i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
name, &dev->priv.uuari.uars[0], name, MLX5_EQ_TYPE_COMP);
MLX5_EQ_TYPE_COMP);
if (err) { if (err) {
kfree(eq); kfree(eq);
goto clean; goto clean;
...@@ -920,8 +923,6 @@ static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv) ...@@ -920,8 +923,6 @@ static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
goto out; goto out;
} }
MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
err = mlx5_init_cq_table(dev); err = mlx5_init_cq_table(dev);
if (err) { if (err) {
dev_err(&pdev->dev, "failed to initialize cq table\n"); dev_err(&pdev->dev, "failed to initialize cq table\n");
...@@ -1100,8 +1101,8 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, ...@@ -1100,8 +1101,8 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
goto err_cleanup_once; goto err_cleanup_once;
} }
err = mlx5_alloc_uuars(dev, &priv->uuari); dev->priv.uar = mlx5_get_uars_page(dev);
if (err) { if (!dev->priv.uar) {
dev_err(&pdev->dev, "Failed allocating uar, aborting\n"); dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
goto err_disable_msix; goto err_disable_msix;
} }
...@@ -1109,7 +1110,7 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, ...@@ -1109,7 +1110,7 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
err = mlx5_start_eqs(dev); err = mlx5_start_eqs(dev);
if (err) { if (err) {
dev_err(&pdev->dev, "Failed to start pages and async EQs\n"); dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
goto err_free_uar; goto err_put_uars;
} }
err = alloc_comp_eqs(dev); err = alloc_comp_eqs(dev);
...@@ -1175,8 +1176,8 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, ...@@ -1175,8 +1176,8 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
err_stop_eqs: err_stop_eqs:
mlx5_stop_eqs(dev); mlx5_stop_eqs(dev);
err_free_uar: err_put_uars:
mlx5_free_uuars(dev, &priv->uuari); mlx5_put_uars_page(dev, priv->uar);
err_disable_msix: err_disable_msix:
mlx5_disable_msix(dev); mlx5_disable_msix(dev);
...@@ -1238,7 +1239,7 @@ static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, ...@@ -1238,7 +1239,7 @@ static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
mlx5_irq_clear_affinity_hints(dev); mlx5_irq_clear_affinity_hints(dev);
free_comp_eqs(dev); free_comp_eqs(dev);
mlx5_stop_eqs(dev); mlx5_stop_eqs(dev);
mlx5_free_uuars(dev, &priv->uuari); mlx5_put_uars_page(dev, priv->uar);
mlx5_disable_msix(dev); mlx5_disable_msix(dev);
if (cleanup) if (cleanup)
mlx5_cleanup_once(dev); mlx5_cleanup_once(dev);
...@@ -1313,6 +1314,11 @@ static int init_one(struct pci_dev *pdev, ...@@ -1313,6 +1314,11 @@ static int init_one(struct pci_dev *pdev,
goto clean_dev; goto clean_dev;
} }
#endif #endif
mutex_init(&priv->bfregs.reg_head.lock);
mutex_init(&priv->bfregs.wc_head.lock);
INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
err = mlx5_pci_init(dev, priv); err = mlx5_pci_init(dev, priv);
if (err) { if (err) {
dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err); dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
......
...@@ -42,13 +42,13 @@ struct mlx5_core_cq { ...@@ -42,13 +42,13 @@ struct mlx5_core_cq {
int cqe_sz; int cqe_sz;
__be32 *set_ci_db; __be32 *set_ci_db;
__be32 *arm_db; __be32 *arm_db;
struct mlx5_uars_page *uar;
atomic_t refcount; atomic_t refcount;
struct completion free; struct completion free;
unsigned vector; unsigned vector;
unsigned int irqn; unsigned int irqn;
void (*comp) (struct mlx5_core_cq *); void (*comp) (struct mlx5_core_cq *);
void (*event) (struct mlx5_core_cq *, enum mlx5_event); void (*event) (struct mlx5_core_cq *, enum mlx5_event);
struct mlx5_uar *uar;
u32 cons_index; u32 cons_index;
unsigned arm_sn; unsigned arm_sn;
struct mlx5_rsc_debug *dbg; struct mlx5_rsc_debug *dbg;
...@@ -144,7 +144,6 @@ enum { ...@@ -144,7 +144,6 @@ enum {
static inline void mlx5_cq_arm(struct mlx5_core_cq *cq, u32 cmd, static inline void mlx5_cq_arm(struct mlx5_core_cq *cq, u32 cmd,
void __iomem *uar_page, void __iomem *uar_page,
spinlock_t *doorbell_lock,
u32 cons_index) u32 cons_index)
{ {
__be32 doorbell[2]; __be32 doorbell[2];
...@@ -164,7 +163,7 @@ static inline void mlx5_cq_arm(struct mlx5_core_cq *cq, u32 cmd, ...@@ -164,7 +163,7 @@ static inline void mlx5_cq_arm(struct mlx5_core_cq *cq, u32 cmd,
doorbell[0] = cpu_to_be32(sn << 28 | cmd | ci); doorbell[0] = cpu_to_be32(sn << 28 | cmd | ci);
doorbell[1] = cpu_to_be32(cq->cqn); doorbell[1] = cpu_to_be32(cq->cqn);
mlx5_write64(doorbell, uar_page + MLX5_CQ_DOORBELL, doorbell_lock); mlx5_write64(doorbell, uar_page + MLX5_CQ_DOORBELL, NULL);
} }
int mlx5_init_cq_table(struct mlx5_core_dev *dev); int mlx5_init_cq_table(struct mlx5_core_dev *dev);
......
...@@ -212,10 +212,20 @@ enum { ...@@ -212,10 +212,20 @@ enum {
}; };
enum { enum {
MLX5_BF_REGS_PER_PAGE = 4, MLX5_ADAPTER_PAGE_SHIFT = 12,
MLX5_MAX_UAR_PAGES = 1 << 8, MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
MLX5_NON_FP_BF_REGS_PER_PAGE = 2, };
MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
enum {
MLX5_BFREGS_PER_UAR = 4,
MLX5_MAX_UARS = 1 << 8,
MLX5_NON_FP_BFREGS_PER_UAR = 2,
MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
MLX5_NON_FP_BFREGS_PER_UAR,
MLX5_MAX_BFREGS = MLX5_MAX_UARS *
MLX5_NON_FP_BFREGS_PER_UAR,
MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
}; };
enum { enum {
...@@ -388,11 +398,6 @@ enum { ...@@ -388,11 +398,6 @@ enum {
MLX5_MAX_PAGE_SHIFT = 31 MLX5_MAX_PAGE_SHIFT = 31
}; };
enum {
MLX5_ADAPTER_PAGE_SHIFT = 12,
MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
};
enum { enum {
MLX5_CAP_OFF_CMDIF_CSUM = 46, MLX5_CAP_OFF_CMDIF_CSUM = 46,
}; };
......
...@@ -68,10 +68,12 @@ static inline void mlx5_write64(__be32 val[2], void __iomem *dest, ...@@ -68,10 +68,12 @@ static inline void mlx5_write64(__be32 val[2], void __iomem *dest,
{ {
unsigned long flags; unsigned long flags;
spin_lock_irqsave(doorbell_lock, flags); if (doorbell_lock)
spin_lock_irqsave(doorbell_lock, flags);
__raw_writel((__force u32) val[0], dest); __raw_writel((__force u32) val[0], dest);
__raw_writel((__force u32) val[1], dest + 4); __raw_writel((__force u32) val[1], dest + 4);
spin_unlock_irqrestore(doorbell_lock, flags); if (doorbell_lock)
spin_unlock_irqrestore(doorbell_lock, flags);
} }
#endif #endif
......
...@@ -187,36 +187,18 @@ enum mlx5_eq_type { ...@@ -187,36 +187,18 @@ enum mlx5_eq_type {
#endif #endif
}; };
struct mlx5_uuar_info { struct mlx5_bfreg_info {
struct mlx5_uar *uars; u32 *sys_pages;
int num_uars; int num_low_latency_bfregs;
int num_low_latency_uuars;
unsigned long *bitmap;
unsigned int *count; unsigned int *count;
struct mlx5_bf *bfs;
/* /*
* protect uuar allocation data structs * protect bfreg allocation data structs
*/ */
struct mutex lock; struct mutex lock;
u32 ver; u32 ver;
}; bool lib_uar_4k;
u32 num_sys_pages;
struct mlx5_bf {
void __iomem *reg;
void __iomem *regreg;
int buf_size;
struct mlx5_uar *uar;
unsigned long offset;
int need_lock;
/* protect blue flame buffer selection when needed
*/
spinlock_t lock;
/* serialize 64 bit writes when done as two 32 bit accesses
*/
spinlock_t lock32;
int uuarn;
}; };
struct mlx5_cmd_first { struct mlx5_cmd_first {
...@@ -451,14 +433,38 @@ struct mlx5_eq_table { ...@@ -451,14 +433,38 @@ struct mlx5_eq_table {
spinlock_t lock; spinlock_t lock;
}; };
struct mlx5_uar { struct mlx5_uars_page {
u32 index;
struct list_head bf_list;
unsigned free_bf_bmap;
void __iomem *bf_map;
void __iomem *map; void __iomem *map;
bool wc;
u32 index;
struct list_head list;
unsigned int bfregs;
unsigned long *reg_bitmap; /* for non fast path bf regs */
unsigned long *fp_bitmap;
unsigned int reg_avail;
unsigned int fp_avail;
struct kref ref_count;
struct mlx5_core_dev *mdev;
}; };
struct mlx5_bfreg_head {
/* protect blue flame registers allocations */
struct mutex lock;
struct list_head list;
};
struct mlx5_bfreg_data {
struct mlx5_bfreg_head reg_head;
struct mlx5_bfreg_head wc_head;
};
struct mlx5_sq_bfreg {
void __iomem *map;
struct mlx5_uars_page *up;
bool wc;
u32 index;
unsigned int offset;
};
struct mlx5_core_health { struct mlx5_core_health {
struct health_buffer __iomem *health; struct health_buffer __iomem *health;
...@@ -578,8 +584,6 @@ struct mlx5_priv { ...@@ -578,8 +584,6 @@ struct mlx5_priv {
struct mlx5_eq_table eq_table; struct mlx5_eq_table eq_table;
struct msix_entry *msix_arr; struct msix_entry *msix_arr;
struct mlx5_irq_info *irq_info; struct mlx5_irq_info *irq_info;
struct mlx5_uuar_info uuari;
MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
/* pages stuff */ /* pages stuff */
struct workqueue_struct *pg_wq; struct workqueue_struct *pg_wq;
...@@ -644,6 +648,8 @@ struct mlx5_priv { ...@@ -644,6 +648,8 @@ struct mlx5_priv {
void *pfault_ctx; void *pfault_ctx;
struct srcu_struct pfault_srcu; struct srcu_struct pfault_srcu;
#endif #endif
struct mlx5_bfreg_data bfregs;
struct mlx5_uars_page *uar;
}; };
enum mlx5_device_state { enum mlx5_device_state {
...@@ -712,7 +718,6 @@ struct mlx5_td { ...@@ -712,7 +718,6 @@ struct mlx5_td {
}; };
struct mlx5e_resources { struct mlx5e_resources {
struct mlx5_uar cq_uar;
u32 pdn; u32 pdn;
struct mlx5_td td; struct mlx5_td td;
struct mlx5_core_mkey mkey; struct mlx5_core_mkey mkey;
...@@ -902,11 +907,6 @@ void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); ...@@ -902,11 +907,6 @@ void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar,
bool map_wc);
void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
void mlx5_health_cleanup(struct mlx5_core_dev *dev); void mlx5_health_cleanup(struct mlx5_core_dev *dev);
int mlx5_health_init(struct mlx5_core_dev *dev); int mlx5_health_init(struct mlx5_core_dev *dev);
void mlx5_start_health_poll(struct mlx5_core_dev *dev); void mlx5_start_health_poll(struct mlx5_core_dev *dev);
...@@ -972,7 +972,7 @@ void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec); ...@@ -972,7 +972,7 @@ void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec);
void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
int nent, u64 mask, const char *name, int nent, u64 mask, const char *name,
struct mlx5_uar *uar, enum mlx5_eq_type type); enum mlx5_eq_type type);
int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
int mlx5_start_eqs(struct mlx5_core_dev *dev); int mlx5_start_eqs(struct mlx5_core_dev *dev);
int mlx5_stop_eqs(struct mlx5_core_dev *dev); int mlx5_stop_eqs(struct mlx5_core_dev *dev);
...@@ -1021,6 +1021,9 @@ void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); ...@@ -1021,6 +1021,9 @@ void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index); int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index);
void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate); void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate);
bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
bool map_wc, bool fast_path);
void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
static inline int fw_initializing(struct mlx5_core_dev *dev) static inline int fw_initializing(struct mlx5_core_dev *dev)
{ {
...@@ -1080,6 +1083,8 @@ int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); ...@@ -1080,6 +1083,8 @@ int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
bool mlx5_lag_is_active(struct mlx5_core_dev *dev); bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
struct mlx5_profile { struct mlx5_profile {
u64 mask; u64 mask;
......
...@@ -905,7 +905,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { ...@@ -905,7 +905,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 uc[0x1]; u8 uc[0x1];
u8 rc[0x1]; u8 rc[0x1];
u8 reserved_at_240[0xa]; u8 uar_4k[0x1];
u8 reserved_at_241[0x9];
u8 uar_sz[0x6]; u8 uar_sz[0x6];
u8 reserved_at_250[0x8]; u8 reserved_at_250[0x8];
u8 log_pg_sz[0x8]; u8 log_pg_sz[0x8];
...@@ -997,7 +998,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { ...@@ -997,7 +998,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 device_frequency_mhz[0x20]; u8 device_frequency_mhz[0x20];
u8 device_frequency_khz[0x20]; u8 device_frequency_khz[0x20];
u8 reserved_at_500[0x80]; u8 reserved_at_500[0x20];
u8 num_of_uars_per_page[0x20];
u8 reserved_at_540[0x40];
u8 reserved_at_580[0x3f]; u8 reserved_at_580[0x3f];
u8 cqe_compression[0x1]; u8 cqe_compression[0x1];
......
...@@ -61,19 +61,24 @@ enum { ...@@ -61,19 +61,24 @@ enum {
*/ */
struct mlx5_ib_alloc_ucontext_req { struct mlx5_ib_alloc_ucontext_req {
__u32 total_num_uuars; __u32 total_num_bfregs;
__u32 num_low_latency_uuars; __u32 num_low_latency_bfregs;
};
enum mlx5_lib_caps {
MLX5_LIB_CAP_4K_UAR = (u64)1 << 0,
}; };
struct mlx5_ib_alloc_ucontext_req_v2 { struct mlx5_ib_alloc_ucontext_req_v2 {
__u32 total_num_uuars; __u32 total_num_bfregs;
__u32 num_low_latency_uuars; __u32 num_low_latency_bfregs;
__u32 flags; __u32 flags;
__u32 comp_mask; __u32 comp_mask;
__u8 max_cqe_version; __u8 max_cqe_version;
__u8 reserved0; __u8 reserved0;
__u16 reserved1; __u16 reserved1;
__u32 reserved2; __u32 reserved2;
__u64 lib_caps;
}; };
enum mlx5_ib_alloc_ucontext_resp_mask { enum mlx5_ib_alloc_ucontext_resp_mask {
...@@ -88,7 +93,7 @@ enum mlx5_user_cmds_supp_uhw { ...@@ -88,7 +93,7 @@ enum mlx5_user_cmds_supp_uhw {
struct mlx5_ib_alloc_ucontext_resp { struct mlx5_ib_alloc_ucontext_resp {
__u32 qp_tab_size; __u32 qp_tab_size;
__u32 bf_reg_size; __u32 bf_reg_size;
__u32 tot_uuars; __u32 tot_bfregs;
__u32 cache_line_size; __u32 cache_line_size;
__u16 max_sq_desc_sz; __u16 max_sq_desc_sz;
__u16 max_rq_desc_sz; __u16 max_rq_desc_sz;
...@@ -103,6 +108,8 @@ struct mlx5_ib_alloc_ucontext_resp { ...@@ -103,6 +108,8 @@ struct mlx5_ib_alloc_ucontext_resp {
__u8 cmds_supp_uhw; __u8 cmds_supp_uhw;
__u16 reserved2; __u16 reserved2;
__u64 hca_core_clock_offset; __u64 hca_core_clock_offset;
__u32 log_uar_size;
__u32 num_uars_per_page;
}; };
struct mlx5_ib_alloc_pd_resp { struct mlx5_ib_alloc_pd_resp {
...@@ -241,7 +248,7 @@ struct mlx5_ib_create_qp_rss { ...@@ -241,7 +248,7 @@ struct mlx5_ib_create_qp_rss {
}; };
struct mlx5_ib_create_qp_resp { struct mlx5_ib_create_qp_resp {
__u32 uuar_index; __u32 bfreg_index;
}; };
struct mlx5_ib_alloc_mw { struct mlx5_ib_alloc_mw {
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment