Commit be020f86 authored by Russell King's avatar Russell King

ARM: entry: abort-macro: specify registers to be used for macros

Require all callers of abort macros to specify the registers to be
used.  This improves the documentation at the callsites as to which
registers are being used by this assembly code.
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 0402bece
...@@ -22,7 +22,7 @@ ...@@ -22,7 +22,7 @@
ENTRY(v4t_early_abort) ENTRY(v4t_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR mrc p15, 0, r0, c6, c0, 0 @ get FAR
do_thumb_abort do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
ldreq r3, [r2] @ read aborted ARM instruction ldreq r3, [r2] @ read aborted ARM instruction
bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
tst r3, #1 << 20 @ check write tst r3, #1 << 20 @ check write
......
...@@ -22,10 +22,10 @@ ...@@ -22,10 +22,10 @@
ENTRY(v5t_early_abort) ENTRY(v5t_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR mrc p15, 0, r0, c6, c0, 0 @ get FAR
do_thumb_abort do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
ldreq r3, [r2] @ read aborted ARM instruction ldreq r3, [r2] @ read aborted ARM instruction
bic r1, r1, #1 << 11 @ clear bits 11 of FSR bic r1, r1, #1 << 11 @ clear bits 11 of FSR
do_ldrd_abort do_ldrd_abort tmp=r2, insn=r3
tst r3, #1 << 20 @ check write tst r3, #1 << 20 @ check write
orreq r1, r1, #1 << 11 orreq r1, r1, #1 << 11
mov pc, lr mov pc, lr
...@@ -25,9 +25,9 @@ ENTRY(v5tj_early_abort) ...@@ -25,9 +25,9 @@ ENTRY(v5tj_early_abort)
bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
tst r3, #PSR_J_BIT @ Java? tst r3, #PSR_J_BIT @ Java?
movne pc, lr movne pc, lr
do_thumb_abort do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
ldreq r3, [r2] @ read aborted ARM instruction ldreq r3, [r2] @ read aborted ARM instruction
do_ldrd_abort do_ldrd_abort tmp=r2, insn=r3
tst r3, #1 << 20 @ L = 0 -> write tst r3, #1 << 20 @ L = 0 -> write
orreq r1, r1, #1 << 11 @ yes. orreq r1, r1, #1 << 11 @ yes.
mov pc, lr mov pc, lr
......
...@@ -35,12 +35,12 @@ ENTRY(v6_early_abort) ...@@ -35,12 +35,12 @@ ENTRY(v6_early_abort)
bic r1, r1, #1 << 11 @ clear bit 11 of FSR bic r1, r1, #1 << 11 @ clear bit 11 of FSR
tst r3, #PSR_J_BIT @ Java? tst r3, #PSR_J_BIT @ Java?
movne pc, lr movne pc, lr
do_thumb_abort do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
ldreq r3, [r2] @ read aborted ARM instruction ldreq r3, [r2] @ read aborted ARM instruction
#ifdef CONFIG_CPU_ENDIAN_BE8 #ifdef CONFIG_CPU_ENDIAN_BE8
reveq r3, r3 reveq r3, r3
#endif #endif
do_ldrd_abort do_ldrd_abort tmp=r2, insn=r3
tst r3, #1 << 20 @ L = 0 -> write tst r3, #1 << 20 @ L = 0 -> write
orreq r1, r1, #1 << 11 @ yes. orreq r1, r1, #1 << 11 @ yes.
mov pc, lr mov pc, lr
......
...@@ -9,33 +9,33 @@ ...@@ -9,33 +9,33 @@
* *
*/ */
.macro do_thumb_abort .macro do_thumb_abort, fsr, pc, psr, tmp
tst r3, #PSR_T_BIT tst \psr, #PSR_T_BIT
beq not_thumb beq not_thumb
ldrh r3, [r2] @ Read aborted Thumb instruction ldrh \tmp, [\pc] @ Read aborted Thumb instruction
and r3, r3, # 0xfe00 @ Mask opcode field and \tmp, \tmp, # 0xfe00 @ Mask opcode field
cmp r3, # 0x5600 @ Is it ldrsb? cmp \tmp, # 0x5600 @ Is it ldrsb?
orreq r3, r3, #1 << 11 @ Set L-bit if yes orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes
tst r3, #1 << 11 @ L = 0 -> write tst \tmp, #1 << 11 @ L = 0 -> write
orreq r1, r1, #1 << 11 @ yes. orreq \psr, \psr, #1 << 11 @ yes.
mov pc, lr mov pc, lr
not_thumb: not_thumb:
.endm .endm
/* /*
* We check for the following insturction encoding for LDRD. * We check for the following instruction encoding for LDRD.
* *
* [27:25] == 0 * [27:25] == 000
* [7:4] == 1101 * [7:4] == 1101
* [20] == 0 * [20] == 0
*/ */
.macro do_ldrd_abort .macro do_ldrd_abort, tmp, insn
tst r3, #0x0e000000 @ [27:25] == 0 tst \insn, #0x0e000000 @ [27:25] == 0
bne not_ldrd bne not_ldrd
and r2, r3, #0x000000f0 @ [7:4] == 1101 and \tmp, \insn, #0x000000f0 @ [7:4] == 1101
cmp r2, #0x000000d0 cmp \tmp, #0x000000d0
bne not_ldrd bne not_ldrd
tst r3, #1 << 20 @ [20] == 0 tst \insn, #1 << 20 @ [20] == 0
moveq pc, lr moveq pc, lr
not_ldrd: not_ldrd:
.endm .endm
......
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