Commit be0b420a authored by Tushar Behera's avatar Tushar Behera Committed by Kukjin Kim

ARM: dts: Update the parent for Audss clocks in Exynos5420

Currently CLK_FOUT_EPLL was set as one of the parents of AUDSS mux.
As per the user manual, it should be CLK_MAU_EPLL.

The problem surfaced when the bootloader in Peach-pit board set
the EPLL clock as the parent of AUDSS mux. While booting the kernel,
we used to get a system hang during late boot if CLK_MAU_EPLL was
disabled.
Signed-off-by: default avatarTushar Behera <tushar.b@samsung.com>
Signed-off-by: default avatarShaik Ameer Basha <shaik.ameer@samsung.com>
Reported-by: default avatarKevin Hilman <khilman@linaro.org>
Tested-by: default avatarJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: default avatarDoug Anderson <dianders@chromium.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent cd3de83f
...@@ -167,7 +167,7 @@ clock_audss: audss-clock-controller@3810000 { ...@@ -167,7 +167,7 @@ clock_audss: audss-clock-controller@3810000 {
compatible = "samsung,exynos5420-audss-clock"; compatible = "samsung,exynos5420-audss-clock";
reg = <0x03810000 0x0C>; reg = <0x03810000 0x0C>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
<&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
}; };
......
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