Commit be1d8543 authored by Mike Frysinger's avatar Mike Frysinger Committed by Bryan Wu

Blackfin arch: base SIC_IWR# programming on whether the MMR exists

base SIC_IWR# programming on whether the MMR exists
rather than having to maintain another list of processors
Signed-off-by: default avatarMike Frysinger <vapier.adi@gmail.com>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent ed1fb604
...@@ -1101,10 +1101,9 @@ int __init init_arch_irq(void) ...@@ -1101,10 +1101,9 @@ int __init init_arch_irq(void)
IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \ #ifdef SIC_IWR0
|| defined(BF538_FAMILY) || defined(CONFIG_BF51x)
bfin_write_SIC_IWR0(IWR_DISABLE_ALL); bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x) # ifdef SIC_IWR1
/* BF52x/BF51x system reset does not properly reset SIC_IWR1 which /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
* will screw up the bootrom as it relies on MDMA0/1 waking it * will screw up the bootrom as it relies on MDMA0/1 waking it
* up from IDLE instructions. See this report for more info: * up from IDLE instructions. See this report for more info:
...@@ -1114,10 +1113,8 @@ int __init init_arch_irq(void) ...@@ -1114,10 +1113,8 @@ int __init init_arch_irq(void)
bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
else else
bfin_write_SIC_IWR1(IWR_DISABLE_ALL); bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
#else # endif
bfin_write_SIC_IWR1(IWR_DISABLE_ALL); # ifdef SIC_IWR2
#endif
# ifdef CONFIG_BF54x
bfin_write_SIC_IWR2(IWR_DISABLE_ALL); bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
# endif # endif
#else #else
......
...@@ -82,10 +82,9 @@ void bfin_pm_suspend_standby_enter(void) ...@@ -82,10 +82,9 @@ void bfin_pm_suspend_standby_enter(void)
bfin_pm_standby_restore(); bfin_pm_standby_restore();
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \ #ifdef SIC_IWR0
defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
bfin_write_SIC_IWR0(IWR_DISABLE_ALL); bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x) # ifdef SIC_IWR1
/* BF52x system reset does not properly reset SIC_IWR1 which /* BF52x system reset does not properly reset SIC_IWR1 which
* will screw up the bootrom as it relies on MDMA0/1 waking it * will screw up the bootrom as it relies on MDMA0/1 waking it
* up from IDLE instructions. See this report for more info: * up from IDLE instructions. See this report for more info:
...@@ -95,10 +94,8 @@ void bfin_pm_suspend_standby_enter(void) ...@@ -95,10 +94,8 @@ void bfin_pm_suspend_standby_enter(void)
bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
else else
bfin_write_SIC_IWR1(IWR_DISABLE_ALL); bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
#else # endif
bfin_write_SIC_IWR1(IWR_DISABLE_ALL); # ifdef SIC_IWR2
#endif
# ifdef CONFIG_BF54x
bfin_write_SIC_IWR2(IWR_DISABLE_ALL); bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
# endif # endif
#else #else
......
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