m68knommu: Add support for the Coldfire m5441x.

Add support for the Coldfire 5441x (54410/54415/54416/54417/54418).  Currently
we only support noMMU mode.  It requires the PIT patch posted previously as it
uses the PIT instead of the dma timer as a clock source so we can get all that
GENERIC_CLOCKEVENTS goodness.  It also adds some simple clk definitions and
very simple minded power management.  The gpio code is tweeked and some
additional devices are added to devices.c.  The Makefile uses -mv4e as
apparently, the only difference a v4m (m5441x) and a v4e is the later has a
FPU, which I don't think should matter to us in the kernel.
Signed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>

arch/m68k/Kconfig.cpu

@@ -261,6 +261,14 @@ config M548x
 	help
 	  Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
 
+config M5441x
+	bool "MCF5441x"
+	depends on !MMU
+	select GENERIC_CLOCKEVENTS
+	select HAVE_CACHE_CB
+	help
+	  Freescale Coldfire 54410/54415/54416/54417/54418 processor support.
+
 endif # COLDFIRE
 
 

arch/m68k/Makefile

@@ -41,6 +41,7 @@ cpuflags-$(CONFIG_M68030)	:=
 cpuflags-$(CONFIG_M68020)	:=
 cpuflags-$(CONFIG_M68360)	:= -m68332
 cpuflags-$(CONFIG_M68000)	:= -m68000
+cpuflags-$(CONFIG_M5441x)	:= $(call cc-option,-mcpu=54455,-mcfv4e)
 cpuflags-$(CONFIG_M54xx)	:= $(call cc-option,-mcpu=5475,-m5200)
 cpuflags-$(CONFIG_M5407)	:= $(call cc-option,-mcpu=5407,-m5200)
 cpuflags-$(CONFIG_M532x)	:= $(call cc-option,-mcpu=532x,-m5307)

arch/m68k/include/asm/gpio.h

@@ -64,8 +64,14 @@ static inline void gpio_set_value(unsigned gpio, int value)
 
 static inline int gpio_to_irq(unsigned gpio)
 {
-	return (gpio < MCFGPIO_IRQ_MAX) ? gpio + MCFGPIO_IRQ_VECBASE
-		: __gpio_to_irq(gpio);
+#if defined(MCFGPIO_IRQ_MIN)
+	if ((gpio >= MCFGPIO_IRQ_MIN) && (gpio < MCFGPIO_IRQ_MAX))
+#else
+	if (gpio < MCFGPIO_IRQ_MAX)
+#endif
+		return gpio + MCFGPIO_IRQ_VECBASE;
+	else
+		return __gpio_to_irq(gpio);
 }
 
 static inline int irq_to_gpio(unsigned irq)

arch/m68k/include/asm/m5441xsim.h

+/*
+ *	m5441xsim.h -- Coldfire 5441x register definitions
+ *
+ *	(C) Copyright 2012, Steven King <sfking@fdwdc.com>
+*/
+
+#ifndef m5441xsim_h
+#define m5441xsim_h
+
+#define CPU_NAME		"COLDFIRE(m5441x)"
+#define CPU_INSTR_PER_JIFFY	2
+#define MCF_BUSCLK		(MCF_CLK / 2)
+
+#include <asm/m54xxacr.h>
+
+/*
+ *  Reset Controller Module.
+ */
+
+#define	MCF_RCR			0xec090000
+#define	MCF_RSR			0xec090001
+
+#define	MCF_RCR_SWRESET		0x80		/* Software reset bit */
+#define	MCF_RCR_FRCSTOUT	0x40		/* Force external reset */
+
+/*
+ *  Interrupt Controller Modules.
+ */
+/* the 5441x have 3 interrupt controllers, each control 64 interrupts */
+#define MCFINT_VECBASE		64
+#define MCFINT0_VECBASE		MCFINT_VECBASE
+#define MCFINT1_VECBASE		(MCFINT0_VECBASE + 64)
+#define MCFINT2_VECBASE		(MCFINT1_VECBASE + 64)
+
+/* interrupt controller 0 */
+#define MCFINTC0_SIMR		0xfc04801c
+#define MCFINTC0_CIMR		0xfc04801d
+#define	MCFINTC0_ICR0		0xfc048040
+/* interrupt controller 1 */
+#define MCFINTC1_SIMR		0xfc04c01c
+#define MCFINTC1_CIMR		0xfc04c01d
+#define	MCFINTC1_ICR0		0xfc04c040
+/* interrupt controller 2 */
+#define MCFINTC2_SIMR		0xfc05001c
+#define MCFINTC2_CIMR		0xfc05001d
+#define	MCFINTC2_ICR0		0xfc050040
+
+/* on interrupt controller 0 */
+#define MCFINT0_EPORT0		1
+#define MCFINT0_UART0		26
+#define MCFINT0_UART1		27
+#define MCFINT0_UART2		28
+#define MCFINT0_UART3		29
+#define MCFINT0_I2C0		30
+#define MCFINT0_DSPI0		31
+
+#define MCFINT0_TIMER0		32
+#define MCFINT0_TIMER1		33
+#define MCFINT0_TIMER2		34
+#define MCFINT0_TIMER3		35
+
+#define MCFINT0_FECRX0		36
+#define MCFINT0_FECTX0		40
+#define MCFINT0_FECENTC0	42
+
+#define MCFINT0_FECRX1		49
+#define MCFINT0_FECTX1		53
+#define MCFINT0_FECENTC1	55
+
+/* on interrupt controller 1 */
+#define MCFINT1_UART4		48
+#define MCFINT1_UART5		49
+#define MCFINT1_UART6		50
+#define MCFINT1_UART7		51
+#define MCFINT1_UART8		52
+#define MCFINT1_UART9		53
+#define MCFINT1_DSPI1		54
+#define MCFINT1_DSPI2		55
+#define MCFINT1_DSPI3		56
+#define MCFINT1_I2C1		57
+#define MCFINT1_I2C2		58
+#define MCFINT1_I2C3		59
+#define MCFINT1_I2C4		60
+#define MCFINT1_I2C5		61
+
+/* on interrupt controller 2 */
+#define MCFINT2_PIT0		13
+#define MCFINT2_PIT1		14
+#define MCFINT2_PIT2		15
+#define MCFINT2_PIT3		16
+#define MCFINT2_RTC		26
+
+/*
+ *  PIT timer module.
+ */
+#define	MCFPIT_BASE0		0xFC080000	/* Base address of TIMER0 */
+#define	MCFPIT_BASE1		0xFC084000	/* Base address of TIMER1 */
+#define	MCFPIT_BASE2		0xFC088000	/* Base address of TIMER2 */
+#define	MCFPIT_BASE3		0xFC08C000	/* Base address of TIMER3 */
+
+
+#define MCF_IRQ_PIT1		(MCFINT2_VECBASE + MCFINT2_PIT1)
+
+/*
+ * Power Management
+ */
+#define MCFPM_WCR		0xfc040013
+#define MCFPM_PPMSR0		0xfc04002c
+#define MCFPM_PPMCR0		0xfc04002d
+#define MCFPM_PPMSR1		0xfc04002e
+#define MCFPM_PPMCR1		0xfc04002f
+#define MCFPM_PPMHR0		0xfc040030
+#define MCFPM_PPMLR0		0xfc040034
+#define MCFPM_PPMHR1		0xfc040038
+#define MCFPM_PPMLR1		0xfc04003c
+#define MCFPM_LPCR		0xec090007
+/*
+ *  UART module.
+ */
+#define MCFUART_BASE0		0xfc060000	/* Base address of UART0 */
+#define MCFUART_BASE1		0xfc064000	/* Base address of UART1 */
+#define MCFUART_BASE2		0xfc068000	/* Base address of UART2 */
+#define MCFUART_BASE3		0xfc06c000	/* Base address of UART3 */
+#define MCFUART_BASE4		0xec060000	/* Base address of UART4 */
+#define MCFUART_BASE5		0xec064000	/* Base address of UART5 */
+#define MCFUART_BASE6		0xec068000	/* Base address of UART6 */
+#define MCFUART_BASE7		0xec06c000	/* Base address of UART7 */
+#define MCFUART_BASE8		0xec070000	/* Base address of UART8 */
+#define MCFUART_BASE9		0xec074000	/* Base address of UART9 */
+
+#define MCF_IRQ_UART0		(MCFINT0_VECBASE + MCFINT0_UART0)
+#define MCF_IRQ_UART1		(MCFINT0_VECBASE + MCFINT0_UART1)
+#define MCF_IRQ_UART2		(MCFINT0_VECBASE + MCFINT0_UART2)
+#define MCF_IRQ_UART3		(MCFINT0_VECBASE + MCFINT0_UART3)
+#define MCF_IRQ_UART4		(MCFINT1_VECBASE + MCFINT1_UART4)
+#define MCF_IRQ_UART5		(MCFINT1_VECBASE + MCFINT1_UART5)
+#define MCF_IRQ_UART6		(MCFINT1_VECBASE + MCFINT1_UART6)
+#define MCF_IRQ_UART7		(MCFINT1_VECBASE + MCFINT1_UART7)
+#define MCF_IRQ_UART8		(MCFINT1_VECBASE + MCFINT1_UART8)
+#define MCF_IRQ_UART9		(MCFINT1_VECBASE + MCFINT1_UART9)
+/*
+ *  FEC modules.
+ */
+#define MCFFEC_BASE0		0xfc0d4000
+#define MCFFEC_SIZE0		0x800
+#define MCF_IRQ_FECRX0		(MCFINT0_VECBASE + MCFINT0_FECRX0)
+#define MCF_IRQ_FECTX0		(MCFINT0_VECBASE + MCFINT0_FECTX0)
+#define MCF_IRQ_FECENTC0	(MCFINT0_VECBASE + MCFINT0_FECENTC0)
+
+#define MCFFEC_BASE1		0xfc0d8000
+#define MCFFEC_SIZE1		0x800
+#define MCF_IRQ_FECRX1		(MCFINT0_VECBASE + MCFINT0_FECRX1)
+#define MCF_IRQ_FECTX1		(MCFINT0_VECBASE + MCFINT0_FECTX1)
+#define MCF_IRQ_FECENTC1	(MCFINT0_VECBASE + MCFINT0_FECENTC1)
+/*
+ *  I2C modules.
+ */
+#define MCFI2C_BASE0		0xfc058000
+#define MCFI2C_SIZE0		0x20
+#define MCFI2C_BASE1		0xfc038000
+#define MCFI2C_SIZE1		0x20
+#define MCFI2C_BASE2		0xec010000
+#define MCFI2C_SIZE2		0x20
+#define MCFI2C_BASE3		0xec014000
+#define MCFI2C_SIZE3		0x20
+#define MCFI2C_BASE4		0xec018000
+#define MCFI2C_SIZE4		0x20
+#define MCFI2C_BASE5		0xec01c000
+#define MCFI2C_SIZE5		0x20
+
+#define MCF_IRQ_I2C0		(MCFINT0_VECBASE + MCFINT0_I2C0)
+#define MCF_IRQ_I2C1		(MCFINT1_VECBASE + MCFINT1_I2C1)
+#define MCF_IRQ_I2C2		(MCFINT1_VECBASE + MCFINT1_I2C2)
+#define MCF_IRQ_I2C3		(MCFINT1_VECBASE + MCFINT1_I2C3)
+#define MCF_IRQ_I2C4		(MCFINT1_VECBASE + MCFINT1_I2C4)
+#define MCF_IRQ_I2C5		(MCFINT1_VECBASE + MCFINT1_I2C5)
+/*
+ *  EPORT Module.
+ */
+#define MCFEPORT_EPPAR		0xfc090000
+#define MCFEPORT_EPIER		0xfc090003
+#define MCFEPORT_EPFR		0xfc090006
+
+/*
+ *  GPIO Module.
+ */
+#define MCFGPIO_PODR_A		0xec094000
+#define MCFGPIO_PODR_B		0xec094001
+#define MCFGPIO_PODR_C		0xec094002
+#define MCFGPIO_PODR_D		0xec094003
+#define MCFGPIO_PODR_E		0xec094004
+#define MCFGPIO_PODR_F		0xec094005
+#define MCFGPIO_PODR_G		0xec094006
+#define MCFGPIO_PODR_H		0xec094007
+#define MCFGPIO_PODR_I		0xec094008
+#define MCFGPIO_PODR_J		0xec094009
+#define MCFGPIO_PODR_K		0xec09400a
+
+#define MCFGPIO_PDDR_A		0xec09400c
+#define MCFGPIO_PDDR_B		0xec09400d
+#define MCFGPIO_PDDR_C		0xec09400e
+#define MCFGPIO_PDDR_D		0xec09400f
+#define MCFGPIO_PDDR_E		0xec094010
+#define MCFGPIO_PDDR_F		0xec094011
+#define MCFGPIO_PDDR_G		0xec094012
+#define MCFGPIO_PDDR_H		0xec094013
+#define MCFGPIO_PDDR_I		0xec094014
+#define MCFGPIO_PDDR_J		0xec094015
+#define MCFGPIO_PDDR_K		0xec094016
+
+#define MCFGPIO_PPDSDR_A	0xec094018
+#define MCFGPIO_PPDSDR_B	0xec094019
+#define MCFGPIO_PPDSDR_C	0xec09401a
+#define MCFGPIO_PPDSDR_D	0xec09401b
+#define MCFGPIO_PPDSDR_E	0xec09401c
+#define MCFGPIO_PPDSDR_F	0xec09401d
+#define MCFGPIO_PPDSDR_G	0xec09401e
+#define MCFGPIO_PPDSDR_H	0xec09401f
+#define MCFGPIO_PPDSDR_I	0xec094020
+#define MCFGPIO_PPDSDR_J	0xec094021
+#define MCFGPIO_PPDSDR_K	0xec094022
+
+#define MCFGPIO_PCLRR_A		0xec094024
+#define MCFGPIO_PCLRR_B		0xec094025
+#define MCFGPIO_PCLRR_C		0xec094026
+#define MCFGPIO_PCLRR_D		0xec094027
+#define MCFGPIO_PCLRR_E		0xec094028
+#define MCFGPIO_PCLRR_F		0xec094029
+#define MCFGPIO_PCLRR_G		0xec09402a
+#define MCFGPIO_PCLRR_H		0xec09402b
+#define MCFGPIO_PCLRR_I		0xec09402c
+#define MCFGPIO_PCLRR_J		0xec09402d
+#define MCFGPIO_PCLRR_K		0xec09402e
+
+#define MCFGPIO_PAR_FBCTL	0xec094048
+#define MCFGPIO_PAR_BE		0xec094049
+#define MCFGPIO_PAR_CS		0xec09404a
+#define MCFGPIO_PAR_CANI2C	0xec09404b
+#define MCFGPIO_PAR_IRQ0H	0xec09404c
+#define MCFGPIO_PAR_IRQ0L	0xec09404d
+#define MCFGPIO_PAR_DSPIOWH	0xec09404e
+#define MCFGPIO_PAR_DSPIOWL	0xec09404f
+#define MCFGPIO_PAR_TIMER	0xec094050
+#define MCFGPIO_PAR_UART2	0xec094051
+#define MCFGPIO_PAR_UART1	0xec094052
+#define MCFGPIO_PAR_UART0	0xec094053
+#define MCFGPIO_PAR_SDHCH	0xec094054
+#define MCFGPIO_PAR_SDHCL	0xec094055
+#define MCFGPIO_PAR_SIMP0H	0xec094056
+#define MCFGPIO_PAR_SIMP0L	0xec094057
+#define MCFGPIO_PAR_SSI0H	0xec094058
+#define MCFGPIO_PAR_SSI0L	0xec094059
+#define MCFGPIO_PAR_DEBUGH1	0xec09405a
+#define MCFGPIO_PAR_DEBUGH0	0xec09405b
+#define MCFGPIO_PAR_DEBUGl	0xec09405c
+#define MCFGPIO_PAR_FEC		0xec09405e
+
+/* generalization for generic gpio support */
+#define MCFGPIO_PODR		MCFGPIO_PODR_A
+#define MCFGPIO_PDDR		MCFGPIO_PDDR_A
+#define MCFGPIO_PPDR		MCFGPIO_PPDSDR_A
+#define MCFGPIO_SETR		MCFGPIO_PPDSDR_A
+#define MCFGPIO_CLRR		MCFGPIO_PCLRR_A
+
+#define MCFGPIO_IRQ_MIN		17
+#define MCFGPIO_IRQ_MAX		24
+#define MCFGPIO_IRQ_VECBASE	(MCFINT_VECBASE - MCFGPIO_IRQ_MIN)
+#define MCFGPIO_PIN_MAX		87
+
+#endif /* m5441xsim_h */

arch/m68k/include/asm/m54xxacr.h

@@ -55,6 +55,10 @@
 #define ICACHE_SIZE 0x8000	/* instruction - 32k */
 #define DCACHE_SIZE 0x8000	/* data - 32k */
 
+#elif defined(CONFIG_M5441x)
+
+#define ICACHE_SIZE 0x2000	/* instruction - 8k */
+#define DCACHE_SIZE 0x2000	/* data - 8k */
 #endif
 
 #define CACHE_LINE_SIZE 0x0010	/* 16 bytes */

arch/m68k/include/asm/mcfclk.h

+/*
+ * mcfclk.h -- coldfire specific clock structure
+ */
+
+
+#ifndef mcfclk_h
+#define mcfclk_h
+
+struct clk;
+
+#ifdef MCFPM_PPMCR0
+struct clk_ops {
+	void (*enable)(struct clk *);
+	void (*disable)(struct clk *);
+};
+
+struct clk {
+	const char *name;
+	struct clk_ops *clk_ops;
+	unsigned long rate;
+	unsigned long enabled;
+	u8 slot;
+};
+
+extern struct clk *mcf_clks[];
+extern struct clk_ops clk_ops0;
+#ifdef MCFPM_PPMCR1
+extern struct clk_ops clk_ops1;
+#endif /* MCFPM_PPMCR1 */
+
+#define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \
+static struct clk __clk_##clk_bank##_##clk_slot = { \
+	.name = clk_name, \
+	.clk_ops = &clk_ops##clk_bank, \
+	.rate = clk_rate, \
+	.slot = clk_slot, \
+}
+
+void __clk_init_enabled(struct clk *);
+void __clk_init_disabled(struct clk *);
+#endif /* MCFPM_PPMCR0 */
+
+#endif /* mcfclk_h */

arch/m68k/include/asm/mcfgpio.h

@@ -104,7 +104,8 @@ static inline void gpio_free(unsigned gpio)
 #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
     defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
     defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
-    defined(CONFIG_M532x) || defined(CONFIG_M54xx)
+    defined(CONFIG_M532x) || defined(CONFIG_M54xx) || \
+    defined(CONFIG_M5441x)
 
 /* These parts have GPIO organized by 8 bit ports */
 
@@ -137,7 +138,8 @@ static inline void gpio_free(unsigned gpio)
 #define mcfgpio_port(gpio)		((gpio) / MCFGPIO_PORTSIZE)
 
 #if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
-    defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
+    defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+    defined(CONFIG_M532x) || defined(CONFIG_M5441x)
 /*
  * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
  * read-modify-write to change an output and a GPIO module which has separate
@@ -149,6 +151,9 @@ static inline void gpio_free(unsigned gpio)
  * read-modify-write as well as those controlled by the EPORT and GPIO modules.
  */
 #define MCFGPIO_SCR_START		40
+#elif defined(CONFIGM5441x)
+/* The m5441x EPORT doesn't have its own GPIO port, uses PORT C */
+#define MCFGPIO_SCR_START		0
 #else
 #define MCFGPIO_SCR_START		8
 #endif
@@ -189,7 +194,9 @@ static inline u32 __mcfgpio_ppdr(unsigned gpio)
 	else
 		return MCFSIM2_GPIO1READ;
 #elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
-      defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
+      defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+      defined(CONFIG_M532x) || defined(CONFIG_M5441x)
+#if !defined(CONFIG_M5441x)
 	if (gpio < 8)
 		return MCFEPORT_EPPDR;
 #if defined(CONFIG_M528x)
@@ -201,8 +208,9 @@ static inline u32 __mcfgpio_ppdr(unsigned gpio)
 		return MCFQADC_PORTQA;
 	else if (gpio < 40)
 		return MCFQADC_PORTQB;
-#endif
+#endif /* defined(CONFIG_M528x) */
 	else
+#endif /* !defined(CONFIG_M5441x) */
 		return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
 #else
 	return 0;
@@ -228,7 +236,9 @@ static inline u32 __mcfgpio_podr(unsigned gpio)
 	else
 		return MCFSIM2_GPIO1WRITE;
 #elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
-      defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
+      defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+      defined(CONFIG_M532x) || defined(CONFIG_M5441x)
+#if !defined(CONFIG_M5441x)
 	if (gpio < 8)
 		return MCFEPORT_EPDR;
 #if defined(CONFIG_M528x)
@@ -240,8 +250,9 @@ static inline u32 __mcfgpio_podr(unsigned gpio)
 		return MCFQADC_PORTQA;
 	else if (gpio < 40)
 		return MCFQADC_PORTQB;
-#endif
+#endif /* defined(CONFIG_M528x) */
 	else
+#endif /* !defined(CONFIG_M5441x) */
 		return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
 #else
 	return 0;
@@ -267,7 +278,9 @@ static inline u32 __mcfgpio_pddr(unsigned gpio)
 	else
 		return MCFSIM2_GPIO1ENABLE;
 #elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
-      defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
+      defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+      defined(CONFIG_M532x) || defined(CONFIG_M5441x)
+#if !defined(CONFIG_M5441x)
 	if (gpio < 8)
 		return MCFEPORT_EPDDR;
 #if defined(CONFIG_M528x)
@@ -279,8 +292,9 @@ static inline u32 __mcfgpio_pddr(unsigned gpio)
 		return MCFQADC_DDRQA;
 	else if (gpio < 40)
 		return MCFQADC_DDRQB;
-#endif
+#endif /* defined(CONFIG_M528x) */
 	else
+#endif /* !defined(CONFIG_M5441x) */
 		return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
 #else
 	return 0;

arch/m68k/include/asm/mcfsim.h

@@ -46,6 +46,8 @@
 #include <asm/mcfintc.h>
 #elif defined(CONFIG_M54xx)
 #include <asm/m54xxsim.h>
+#elif defined(CONFIG_M5441x)
+#include <asm/m5441xsim.h>
 #endif
 
 /****************************************************************************/

arch/m68k/include/asm/mcftimer.h

@@ -19,7 +19,7 @@
 #define	MCFTIMER_TRR		0x04		/* Timer Reference (r/w) */
 #define	MCFTIMER_TCR		0x08		/* Timer Capture reg (r/w) */
 #define	MCFTIMER_TCN		0x0C		/* Timer Counter reg (r/w) */
-#if defined(CONFIG_M532x)
+#if defined(CONFIG_M532x) || defined(CONFIG_M5441x)
 #define	MCFTIMER_TER		0x03		/* Timer Event reg (r/w) */
 #else
 #define	MCFTIMER_TER		0x11		/* Timer Event reg (r/w) */

arch/m68k/platform/coldfire/Makefile

@@ -28,6 +28,7 @@ obj-$(CONFIG_M5307)	+= m5307.o timers.o intc.o reset.o
 obj-$(CONFIG_M532x)	+= m532x.o timers.o intc-simr.o reset.o
 obj-$(CONFIG_M5407)	+= m5407.o timers.o intc.o reset.o
 obj-$(CONFIG_M54xx)	+= m54xx.o sltimers.o intc-2.o
+obj-$(CONFIG_M5441x)	+= m5441x.o pit.o intc-simr.o reset.o
 
 obj-$(CONFIG_NETtel)	+= nettel.o
 obj-$(CONFIG_CLEOPATRA)	+= nettel.o

arch/m68k/platform/coldfire/clk.c

@@ -10,11 +10,17 @@
 
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
 #include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
 #include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfclk.h>
 
 /***************************************************************************/
-
+#ifndef MCFPM_PPMCR0
 struct clk *clk_get(struct device *dev, const char *id)
 {
 	return NULL;
@@ -49,4 +55,101 @@ struct clk *devm_clk_get(struct device *dev, const char *id)
 }
 EXPORT_SYMBOL(devm_clk_get);
 
+#else
+static DEFINE_SPINLOCK(clk_lock);
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+	const char *clk_name = dev ? dev_name(dev) : id ? id : NULL;
+	struct clk *clk;
+	unsigned i;
+
+	for (i = 0; (clk = mcf_clks[i]) != NULL; ++i)
+		if (!strcmp(clk->name, clk_name))
+			return clk;
+	pr_warn("clk_get: didn't find clock %s\n", clk_name);
+	return ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL(clk_get);
+
+int clk_enable(struct clk *clk)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&clk_lock, flags);
+	if ((clk->enabled++ == 0) && clk->clk_ops)
+		clk->clk_ops->enable(clk);
+	spin_unlock_irqrestore(&clk_lock, flags);
+
+	return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&clk_lock, flags);
+	if ((--clk->enabled == 0) && clk->clk_ops)
+		clk->clk_ops->disable(clk);
+	spin_unlock_irqrestore(&clk_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+void clk_put(struct clk *clk)
+{
+	if (clk->enabled != 0)
+		pr_warn("clk_put %s still enabled\n", clk->name);
+}
+EXPORT_SYMBOL(clk_put);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
 /***************************************************************************/
+
+void __clk_init_enabled(struct clk *clk)
+{
+	clk->enabled = 1;
+	clk->clk_ops->enable(clk);
+}
+
+void __clk_init_disabled(struct clk *clk)
+{
+	clk->enabled = 0;
+	clk->clk_ops->disable(clk);
+}
+
+static void __clk_enable0(struct clk *clk)
+{
+	__raw_writeb(clk->slot, MCFPM_PPMCR0);
+}
+
+static void __clk_disable0(struct clk *clk)
+{
+	__raw_writeb(clk->slot, MCFPM_PPMSR0);
+}
+
+struct clk_ops clk_ops0 = {
+	.enable		= __clk_enable0,
+	.disable	= __clk_disable0,
+};
+
+#ifdef MCFPM_PPMCR1
+static void __clk_enable1(struct clk *clk)
+{
+	__raw_writeb(clk->slot, MCFPM_PPMCR1);
+}
+
+static void __clk_disable1(struct clk *clk)
+{
+	__raw_writeb(clk->slot, MCFPM_PPMSR1);
+}
+
+struct clk_ops clk_ops1 = {
+	.enable		= __clk_enable1,
+	.disable	= __clk_disable1,
+};
+#endif /* MCFPM_PPMCR1 */
+#endif /* MCFPM_PPMCR0 */

arch/m68k/platform/coldfire/device.c

@@ -13,6 +13,7 @@
 #include <linux/io.h>
 #include <linux/spi/spi.h>
 #include <linux/gpio.h>
+#include <linux/fec.h>
 #include <asm/traps.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
@@ -20,7 +21,7 @@
 #include <asm/mcfqspi.h>
 
 /*
- *	All current ColdFire parts contain from 2, 3 or 4 UARTS.
+ *	All current ColdFire parts contain from 2, 3, 4 or 10 UARTS.
  */
 static struct mcf_platform_uart mcf_uart_platform_data[] = {
 	{
@@ -42,6 +43,42 @@ static struct mcf_platform_uart mcf_uart_platform_data[] = {
 		.mapbase	= MCFUART_BASE3,
 		.irq		= MCF_IRQ_UART3,
 	},
+#endif
+#ifdef MCFUART_BASE4
+	{
+		.mapbase	= MCFUART_BASE4,
+		.irq		= MCF_IRQ_UART4,
+	},
+#endif
+#ifdef MCFUART_BASE5
+	{
+		.mapbase	= MCFUART_BASE5,
+		.irq		= MCF_IRQ_UART5,
+	},
+#endif
+#ifdef MCFUART_BASE6
+	{
+		.mapbase	= MCFUART_BASE6,
+		.irq		= MCF_IRQ_UART6,
+	},
+#endif
+#ifdef MCFUART_BASE7
+	{
+		.mapbase	= MCFUART_BASE7,
+		.irq		= MCF_IRQ_UART7,
+	},
+#endif
+#ifdef MCFUART_BASE8
+	{
+		.mapbase	= MCFUART_BASE8,
+		.irq		= MCF_IRQ_UART8,
+	},
+#endif
+#ifdef MCFUART_BASE9
+	{
+		.mapbase	= MCFUART_BASE9,
+		.irq		= MCF_IRQ_UART9,
+	},
 #endif
 	{ },
 };
@@ -53,6 +90,18 @@ static struct platform_device mcf_uart = {
 };
 
 #ifdef CONFIG_FEC
+
+#ifdef CONFIG_M5441x
+#define FEC_NAME	"enet-fec"
+static struct fec_platform_data fec_pdata = {
+	.phy		= PHY_INTERFACE_MODE_RMII,
+};
+#define FEC_PDATA	(&fec_pdata)
+#else
+#define FEC_NAME	"fec"
+#define FEC_PDATA	NULL
+#endif
+
 /*
  *	Some ColdFire cores contain the Fast Ethernet Controller (FEC)
  *	block. It is Freescale's own hardware block. Some ColdFires
@@ -82,10 +131,11 @@ static struct resource mcf_fec0_resources[] = {
 };
 
 static struct platform_device mcf_fec0 = {
-	.name			= "fec",
+	.name			= FEC_NAME,
 	.id			= 0,
 	.num_resources		= ARRAY_SIZE(mcf_fec0_resources),
 	.resource		= mcf_fec0_resources,
+	.dev.platform_data	= FEC_PDATA,
 };
 
 #ifdef MCFFEC_BASE1
@@ -113,10 +163,11 @@ static struct resource mcf_fec1_resources[] = {
 };
 
 static struct platform_device mcf_fec1 = {
-	.name			= "fec",
+	.name			= FEC_NAME,
 	.id			= 1,
 	.num_resources		= ARRAY_SIZE(mcf_fec1_resources),
 	.resource		= mcf_fec1_resources,
+	.dev.platform_data	= FEC_PDATA,
 };
 #endif /* MCFFEC_BASE1 */
 #endif /* CONFIG_FEC */

arch/m68k/platform/coldfire/intc-simr.c

@@ -59,16 +59,18 @@ static unsigned int inline irq2ebit(unsigned int irq)
 #endif
 
 /*
- *	There maybe one or two interrupt control units, each has 64
- *	interrupts. If there is no second unit then MCFINTC1_* defines
- *	will be 0 (and code for them optimized away).
+ *	There maybe one, two or three interrupt control units, each has 64
+ *	interrupts. If there is no second or third unit then MCFINTC1_* or
+ *	MCFINTC2_* defines will be 0 (and code for them optimized away).
  */
 
 static void intc_irq_mask(struct irq_data *d)
 {
 	unsigned int irq = d->irq - MCFINT_VECBASE;
 
-	if (MCFINTC1_SIMR && (irq > 64))
+	if (MCFINTC2_SIMR && (irq > 128))
+		__raw_writeb(irq - 128, MCFINTC2_SIMR);
+	else if (MCFINTC1_SIMR && (irq > 64))
 		__raw_writeb(irq - 64, MCFINTC1_SIMR);
 	else
 		__raw_writeb(irq, MCFINTC0_SIMR);
@@ -78,7 +80,9 @@ static void intc_irq_unmask(struct irq_data *d)
 {
 	unsigned int irq = d->irq - MCFINT_VECBASE;
 
-	if (MCFINTC1_CIMR && (irq > 64))
+	if (MCFINTC2_CIMR && (irq > 128))
+		__raw_writeb(irq - 128, MCFINTC2_CIMR);
+	else if (MCFINTC1_CIMR && (irq > 64))
 		__raw_writeb(irq - 64, MCFINTC1_CIMR);
 	else
 		__raw_writeb(irq, MCFINTC0_CIMR);
@@ -99,9 +103,11 @@ static unsigned int intc_irq_startup(struct irq_data *d)
 		unsigned int ebit = irq2ebit(irq);
 		u8 v;
 
+#if defined(MCFEPORT_EPDDR)
 		/* Set EPORT line as input */
 		v = __raw_readb(MCFEPORT_EPDDR);
 		__raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR);
+#endif
 
 		/* Set EPORT line as interrupt source */
 		v = __raw_readb(MCFEPORT_EPIER);
@@ -109,12 +115,13 @@ static unsigned int intc_irq_startup(struct irq_data *d)
 	}
 
 	irq -= MCFINT_VECBASE;
-	if (MCFINTC1_ICR0 && (irq > 64))
+	if (MCFINTC2_ICR0 && (irq > 128))
+		__raw_writeb(5, MCFINTC2_ICR0 + irq - 128);
+	else if (MCFINTC1_ICR0 && (irq > 64))
 		__raw_writeb(5, MCFINTC1_ICR0 + irq - 64);
 	else
 		__raw_writeb(5, MCFINTC0_ICR0 + irq);
 
-
 	intc_irq_unmask(d);
 	return 0;
 }
@@ -175,8 +182,11 @@ void __init init_IRQ(void)
 	__raw_writeb(0xff, MCFINTC0_SIMR);
 	if (MCFINTC1_SIMR)
 		__raw_writeb(0xff, MCFINTC1_SIMR);
+	if (MCFINTC2_SIMR)
+		__raw_writeb(0xff, MCFINTC2_SIMR);
 
-	eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0);
+	eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0) +
+						(MCFINTC2_ICR0 ? 64 : 0);
 	for (irq = MCFINT_VECBASE; (irq < eirq); irq++) {
 		if ((irq >= EINT1) && (irq <= EINT7))
 			irq_set_chip(irq, &intc_irq_chip_edge_port);

arch/m68k/platform/coldfire/m5441x.c

+/*
+ *	m5441x.c -- support for Coldfire m5441x processors
+ *
+ *	(C) Copyright Steven King <sfking@fdwdc.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfuart.h>
+#include <asm/mcfdma.h>
+#include <asm/mcfclk.h>
+
+DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
+DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
+DEFINE_CLK(0, "mcfcan.1", 9, MCF_CLK);
+DEFINE_CLK(0, "mcfi2c.1", 14, MCF_CLK);
+DEFINE_CLK(0, "mcfdspi.1", 15, MCF_CLK);
+DEFINE_CLK(0, "edma", 17, MCF_CLK);
+DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
+DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
+DEFINE_CLK(0, "intc.2", 20, MCF_CLK);
+DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
+DEFINE_CLK(0, "mcfdspi.0", 23, MCF_CLK);
+DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
+DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
+DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
+DEFINE_CLK(0, "mcfuart.3", 27, MCF_BUSCLK);
+DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
+DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
+DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
+DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
+DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
+DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
+DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK);
+DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK);
+DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK);
+DEFINE_CLK(0, "mcfadc.0", 38, MCF_CLK);
+DEFINE_CLK(0, "mcfdac.0", 39, MCF_CLK);
+DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK);
+DEFINE_CLK(0, "mcfsim.0", 43, MCF_CLK);
+DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
+DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
+DEFINE_CLK(0, "mcfddr-sram.0", 46, MCF_CLK);
+DEFINE_CLK(0, "mcfssi.0", 47, MCF_CLK);
+DEFINE_CLK(0, "pll.0", 48, MCF_CLK);
+DEFINE_CLK(0, "mcfrng.0", 49, MCF_CLK);
+DEFINE_CLK(0, "mcfssi.1", 50, MCF_CLK);
+DEFINE_CLK(0, "mcfsdhc.0", 51, MCF_CLK);
+DEFINE_CLK(0, "enet-fec.0", 53, MCF_CLK);
+DEFINE_CLK(0, "enet-fec.1", 54, MCF_CLK);
+DEFINE_CLK(0, "switch.0", 55, MCF_CLK);
+DEFINE_CLK(0, "switch.1", 56, MCF_CLK);
+DEFINE_CLK(0, "nand.0", 63, MCF_CLK);
+
+DEFINE_CLK(1, "mcfow.0", 2, MCF_CLK);
+DEFINE_CLK(1, "mcfi2c.2", 4, MCF_CLK);
+DEFINE_CLK(1, "mcfi2c.3", 5, MCF_CLK);
+DEFINE_CLK(1, "mcfi2c.4", 6, MCF_CLK);
+DEFINE_CLK(1, "mcfi2c.5", 7, MCF_CLK);
+DEFINE_CLK(1, "mcfuart.4", 24, MCF_BUSCLK);
+DEFINE_CLK(1, "mcfuart.5", 25, MCF_BUSCLK);
+DEFINE_CLK(1, "mcfuart.6", 26, MCF_BUSCLK);
+DEFINE_CLK(1, "mcfuart.7", 27, MCF_BUSCLK);
+DEFINE_CLK(1, "mcfuart.8", 28, MCF_BUSCLK);
+DEFINE_CLK(1, "mcfuart.9", 29, MCF_BUSCLK);
+DEFINE_CLK(1, "mcfpwm.0", 34, MCF_BUSCLK);
+DEFINE_CLK(1, "sys.0", 36, MCF_BUSCLK);
+DEFINE_CLK(1, "gpio.0", 37, MCF_BUSCLK);
+
+struct clk *mcf_clks[] = {
+	&__clk_0_2,
+	&__clk_0_8,
+	&__clk_0_9,
+	&__clk_0_14,
+	&__clk_0_15,
+	&__clk_0_17,
+	&__clk_0_18,
+	&__clk_0_19,
+	&__clk_0_20,
+	&__clk_0_22,
+	&__clk_0_23,
+	&__clk_0_24,
+	&__clk_0_25,
+	&__clk_0_26,
+	&__clk_0_27,
+	&__clk_0_28,
+	&__clk_0_29,
+	&__clk_0_30,
+	&__clk_0_31,
+	&__clk_0_32,
+	&__clk_0_33,
+	&__clk_0_34,
+	&__clk_0_35,
+	&__clk_0_37,
+	&__clk_0_38,
+	&__clk_0_39,
+	&__clk_0_42,
+	&__clk_0_43,
+	&__clk_0_44,
+	&__clk_0_45,
+	&__clk_0_46,
+	&__clk_0_47,
+	&__clk_0_48,
+	&__clk_0_49,
+	&__clk_0_50,
+	&__clk_0_51,
+	&__clk_0_53,
+	&__clk_0_54,
+	&__clk_0_55,
+	&__clk_0_56,
+	&__clk_0_63,
+
+	&__clk_1_2,
+	&__clk_1_4,
+	&__clk_1_5,
+	&__clk_1_6,
+	&__clk_1_7,
+	&__clk_1_24,
+	&__clk_1_25,
+	&__clk_1_26,
+	&__clk_1_27,
+	&__clk_1_28,
+	&__clk_1_29,
+	&__clk_1_34,
+	&__clk_1_36,
+	&__clk_1_37,
+	NULL,
+};
+
+
+static struct clk * const enable_clks[] __initconst = {
+	/* make sure these clocks are enabled */
+	&__clk_0_18, /* intc0 */
+	&__clk_0_19, /* intc0 */
+	&__clk_0_20, /* intc0 */
+	&__clk_0_24, /* uart0 */
+	&__clk_0_25, /* uart1 */
+	&__clk_0_26, /* uart2 */
+	&__clk_0_27, /* uart3 */
+
+	&__clk_0_33, /* pit.1 */
+	&__clk_0_37, /* eport */
+	&__clk_0_48, /* pll */
+
+	&__clk_1_36, /* CCM/reset module/Power management */
+	&__clk_1_37, /* gpio */
+};
+static struct clk * const disable_clks[] __initconst = {
+	&__clk_0_8, /* can.0 */
+	&__clk_0_9, /* can.1 */
+	&__clk_0_14, /* i2c.1 */
+	&__clk_0_15, /* dspi.1 */
+	&__clk_0_17, /* eDMA */
+	&__clk_0_22, /* i2c.0 */
+	&__clk_0_23, /* dspi.0 */
+	&__clk_0_28, /* tmr.1 */
+	&__clk_0_29, /* tmr.2 */
+	&__clk_0_30, /* tmr.2 */
+	&__clk_0_31, /* tmr.3 */
+	&__clk_0_32, /* pit.0 */
+	&__clk_0_34, /* pit.2 */
+	&__clk_0_35, /* pit.3 */
+	&__clk_0_38, /* adc */
+	&__clk_0_39, /* dac */
+	&__clk_0_44, /* usb otg */
+	&__clk_0_45, /* usb host */
+	&__clk_0_47, /* ssi.0 */
+	&__clk_0_49, /* rng */
+	&__clk_0_50, /* ssi.1 */
+	&__clk_0_51, /* eSDHC */
+	&__clk_0_53, /* enet-fec */
+	&__clk_0_54, /* enet-fec */
+	&__clk_0_55, /* switch.0 */
+	&__clk_0_56, /* switch.1 */
+
+	&__clk_1_2, /* 1-wire */
+	&__clk_1_4, /* i2c.2 */
+	&__clk_1_5, /* i2c.3 */
+	&__clk_1_6, /* i2c.4 */
+	&__clk_1_7, /* i2c.5 */
+	&__clk_1_24, /* uart 4 */
+	&__clk_1_25, /* uart 5 */
+	&__clk_1_26, /* uart 6 */
+	&__clk_1_27, /* uart 7 */
+	&__clk_1_28, /* uart 8 */
+	&__clk_1_29, /* uart 9 */
+};
+
+static void __init m5441x_clk_init(void)
+{
+	unsigned i;
+
+	for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
+		__clk_init_enabled(enable_clks[i]);
+	/* make sure these clocks are disabled */
+	for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
+		__clk_init_disabled(disable_clks[i]);
+}
+
+static void __init m5441x_uarts_init(void)
+{
+	__raw_writeb(0x0f, MCFGPIO_PAR_UART0);
+	__raw_writeb(0x00, MCFGPIO_PAR_UART1);
+	__raw_writeb(0x00, MCFGPIO_PAR_UART2);
+}
+
+static void __init m5441x_fec_init(void)
+{
+	__raw_writeb(0x03, MCFGPIO_PAR_FEC);
+}
+
+void __init config_BSP(char *commandp, int size)
+{
+	m5441x_clk_init();
+	mach_sched_init = hw_timer_init;
+	m5441x_uarts_init();
+	m5441x_fec_init();
+}

arch/m68k/platform/coldfire/timers.c

@@ -36,7 +36,7 @@
  */
 void coldfire_profile_init(void);
 
-#if defined(CONFIG_M532x)
+#if defined(CONFIG_M532x) || defined(CONFIG_M5441x)
 #define	__raw_readtrr	__raw_readl
 #define	__raw_writetrr	__raw_writel
 #else