Skip to content

L
linux
Commit bee7a18e authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
Browse files
Options

ARM: shmobile: sh73a0 dtsi: Add PM domain support 

Add a device node for the System Controller, with subnodes that
represent the hardware power area hierarchy.
Hook up all devices to their respective PM domains.

Note that unlike on R-Mobile A1 (r8a7740), PM domain D4 can be powered
down without ill effects on s2ram behavior, just like on SH-Mobile AP4
(sh7372).  Hence we can postpone adding a (minimal) device node for the
Coresight-ETM hardware block.

The System Controller is also used by the R-Mobile Reset driver, which
can now restart the system.
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 05813a81
Hide whitespace changes
Inline Side-by-side
Showing with 142 additions and 2 deletions
arch/arm/boot/dts/sh73a0.dtsi
View file @ bee7a18e
......@@ -27,12 +27,14 @@ cpu@0 {
compatible = "arm,cortex-a9";
reg = <0>;
clock-frequency = <1196000000>;
power-domains = <&pd_a2sl>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
clock-frequency = <1196000000>;
power-domains = <&pd_a2sl>;
};
};
......@@ -57,6 +59,7 @@ sbsc2: memory-controller@fb400000 {
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
<0 38 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sec", "temp";
power-domains = <&pd_a4bc1>;
};
sbsc1: memory-controller@fe400000 {
......@@ -65,6 +68,7 @@ sbsc1: memory-controller@fe400000 {
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
<0 36 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sec", "temp";
power-domains = <&pd_a4bc0>;
};
pmu {
......@@ -77,11 +81,12 @@ cmt1: timer@e6138000 {
compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
reg = <0xe6138000 0x200>;
interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
clock-names = "fck";
power-domains = <&pd_c5>;
renesas,channels-mask = <0x3f>;
clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
clock-names = "fck";
status = "disabled";
};
......@@ -103,6 +108,7 @@ irqpin0: irqpin@e6900000 {
0 7 IRQ_TYPE_LEVEL_HIGH
0 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
power-domains = <&pd_a4s>;
control-parent;
};
......@@ -124,6 +130,7 @@ irqpin1: irqpin@e6900004 {
0 15 IRQ_TYPE_LEVEL_HIGH
0 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
power-domains = <&pd_a4s>;
control-parent;
};
......@@ -145,6 +152,7 @@ irqpin2: irqpin@e6900008 {
0 23 IRQ_TYPE_LEVEL_HIGH
0 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
power-domains = <&pd_a4s>;
control-parent;
};
......@@ -166,6 +174,7 @@ irqpin3: irqpin@e690000c {
0 31 IRQ_TYPE_LEVEL_HIGH
0 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
power-domains = <&pd_a4s>;
control-parent;
};
......@@ -179,6 +188,7 @@ i2c0: i2c@e6820000 {
0 169 IRQ_TYPE_LEVEL_HIGH
0 170 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -192,6 +202,7 @@ i2c1: i2c@e6822000 {
0 53 IRQ_TYPE_LEVEL_HIGH
0 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -205,6 +216,7 @@ i2c2: i2c@e6824000 {
0 173 IRQ_TYPE_LEVEL_HIGH
0 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -218,6 +230,7 @@ i2c3: i2c@e6826000 {
0 185 IRQ_TYPE_LEVEL_HIGH
0 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -231,6 +244,7 @@ i2c4: i2c@e6828000 {
0 189 IRQ_TYPE_LEVEL_HIGH
0 190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
power-domains = <&pd_c5>;
status = "disabled";
};
......@@ -240,6 +254,7 @@ mmcif: mmc@e6bd0000 {
interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
0 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
power-domains = <&pd_a3sp>;
reg-io-width = <4>;
status = "disabled";
};
......@@ -251,6 +266,7 @@ sdhi0: sd@ee100000 {
0 84 IRQ_TYPE_LEVEL_HIGH
0 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
power-domains = <&pd_a3sp>;
cap-sd-highspeed;
status = "disabled";
};
......@@ -262,6 +278,7 @@ sdhi1: sd@ee120000 {
interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
0 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
power-domains = <&pd_a3sp>;
toshiba,mmc-wrprotect-disable;
cap-sd-highspeed;
status = "disabled";
......@@ -273,6 +290,7 @@ sdhi2: sd@ee140000 {
interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
power-domains = <&pd_a3sp>;
toshiba,mmc-wrprotect-disable;
cap-sd-highspeed;
status = "disabled";
......@@ -284,6 +302,7 @@ scifa0: serial@e6c40000 {
interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -293,6 +312,7 @@ scifa1: serial@e6c50000 {
interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -302,6 +322,7 @@ scifa2: serial@e6c60000 {
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -311,6 +332,7 @@ scifa3: serial@e6c70000 {
interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -320,6 +342,7 @@ scifa4: serial@e6c80000 {
interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -329,6 +352,7 @@ scifa5: serial@e6cb0000 {
interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -338,6 +362,7 @@ scifa6: serial@e6cc0000 {
interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -347,6 +372,7 @@ scifa7: serial@e6cd0000 {
interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -356,6 +382,7 @@ scifb8: serial@e6c30000 {
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -374,6 +401,117 @@ pfc: pfc@e6050000 {
<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
power-domains = <&pd_c5>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
pm-domains {
pd_c5: c5 {
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
pd_c4: c4@0 {
reg = <0>;
#power-domain-cells = <0>;
};
pd_d4: d4@1 {
reg = <1>;
#power-domain-cells = <0>;
};
pd_a4bc0: a4bc0@4 {
reg = <4>;
#power-domain-cells = <0>;
};
pd_a4bc1: a4bc1@5 {
reg = <5>;
#power-domain-cells = <0>;
};
pd_a4lc0: a4lc0@6 {
reg = <6>;
#power-domain-cells = <0>;
};
pd_a4lc1: a4lc1@7 {
reg = <7>;
#power-domain-cells = <0>;
};
pd_a4mp: a4mp@8 {
reg = <8>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
pd_a3mp: a3mp@9 {
reg = <9>;
#power-domain-cells = <0>;
};
pd_a3vc: a3vc@10 {
reg = <10>;
#power-domain-cells = <0>;
};
};
pd_a4rm: a4rm@12 {
reg = <12>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
pd_a3r: a3r@13 {
reg = <13>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
pd_a2rv: a2rv@14 {
reg = <14>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
};
};
};
pd_a4s: a4s@16 {
reg = <16>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
pd_a3sp: a3sp@17 {
reg = <17>;
#power-domain-cells = <0>;
};
pd_a3sg: a3sg@18 {
reg = <18>;
#power-domain-cells = <0>;
};
pd_a3sm: a3sm@19 {
reg = <19>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
pd_a2sl: a2sl@20 {
reg = <20>;
#power-domain-cells = <0>;
};
};
};
};
};
};
sh_fsi2: sound@ec230000 {
......@@ -381,6 +519,7 @@ sh_fsi2: sound@ec230000 {
compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
reg = <0xec230000 0x400>;
interrupts = <0 146 0x4>;
power-domains = <&pd_a4mp>;
status = "disabled";
};
......@@ -393,6 +532,7 @@ bsc: bus@fec10000 {
reg = <0xfec10000 0x400>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&zb_clk>;
power-domains = <&pd_a4s>;
};
clocks {
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7