Commit bf002c10 authored by Ville Syrjälä's avatar Ville Syrjälä

drm/i915: W/A for underruns with WM1+ disabled on icl

Disabling WM1+ on ICL causes tons of underruns with
linear/X-tiled framebuffers. We can avoid this by flipping
on a chicken bit affecting the way the hw fill the FIFO.
This may not be the final solution but should hopefully
avoid some underruns in the meantime.

v2: Apparently PIPE_CHICKEN is icl+ only
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190204202232.27153-1-ville.syrjala@linux.intel.comReviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
parent 108d14bd
...@@ -7618,6 +7618,7 @@ enum { ...@@ -7618,6 +7618,7 @@ enum {
#define _PIPEB_CHICKEN 0x71038 #define _PIPEB_CHICKEN 0x71038
#define _PIPEC_CHICKEN 0x72038 #define _PIPEC_CHICKEN 0x72038
#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
#define PM_FILL_MAINTAIN_DBUF_FULLNESS (1 << 0)
#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
_PIPEB_CHICKEN) _PIPEB_CHICKEN)
......
...@@ -3911,6 +3911,12 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc) ...@@ -3911,6 +3911,12 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
*/ */
tmp |= PER_PIXEL_ALPHA_BYPASS_EN; tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
/*
* W/A for underruns with linear/X-tiled with
* WM1+ disabled.
*/
tmp |= PM_FILL_MAINTAIN_DBUF_FULLNESS;
I915_WRITE(PIPE_CHICKEN(pipe), tmp); I915_WRITE(PIPE_CHICKEN(pipe), tmp);
} }
......
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