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Commit bf6534a1 authored by Maxime Ripard's avatar Maxime Ripard
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ARM: sunxi: dt: Convert to the new clock compatibles 

Switch the device tree to the new compatibles introduced in the clock drivers
to have a common pattern accross all Allwinner SoCs.
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 7902763e
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Showing with 110 additions and 110 deletions
arch/arm/boot/dts/sun4i-a10.dtsi
View file @ bf6534a1
......@@ -60,7 +60,7 @@ dummy: dummy {
osc24M: clk@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-osc-clk";
compatible = "allwinner,sun4i-a10-osc-clk";
reg = <0x01c20050 0x4>;
clock-frequency = <24000000>;
clock-output-names = "osc24M";
......@@ -75,7 +75,7 @@ osc32k: clk@0 {
pll1: clk@01c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-pll1-clk";
compatible = "allwinner,sun4i-a10-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll1";
......@@ -83,7 +83,7 @@ pll1: clk@01c20000 {
pll4: clk@01c20018 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-pll1-clk";
compatible = "allwinner,sun4i-a10-pll1-clk";
reg = <0x01c20018 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll4";
......@@ -91,7 +91,7 @@ pll4: clk@01c20018 {
pll5: clk@01c20020 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll5-clk";
compatible = "allwinner,sun4i-a10-pll5-clk";
reg = <0x01c20020 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll5_ddr", "pll5_other";
......@@ -99,7 +99,7 @@ pll5: clk@01c20020 {
pll6: clk@01c20028 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll6-clk";
compatible = "allwinner,sun4i-a10-pll6-clk";
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll6_sata", "pll6_other", "pll6";
......@@ -108,7 +108,7 @@ pll6: clk@01c20028 {
/* dummy is 200M */
cpu: cpu@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-cpu-clk";
compatible = "allwinner,sun4i-a10-cpu-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
clock-output-names = "cpu";
......@@ -116,7 +116,7 @@ cpu: cpu@01c20054 {
axi: axi@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-axi-clk";
compatible = "allwinner,sun4i-a10-axi-clk";
reg = <0x01c20054 0x4>;
clocks = <&cpu>;
clock-output-names = "axi";
......@@ -124,7 +124,7 @@ axi: axi@01c20054 {
axi_gates: clk@01c2005c {
#clock-cells = <1>;
compatible = "allwinner,sun4i-axi-gates-clk";
compatible = "allwinner,sun4i-a10-axi-gates-clk";
reg = <0x01c2005c 0x4>;
clocks = <&axi>;
clock-output-names = "axi_dram";
......@@ -132,7 +132,7 @@ axi_gates: clk@01c2005c {
ahb: ahb@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-ahb-clk";
compatible = "allwinner,sun4i-a10-ahb-clk";
reg = <0x01c20054 0x4>;
clocks = <&axi>;
clock-output-names = "ahb";
......@@ -140,7 +140,7 @@ ahb: ahb@01c20054 {
ahb_gates: clk@01c20060 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-ahb-gates-clk";
compatible = "allwinner,sun4i-a10-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
clock-output-names = "ahb_usb0", "ahb_ehci0",
......@@ -158,7 +158,7 @@ ahb_gates: clk@01c20060 {
apb0: apb0@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb0-clk";
compatible = "allwinner,sun4i-a10-apb0-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb>;
clock-output-names = "apb0";
......@@ -166,7 +166,7 @@ apb0: apb0@01c20054 {
apb0_gates: clk@01c20068 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-apb0-gates-clk";
compatible = "allwinner,sun4i-a10-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
clock-output-names = "apb0_codec", "apb0_spdif",
......@@ -176,7 +176,7 @@ apb0_gates: clk@01c20068 {
apb1_mux: apb1_mux@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb1-mux-clk";
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
clock-output-names = "apb1_mux";
......@@ -184,7 +184,7 @@ apb1_mux: apb1_mux@01c20058 {
apb1: apb1@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb1-clk";
compatible = "allwinner,sun4i-a10-apb1-clk";
reg = <0x01c20058 0x4>;
clocks = <&apb1_mux>;
clock-output-names = "apb1";
......@@ -192,7 +192,7 @@ apb1: apb1@01c20058 {
apb1_gates: clk@01c2006c {
#clock-cells = <1>;
compatible = "allwinner,sun4i-apb1-gates-clk";
compatible = "allwinner,sun4i-a10-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
......@@ -205,7 +205,7 @@ apb1_gates: clk@01c2006c {
nand_clk: clk@01c20080 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20080 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "nand";
......@@ -213,7 +213,7 @@ nand_clk: clk@01c20080 {
ms_clk: clk@01c20084 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20084 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ms";
......@@ -221,7 +221,7 @@ ms_clk: clk@01c20084 {
mmc0_clk: clk@01c20088 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc0";
......@@ -229,7 +229,7 @@ mmc0_clk: clk@01c20088 {
mmc1_clk: clk@01c2008c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c2008c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc1";
......@@ -237,7 +237,7 @@ mmc1_clk: clk@01c2008c {
mmc2_clk: clk@01c20090 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20090 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc2";
......@@ -245,7 +245,7 @@ mmc2_clk: clk@01c20090 {
mmc3_clk: clk@01c20094 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20094 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc3";
......@@ -253,7 +253,7 @@ mmc3_clk: clk@01c20094 {
ts_clk: clk@01c20098 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20098 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ts";
......@@ -261,7 +261,7 @@ ts_clk: clk@01c20098 {
ss_clk: clk@01c2009c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c2009c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ss";
......@@ -269,7 +269,7 @@ ss_clk: clk@01c2009c {
spi0_clk: clk@01c200a0 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200a0 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi0";
......@@ -277,7 +277,7 @@ spi0_clk: clk@01c200a0 {
spi1_clk: clk@01c200a4 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200a4 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi1";
......@@ -285,7 +285,7 @@ spi1_clk: clk@01c200a4 {
spi2_clk: clk@01c200a8 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200a8 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi2";
......@@ -293,7 +293,7 @@ spi2_clk: clk@01c200a8 {
pata_clk: clk@01c200ac {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200ac 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "pata";
......@@ -301,7 +301,7 @@ pata_clk: clk@01c200ac {
ir0_clk: clk@01c200b0 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200b0 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ir0";
......@@ -309,7 +309,7 @@ ir0_clk: clk@01c200b0 {
ir1_clk: clk@01c200b4 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200b4 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ir1";
......@@ -326,7 +326,7 @@ usb_clk: clk@01c200cc {
spi3_clk: clk@01c200d4 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200d4 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi3";
......
arch/arm/boot/dts/sun5i-a10s.dtsi
View file @ bf6534a1
......@@ -53,7 +53,7 @@ dummy: dummy {
osc24M: clk@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-osc-clk";
compatible = "allwinner,sun4i-a10-osc-clk";
reg = <0x01c20050 0x4>;
clock-frequency = <24000000>;
clock-output-names = "osc24M";
......@@ -68,7 +68,7 @@ osc32k: clk@0 {
pll1: clk@01c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-pll1-clk";
compatible = "allwinner,sun4i-a10-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll1";
......@@ -76,7 +76,7 @@ pll1: clk@01c20000 {
pll4: clk@01c20018 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-pll1-clk";
compatible = "allwinner,sun4i-a10-pll1-clk";
reg = <0x01c20018 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll4";
......@@ -84,7 +84,7 @@ pll4: clk@01c20018 {
pll5: clk@01c20020 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll5-clk";
compatible = "allwinner,sun4i-a10-pll5-clk";
reg = <0x01c20020 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll5_ddr", "pll5_other";
......@@ -92,7 +92,7 @@ pll5: clk@01c20020 {
pll6: clk@01c20028 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll6-clk";
compatible = "allwinner,sun4i-a10-pll6-clk";
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll6_sata", "pll6_other", "pll6";
......@@ -101,7 +101,7 @@ pll6: clk@01c20028 {
/* dummy is 200M */
cpu: cpu@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-cpu-clk";
compatible = "allwinner,sun4i-a10-cpu-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
clock-output-names = "cpu";
......@@ -109,7 +109,7 @@ cpu: cpu@01c20054 {
axi: axi@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-axi-clk";
compatible = "allwinner,sun4i-a10-axi-clk";
reg = <0x01c20054 0x4>;
clocks = <&cpu>;
clock-output-names = "axi";
......@@ -117,7 +117,7 @@ axi: axi@01c20054 {
axi_gates: clk@01c2005c {
#clock-cells = <1>;
compatible = "allwinner,sun4i-axi-gates-clk";
compatible = "allwinner,sun4i-a10-axi-gates-clk";
reg = <0x01c2005c 0x4>;
clocks = <&axi>;
clock-output-names = "axi_dram";
......@@ -125,7 +125,7 @@ axi_gates: clk@01c2005c {
ahb: ahb@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-ahb-clk";
compatible = "allwinner,sun4i-a10-ahb-clk";
reg = <0x01c20054 0x4>;
clocks = <&axi>;
clock-output-names = "ahb";
......@@ -147,7 +147,7 @@ ahb_gates: clk@01c20060 {
apb0: apb0@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb0-clk";
compatible = "allwinner,sun4i-a10-apb0-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb>;
clock-output-names = "apb0";
......@@ -164,7 +164,7 @@ apb0_gates: clk@01c20068 {
apb1_mux: apb1_mux@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb1-mux-clk";
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
clock-output-names = "apb1_mux";
......@@ -172,7 +172,7 @@ apb1_mux: apb1_mux@01c20058 {
apb1: apb1@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb1-clk";
compatible = "allwinner,sun4i-a10-apb1-clk";
reg = <0x01c20058 0x4>;
clocks = <&apb1_mux>;
clock-output-names = "apb1";
......@@ -190,7 +190,7 @@ apb1_gates: clk@01c2006c {
nand_clk: clk@01c20080 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20080 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "nand";
......@@ -198,7 +198,7 @@ nand_clk: clk@01c20080 {
ms_clk: clk@01c20084 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20084 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ms";
......@@ -206,7 +206,7 @@ ms_clk: clk@01c20084 {
mmc0_clk: clk@01c20088 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc0";
......@@ -214,7 +214,7 @@ mmc0_clk: clk@01c20088 {
mmc1_clk: clk@01c2008c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c2008c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc1";
......@@ -222,7 +222,7 @@ mmc1_clk: clk@01c2008c {
mmc2_clk: clk@01c20090 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20090 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc2";
......@@ -230,7 +230,7 @@ mmc2_clk: clk@01c20090 {
ts_clk: clk@01c20098 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20098 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ts";
......@@ -238,7 +238,7 @@ ts_clk: clk@01c20098 {
ss_clk: clk@01c2009c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c2009c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ss";
......@@ -246,7 +246,7 @@ ss_clk: clk@01c2009c {
spi0_clk: clk@01c200a0 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200a0 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi0";
......@@ -254,7 +254,7 @@ spi0_clk: clk@01c200a0 {
spi1_clk: clk@01c200a4 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200a4 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi1";
......@@ -262,7 +262,7 @@ spi1_clk: clk@01c200a4 {
spi2_clk: clk@01c200a8 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200a8 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi2";
......@@ -270,7 +270,7 @@ spi2_clk: clk@01c200a8 {
ir0_clk: clk@01c200b0 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200b0 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ir0";
......@@ -287,7 +287,7 @@ usb_clk: clk@01c200cc {
mbus_clk: clk@01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c2015c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mbus";
......
arch/arm/boot/dts/sun5i-a13.dtsi
View file @ bf6534a1
......@@ -54,7 +54,7 @@ dummy: dummy {
osc24M: clk@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-osc-clk";
compatible = "allwinner,sun4i-a10-osc-clk";
reg = <0x01c20050 0x4>;
clock-frequency = <24000000>;
clock-output-names = "osc24M";
......@@ -69,7 +69,7 @@ osc32k: clk@0 {
pll1: clk@01c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-pll1-clk";
compatible = "allwinner,sun4i-a10-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll1";
......@@ -77,7 +77,7 @@ pll1: clk@01c20000 {
pll4: clk@01c20018 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-pll1-clk";
compatible = "allwinner,sun4i-a10-pll1-clk";
reg = <0x01c20018 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll4";
......@@ -85,7 +85,7 @@ pll4: clk@01c20018 {
pll5: clk@01c20020 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll5-clk";
compatible = "allwinner,sun4i-a10-pll5-clk";
reg = <0x01c20020 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll5_ddr", "pll5_other";
......@@ -93,7 +93,7 @@ pll5: clk@01c20020 {
pll6: clk@01c20028 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll6-clk";
compatible = "allwinner,sun4i-a10-pll6-clk";
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll6_sata", "pll6_other", "pll6";
......@@ -102,7 +102,7 @@ pll6: clk@01c20028 {
/* dummy is 200M */
cpu: cpu@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-cpu-clk";
compatible = "allwinner,sun4i-a10-cpu-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
clock-output-names = "cpu";
......@@ -110,7 +110,7 @@ cpu: cpu@01c20054 {
axi: axi@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-axi-clk";
compatible = "allwinner,sun4i-a10-axi-clk";
reg = <0x01c20054 0x4>;
clocks = <&cpu>;
clock-output-names = "axi";
......@@ -118,7 +118,7 @@ axi: axi@01c20054 {
axi_gates: clk@01c2005c {
#clock-cells = <1>;
compatible = "allwinner,sun4i-axi-gates-clk";
compatible = "allwinner,sun4i-a10-axi-gates-clk";
reg = <0x01c2005c 0x4>;
clocks = <&axi>;
clock-output-names = "axi_dram";
......@@ -126,7 +126,7 @@ axi_gates: clk@01c2005c {
ahb: ahb@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-ahb-clk";
compatible = "allwinner,sun4i-a10-ahb-clk";
reg = <0x01c20054 0x4>;
clocks = <&axi>;
clock-output-names = "ahb";
......@@ -147,7 +147,7 @@ ahb_gates: clk@01c20060 {
apb0: apb0@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb0-clk";
compatible = "allwinner,sun4i-a10-apb0-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb>;
clock-output-names = "apb0";
......@@ -163,7 +163,7 @@ apb0_gates: clk@01c20068 {
apb1_mux: apb1_mux@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb1-mux-clk";
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
clock-output-names = "apb1_mux";
......@@ -171,7 +171,7 @@ apb1_mux: apb1_mux@01c20058 {
apb1: apb1@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb1-clk";
compatible = "allwinner,sun4i-a10-apb1-clk";
reg = <0x01c20058 0x4>;
clocks = <&apb1_mux>;
clock-output-names = "apb1";
......@@ -188,7 +188,7 @@ apb1_gates: clk@01c2006c {
nand_clk: clk@01c20080 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20080 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "nand";
......@@ -196,7 +196,7 @@ nand_clk: clk@01c20080 {
ms_clk: clk@01c20084 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20084 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ms";
......@@ -204,7 +204,7 @@ ms_clk: clk@01c20084 {
mmc0_clk: clk@01c20088 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc0";
......@@ -212,7 +212,7 @@ mmc0_clk: clk@01c20088 {
mmc1_clk: clk@01c2008c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c2008c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc1";
......@@ -220,7 +220,7 @@ mmc1_clk: clk@01c2008c {
mmc2_clk: clk@01c20090 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20090 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc2";
......@@ -228,7 +228,7 @@ mmc2_clk: clk@01c20090 {
ts_clk: clk@01c20098 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20098 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ts";
......@@ -236,7 +236,7 @@ ts_clk: clk@01c20098 {
ss_clk: clk@01c2009c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c2009c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ss";
......@@ -244,7 +244,7 @@ ss_clk: clk@01c2009c {
spi0_clk: clk@01c200a0 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200a0 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi0";
......@@ -252,7 +252,7 @@ spi0_clk: clk@01c200a0 {
spi1_clk: clk@01c200a4 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200a4 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi1";
......@@ -260,7 +260,7 @@ spi1_clk: clk@01c200a4 {
spi2_clk: clk@01c200a8 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200a8 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi2";
......@@ -268,7 +268,7 @@ spi2_clk: clk@01c200a8 {
ir0_clk: clk@01c200b0 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200b0 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ir0";
......@@ -285,7 +285,7 @@ usb_clk: clk@01c200cc {
mbus_clk: clk@01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c2015c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mbus";
......
arch/arm/boot/dts/sun6i-a31.dtsi
View file @ bf6534a1
......@@ -95,7 +95,7 @@ pll6: clk@01c20028 {
cpu: cpu@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-cpu-clk";
compatible = "allwinner,sun4i-a10-cpu-clk";
reg = <0x01c20050 0x4>;
/*
......@@ -110,7 +110,7 @@ cpu: cpu@01c20050 {
axi: axi@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-axi-clk";
compatible = "allwinner,sun4i-a10-axi-clk";
reg = <0x01c20050 0x4>;
clocks = <&cpu>;
clock-output-names = "axi";
......@@ -126,7 +126,7 @@ ahb1_mux: ahb1_mux@01c20054 {
ahb1: ahb1@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-ahb-clk";
compatible = "allwinner,sun4i-a10-ahb-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb1_mux>;
clock-output-names = "ahb1";
......@@ -155,7 +155,7 @@ ahb1_gates: clk@01c20060 {
apb1: apb1@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb0-clk";
compatible = "allwinner,sun4i-a10-apb0-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb1>;
clock-output-names = "apb1";
......@@ -173,7 +173,7 @@ apb1_gates: clk@01c20068 {
apb2_mux: apb2_mux@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb1-mux-clk";
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
clock-output-names = "apb2_mux";
......
arch/arm/boot/dts/sun7i-a20.dtsi
View file @ bf6534a1
......@@ -64,7 +64,7 @@ clocks {
osc24M: clk@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-osc-clk";
compatible = "allwinner,sun4i-a10-osc-clk";
reg = <0x01c20050 0x4>;
clock-frequency = <24000000>;
clock-output-names = "osc24M";
......@@ -79,7 +79,7 @@ osc32k: clk@0 {
pll1: clk@01c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-pll1-clk";
compatible = "allwinner,sun4i-a10-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll1";
......@@ -87,7 +87,7 @@ pll1: clk@01c20000 {
pll4: clk@01c20018 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-pll1-clk";
compatible = "allwinner,sun4i-a10-pll1-clk";
reg = <0x01c20018 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll4";
......@@ -95,7 +95,7 @@ pll4: clk@01c20018 {
pll5: clk@01c20020 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll5-clk";
compatible = "allwinner,sun4i-a10-pll5-clk";
reg = <0x01c20020 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll5_ddr", "pll5_other";
......@@ -103,7 +103,7 @@ pll5: clk@01c20020 {
pll6: clk@01c20028 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll6-clk";
compatible = "allwinner,sun4i-a10-pll6-clk";
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll6_sata", "pll6_other", "pll6";
......@@ -111,7 +111,7 @@ pll6: clk@01c20028 {
cpu: cpu@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-cpu-clk";
compatible = "allwinner,sun4i-a10-cpu-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
clock-output-names = "cpu";
......@@ -119,7 +119,7 @@ cpu: cpu@01c20054 {
axi: axi@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-axi-clk";
compatible = "allwinner,sun4i-a10-axi-clk";
reg = <0x01c20054 0x4>;
clocks = <&cpu>;
clock-output-names = "axi";
......@@ -127,7 +127,7 @@ axi: axi@01c20054 {
ahb: ahb@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-ahb-clk";
compatible = "allwinner,sun4i-a10-ahb-clk";
reg = <0x01c20054 0x4>;
clocks = <&axi>;
clock-output-names = "ahb";
......@@ -155,7 +155,7 @@ ahb_gates: clk@01c20060 {
apb0: apb0@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb0-clk";
compatible = "allwinner,sun4i-a10-apb0-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb>;
clock-output-names = "apb0";
......@@ -174,7 +174,7 @@ apb0_gates: clk@01c20068 {
apb1_mux: apb1_mux@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb1-mux-clk";
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
clock-output-names = "apb1_mux";
......@@ -182,7 +182,7 @@ apb1_mux: apb1_mux@01c20058 {
apb1: apb1@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb1-clk";
compatible = "allwinner,sun4i-a10-apb1-clk";
reg = <0x01c20058 0x4>;
clocks = <&apb1_mux>;
clock-output-names = "apb1";
......@@ -203,7 +203,7 @@ apb1_gates: clk@01c2006c {
nand_clk: clk@01c20080 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20080 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "nand";
......@@ -211,7 +211,7 @@ nand_clk: clk@01c20080 {
ms_clk: clk@01c20084 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20084 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ms";
......@@ -219,7 +219,7 @@ ms_clk: clk@01c20084 {
mmc0_clk: clk@01c20088 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc0";
......@@ -227,7 +227,7 @@ mmc0_clk: clk@01c20088 {
mmc1_clk: clk@01c2008c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c2008c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc1";
......@@ -235,7 +235,7 @@ mmc1_clk: clk@01c2008c {
mmc2_clk: clk@01c20090 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20090 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc2";
......@@ -243,7 +243,7 @@ mmc2_clk: clk@01c20090 {
mmc3_clk: clk@01c20094 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20094 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc3";
......@@ -251,7 +251,7 @@ mmc3_clk: clk@01c20094 {
ts_clk: clk@01c20098 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20098 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ts";
......@@ -259,7 +259,7 @@ ts_clk: clk@01c20098 {
ss_clk: clk@01c2009c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c2009c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ss";
......@@ -267,7 +267,7 @@ ss_clk: clk@01c2009c {
spi0_clk: clk@01c200a0 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200a0 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi0";
......@@ -275,7 +275,7 @@ spi0_clk: clk@01c200a0 {
spi1_clk: clk@01c200a4 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200a4 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi1";
......@@ -283,7 +283,7 @@ spi1_clk: clk@01c200a4 {
spi2_clk: clk@01c200a8 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200a8 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi2";
......@@ -291,7 +291,7 @@ spi2_clk: clk@01c200a8 {
pata_clk: clk@01c200ac {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200ac 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "pata";
......@@ -299,7 +299,7 @@ pata_clk: clk@01c200ac {
ir0_clk: clk@01c200b0 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200b0 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ir0";
......@@ -307,7 +307,7 @@ ir0_clk: clk@01c200b0 {
ir1_clk: clk@01c200b4 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200b4 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ir1";
......@@ -324,7 +324,7 @@ usb_clk: clk@01c200cc {
spi3_clk: clk@01c200d4 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200d4 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi3";
......@@ -332,7 +332,7 @@ spi3_clk: clk@01c200d4 {
mbus_clk: clk@01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c2015c 0x4>;
clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
clock-output-names = "mbus";
......
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