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Commit bf66e3c4 authored by Nicholas Piggin's avatar Nicholas Piggin Committed by Michael Ellerman
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powerpc/64s/exception: fix indenting irregularities 

Generally, macros that result in instructions being expanded are
indented by a tab, and those that don't have no indent. Fix the
obvious cases that go contrary to style.

No generated code change.
Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 1b4d4a79
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Showing with 46 additions and 46 deletions
arch/powerpc/kernel/exceptions-64s.S
View file @ bf66e3c4
...@@ -261,16 +261,16 @@ END_FTR_SECTION_NESTED(ftr,ftr,943) ...@@ -261,16 +261,16 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
cmpwi r10,KVM_GUEST_MODE_SKIP cmpwi r10,KVM_GUEST_MODE_SKIP
beq 89f beq 89f
.else .else
BEGIN_FTR_SECTION_NESTED(947) BEGIN_FTR_SECTION_NESTED(947)
ld r10,\area+EX_CFAR(r13) ld r10,\area+EX_CFAR(r13)
std r10,HSTATE_CFAR(r13) std r10,HSTATE_CFAR(r13)
END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947) END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947)
.endif .endif
BEGIN_FTR_SECTION_NESTED(948) BEGIN_FTR_SECTION_NESTED(948)
ld r10,\area+EX_PPR(r13) ld r10,\area+EX_PPR(r13)
std r10,HSTATE_PPR(r13) std r10,HSTATE_PPR(r13)
END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948) END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948)
ld r10,\area+EX_R10(r13) ld r10,\area+EX_R10(r13)
std r12,HSTATE_SCRATCH0(r13) std r12,HSTATE_SCRATCH0(r13)
sldi r12,r9,32 sldi r12,r9,32
...@@ -372,10 +372,10 @@ END_FTR_SECTION_NESTED(ftr,ftr,943) ...@@ -372,10 +372,10 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
std r9,GPR11(r1); \ std r9,GPR11(r1); \
std r10,GPR12(r1); \ std r10,GPR12(r1); \
std r11,GPR13(r1); \ std r11,GPR13(r1); \
BEGIN_FTR_SECTION_NESTED(66); \ BEGIN_FTR_SECTION_NESTED(66); \
ld r10,area+EX_CFAR(r13); \ ld r10,area+EX_CFAR(r13); \
std r10,ORIG_GPR3(r1); \ std r10,ORIG_GPR3(r1); \
END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \
GET_CTR(r10, area); \ GET_CTR(r10, area); \
std r10,_CTR(r1); std r10,_CTR(r1);
...@@ -794,7 +794,7 @@ EXC_REAL_BEGIN(system_reset, 0x100, 0x100) ...@@ -794,7 +794,7 @@ EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
* but we branch to the 0xc000... address so we can turn on relocation * but we branch to the 0xc000... address so we can turn on relocation
* with mtmsr. * with mtmsr.
*/ */
BEGIN_FTR_SECTION BEGIN_FTR_SECTION
mfspr r10,SPRN_SRR1 mfspr r10,SPRN_SRR1
rlwinm. r10,r10,47-31,30,31 rlwinm. r10,r10,47-31,30,31
beq- 1f beq- 1f
...@@ -803,7 +803,7 @@ EXC_REAL_BEGIN(system_reset, 0x100, 0x100) ...@@ -803,7 +803,7 @@ EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
bltlr cr1 /* no state loss, return to idle caller */ bltlr cr1 /* no state loss, return to idle caller */
BRANCH_TO_C000(r10, system_reset_idle_common) BRANCH_TO_C000(r10, system_reset_idle_common)
1: 1:
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
#endif #endif
KVMTEST EXC_STD 0x100 KVMTEST EXC_STD 0x100
...@@ -1151,10 +1151,10 @@ END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) ...@@ -1151,10 +1151,10 @@ END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
* *
* Go back to nap/sleep/winkle mode again if (b) is true. * Go back to nap/sleep/winkle mode again if (b) is true.
*/ */
BEGIN_FTR_SECTION BEGIN_FTR_SECTION
rlwinm. r11,r12,47-31,30,31 rlwinm. r11,r12,47-31,30,31
bne machine_check_idle_common bne machine_check_idle_common
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
#endif #endif
/* /*
...@@ -1261,13 +1261,13 @@ EXC_COMMON_BEGIN(mce_return) ...@@ -1261,13 +1261,13 @@ EXC_COMMON_BEGIN(mce_return)
b . b .
EXC_REAL_BEGIN(data_access, 0x300, 0x80) EXC_REAL_BEGIN(data_access, 0x300, 0x80)
SET_SCRATCH0(r13) /* save r13 */ SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXGEN EXCEPTION_PROLOG_0 PACA_EXGEN
b tramp_real_data_access b tramp_real_data_access
EXC_REAL_END(data_access, 0x300, 0x80) EXC_REAL_END(data_access, 0x300, 0x80)
TRAMP_REAL_BEGIN(tramp_real_data_access) TRAMP_REAL_BEGIN(tramp_real_data_access)
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x300, 0 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x300, 0
/* /*
* DAR/DSISR must be read before setting MSR[RI], because * DAR/DSISR must be read before setting MSR[RI], because
* a d-side MCE will clobber those registers so is not * a d-side MCE will clobber those registers so is not
...@@ -1280,9 +1280,9 @@ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x300, 0 ...@@ -1280,9 +1280,9 @@ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x300, 0
EXCEPTION_PROLOG_2_REAL data_access_common, EXC_STD, 1 EXCEPTION_PROLOG_2_REAL data_access_common, EXC_STD, 1
EXC_VIRT_BEGIN(data_access, 0x4300, 0x80) EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
SET_SCRATCH0(r13) /* save r13 */ SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXGEN EXCEPTION_PROLOG_0 PACA_EXGEN
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x300, 0 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x300, 0
mfspr r10,SPRN_DAR mfspr r10,SPRN_DAR
mfspr r11,SPRN_DSISR mfspr r11,SPRN_DSISR
std r10,PACA_EXGEN+EX_DAR(r13) std r10,PACA_EXGEN+EX_DAR(r13)
...@@ -1315,24 +1315,24 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) ...@@ -1315,24 +1315,24 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
SET_SCRATCH0(r13) /* save r13 */ SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXSLB EXCEPTION_PROLOG_0 PACA_EXSLB
b tramp_real_data_access_slb b tramp_real_data_access_slb
EXC_REAL_END(data_access_slb, 0x380, 0x80) EXC_REAL_END(data_access_slb, 0x380, 0x80)
TRAMP_REAL_BEGIN(tramp_real_data_access_slb) TRAMP_REAL_BEGIN(tramp_real_data_access_slb)
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 1, 0x380, 0 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 1, 0x380, 0
mfspr r10,SPRN_DAR mfspr r10,SPRN_DAR
std r10,PACA_EXSLB+EX_DAR(r13) std r10,PACA_EXSLB+EX_DAR(r13)
EXCEPTION_PROLOG_2_REAL data_access_slb_common, EXC_STD, 1 EXCEPTION_PROLOG_2_REAL data_access_slb_common, EXC_STD, 1
EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
SET_SCRATCH0(r13) /* save r13 */ SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXSLB EXCEPTION_PROLOG_0 PACA_EXSLB
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 0, 0x380, 0 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 0, 0x380, 0
mfspr r10,SPRN_DAR mfspr r10,SPRN_DAR
std r10,PACA_EXSLB+EX_DAR(r13) std r10,PACA_EXSLB+EX_DAR(r13)
EXCEPTION_PROLOG_2_VIRT data_access_slb_common, EXC_STD EXCEPTION_PROLOG_2_VIRT data_access_slb_common, EXC_STD
EXC_VIRT_END(data_access_slb, 0x4380, 0x80) EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
...@@ -1415,25 +1415,25 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) ...@@ -1415,25 +1415,25 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
SET_SCRATCH0(r13) /* save r13 */ SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXGEN EXCEPTION_PROLOG_0 PACA_EXGEN
BEGIN_FTR_SECTION BEGIN_FTR_SECTION
EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, IRQS_DISABLED EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, IRQS_DISABLED
EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_HV, 1 EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_HV, 1
FTR_SECTION_ELSE FTR_SECTION_ELSE
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, IRQS_DISABLED EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, IRQS_DISABLED
EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_STD, 1 EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_STD, 1
ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
EXC_REAL_END(hardware_interrupt, 0x500, 0x100) EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
SET_SCRATCH0(r13) /* save r13 */ SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXGEN EXCEPTION_PROLOG_0 PACA_EXGEN
BEGIN_FTR_SECTION BEGIN_FTR_SECTION
EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, IRQS_DISABLED EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, IRQS_DISABLED
EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_HV EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_HV
FTR_SECTION_ELSE FTR_SECTION_ELSE
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, IRQS_DISABLED EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, IRQS_DISABLED
EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_STD EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_STD
ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
TRAMP_KVM(PACA_EXGEN, 0x500) TRAMP_KVM(PACA_EXGEN, 0x500)
...@@ -1442,25 +1442,25 @@ EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) ...@@ -1442,25 +1442,25 @@ EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
EXC_REAL_BEGIN(alignment, 0x600, 0x100) EXC_REAL_BEGIN(alignment, 0x600, 0x100)
SET_SCRATCH0(r13) /* save r13 */ SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXGEN EXCEPTION_PROLOG_0 PACA_EXGEN
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x600, 0 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x600, 0
mfspr r10,SPRN_DAR mfspr r10,SPRN_DAR
mfspr r11,SPRN_DSISR mfspr r11,SPRN_DSISR
std r10,PACA_EXGEN+EX_DAR(r13) std r10,PACA_EXGEN+EX_DAR(r13)
stw r11,PACA_EXGEN+EX_DSISR(r13) stw r11,PACA_EXGEN+EX_DSISR(r13)
EXCEPTION_PROLOG_2_REAL alignment_common, EXC_STD, 1 EXCEPTION_PROLOG_2_REAL alignment_common, EXC_STD, 1
EXC_REAL_END(alignment, 0x600, 0x100) EXC_REAL_END(alignment, 0x600, 0x100)
EXC_VIRT_BEGIN(alignment, 0x4600, 0x100) EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
SET_SCRATCH0(r13) /* save r13 */ SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0 PACA_EXGEN EXCEPTION_PROLOG_0 PACA_EXGEN
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x600, 0 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x600, 0
mfspr r10,SPRN_DAR mfspr r10,SPRN_DAR
mfspr r11,SPRN_DSISR mfspr r11,SPRN_DSISR
std r10,PACA_EXGEN+EX_DAR(r13) std r10,PACA_EXGEN+EX_DAR(r13)
stw r11,PACA_EXGEN+EX_DSISR(r13) stw r11,PACA_EXGEN+EX_DSISR(r13)
EXCEPTION_PROLOG_2_VIRT alignment_common, EXC_STD EXCEPTION_PROLOG_2_VIRT alignment_common, EXC_STD
EXC_VIRT_END(alignment, 0x4600, 0x100) EXC_VIRT_END(alignment, 0x4600, 0x100)
TRAMP_KVM(PACA_EXGEN, 0x600) TRAMP_KVM(PACA_EXGEN, 0x600)
......
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