Commit c0e6f5bf authored by Jerome Brunet's avatar Jerome Brunet Committed by Neil Armstrong

clk: meson: gxbb: claim clock controller input clock from DT

Instead of relying on a fixed name for the xtal clock, claim the
controller input clock trough DT.
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Reviewed-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190116175435.4990-2-jbrunet@baylibre.com
parent 74e1f252
...@@ -16,6 +16,8 @@ ...@@ -16,6 +16,8 @@
#include "gxbb.h" #include "gxbb.h"
#include "clk-regmap.h" #include "clk-regmap.h"
#define IN_PREFIX "ee-in-"
static DEFINE_SPINLOCK(meson_clk_lock); static DEFINE_SPINLOCK(meson_clk_lock);
static const struct pll_params_table gxbb_gp0_pll_params_table[] = { static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
...@@ -118,7 +120,7 @@ static struct clk_regmap gxbb_fixed_pll_dco = { ...@@ -118,7 +120,7 @@ static struct clk_regmap gxbb_fixed_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "fixed_pll_dco", .name = "fixed_pll_dco",
.ops = &meson_clk_pll_ro_ops, .ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ "xtal" }, .parent_names = (const char *[]){ IN_PREFIX "xtal" },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -148,7 +150,7 @@ static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = { ...@@ -148,7 +150,7 @@ static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_pll_pre_mult", .name = "hdmi_pll_pre_mult",
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
.parent_names = (const char *[]){ "xtal" }, .parent_names = (const char *[]){ IN_PREFIX "xtal" },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -241,7 +243,7 @@ static struct clk_regmap gxl_hdmi_pll_dco = { ...@@ -241,7 +243,7 @@ static struct clk_regmap gxl_hdmi_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "hdmi_pll_dco", .name = "hdmi_pll_dco",
.ops = &meson_clk_pll_ro_ops, .ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ "xtal" }, .parent_names = (const char *[]){ IN_PREFIX "xtal" },
.num_parents = 1, .num_parents = 1,
/* /*
* Display directly handle hdmi pll registers ATM, we need * Display directly handle hdmi pll registers ATM, we need
...@@ -378,7 +380,7 @@ static struct clk_regmap gxbb_sys_pll_dco = { ...@@ -378,7 +380,7 @@ static struct clk_regmap gxbb_sys_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "sys_pll_dco", .name = "sys_pll_dco",
.ops = &meson_clk_pll_ro_ops, .ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ "xtal" }, .parent_names = (const char *[]){ IN_PREFIX "xtal" },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -439,7 +441,7 @@ static struct clk_regmap gxbb_gp0_pll_dco = { ...@@ -439,7 +441,7 @@ static struct clk_regmap gxbb_gp0_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gp0_pll_dco", .name = "gp0_pll_dco",
.ops = &meson_clk_pll_ops, .ops = &meson_clk_pll_ops,
.parent_names = (const char *[]){ "xtal" }, .parent_names = (const char *[]){ IN_PREFIX "xtal" },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -491,7 +493,7 @@ static struct clk_regmap gxl_gp0_pll_dco = { ...@@ -491,7 +493,7 @@ static struct clk_regmap gxl_gp0_pll_dco = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gp0_pll_dco", .name = "gp0_pll_dco",
.ops = &meson_clk_pll_ops, .ops = &meson_clk_pll_ops,
.parent_names = (const char *[]){ "xtal" }, .parent_names = (const char *[]){ IN_PREFIX "xtal" },
.num_parents = 1, .num_parents = 1,
}, },
}; };
...@@ -789,7 +791,7 @@ static struct clk_regmap gxbb_mpll2 = { ...@@ -789,7 +791,7 @@ static struct clk_regmap gxbb_mpll2 = {
static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
static const char * const clk81_parent_names[] = { static const char * const clk81_parent_names[] = {
"xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
"fclk_div3", "fclk_div5" "fclk_div3", "fclk_div5"
}; };
...@@ -852,7 +854,7 @@ static struct clk_regmap gxbb_sar_adc_clk_sel = { ...@@ -852,7 +854,7 @@ static struct clk_regmap gxbb_sar_adc_clk_sel = {
.name = "sar_adc_clk_sel", .name = "sar_adc_clk_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
/* NOTE: The datasheet doesn't list the parents for bit 10 */ /* NOTE: The datasheet doesn't list the parents for bit 10 */
.parent_names = (const char *[]){ "xtal", "clk81", }, .parent_names = (const char *[]){ IN_PREFIX "xtal", "clk81", },
.num_parents = 2, .num_parents = 2,
}, },
}; };
...@@ -891,7 +893,7 @@ static struct clk_regmap gxbb_sar_adc_clk = { ...@@ -891,7 +893,7 @@ static struct clk_regmap gxbb_sar_adc_clk = {
*/ */
static const char * const gxbb_mali_0_1_parent_names[] = { static const char * const gxbb_mali_0_1_parent_names[] = {
"xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7", IN_PREFIX "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
"fclk_div4", "fclk_div3", "fclk_div5" "fclk_div4", "fclk_div3", "fclk_div5"
}; };
...@@ -1153,7 +1155,7 @@ static struct clk_regmap gxbb_32k_clk = { ...@@ -1153,7 +1155,7 @@ static struct clk_regmap gxbb_32k_clk = {
}; };
static const char * const gxbb_32k_clk_parent_names[] = { static const char * const gxbb_32k_clk_parent_names[] = {
"xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5" IN_PREFIX "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
}; };
static struct clk_regmap gxbb_32k_clk_sel = { static struct clk_regmap gxbb_32k_clk_sel = {
...@@ -1172,7 +1174,7 @@ static struct clk_regmap gxbb_32k_clk_sel = { ...@@ -1172,7 +1174,7 @@ static struct clk_regmap gxbb_32k_clk_sel = {
}; };
static const char * const gxbb_sd_emmc_clk0_parent_names[] = { static const char * const gxbb_sd_emmc_clk0_parent_names[] = {
"xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7", IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
/* /*
* Following these parent clocks, we should also have had mpll2, mpll3 * Following these parent clocks, we should also have had mpll2, mpll3
...@@ -2138,7 +2140,7 @@ static struct clk_regmap gxbb_hdmi_tx = { ...@@ -2138,7 +2140,7 @@ static struct clk_regmap gxbb_hdmi_tx = {
/* HDMI Clocks */ /* HDMI Clocks */
static const char * const gxbb_hdmi_parent_names[] = { static const char * const gxbb_hdmi_parent_names[] = {
"xtal", "fclk_div4", "fclk_div3", "fclk_div5" IN_PREFIX "xtal", "fclk_div4", "fclk_div3", "fclk_div5"
}; };
static struct clk_regmap gxbb_hdmi_sel = { static struct clk_regmap gxbb_hdmi_sel = {
...@@ -2285,7 +2287,7 @@ static struct clk_regmap gxbb_vdec_hevc = { ...@@ -2285,7 +2287,7 @@ static struct clk_regmap gxbb_vdec_hevc = {
static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8, static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
9, 10, 11, 13, 14, }; 9, 10, 11, 13, 14, };
static const char * const gen_clk_parent_names[] = { static const char * const gen_clk_parent_names[] = {
"xtal", "vdec_1", "vdec_hevc", "mpll0", "mpll1", "mpll2", IN_PREFIX "xtal", "vdec_1", "vdec_hevc", "mpll0", "mpll1", "mpll2",
"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll", "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
}; };
...@@ -3085,6 +3087,7 @@ static const struct of_device_id clkc_match_table[] = { ...@@ -3085,6 +3087,7 @@ static const struct of_device_id clkc_match_table[] = {
static int gxbb_clkc_probe(struct platform_device *pdev) static int gxbb_clkc_probe(struct platform_device *pdev)
{ {
const struct clkc_data *clkc_data; const struct clkc_data *clkc_data;
struct clk_hw *input;
struct regmap *map; struct regmap *map;
int ret, i; int ret, i;
struct device *dev = &pdev->dev; struct device *dev = &pdev->dev;
...@@ -3100,6 +3103,14 @@ static int gxbb_clkc_probe(struct platform_device *pdev) ...@@ -3100,6 +3103,14 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
return PTR_ERR(map); return PTR_ERR(map);
} }
input = meson_clk_hw_register_input(dev, "xtal", IN_PREFIX "xtal", 0);
if (IS_ERR(input)) {
ret = PTR_ERR(input);
if (ret != -EPROBE_DEFER)
dev_err(dev, "failed to get input clock");
return ret;
}
/* Populate regmap for the common regmap backed clocks */ /* Populate regmap for the common regmap backed clocks */
for (i = 0; i < ARRAY_SIZE(gx_clk_regmaps); i++) for (i = 0; i < ARRAY_SIZE(gx_clk_regmaps); i++)
gx_clk_regmaps[i]->map = map; gx_clk_regmaps[i]->map = map;
......
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