Commit c20ff3e0 authored by Stefan Mätje's avatar Stefan Mätje Committed by Marc Kleine-Budde

can: esd_402_pci: Add support for one-shot mode

This patch adds support for one-shot mode. In this mode there happens no
automatic retransmission in the case of an arbitration lost error or on
any bus error.
Signed-off-by: default avatarStefan Mätje <stefan.maetje@esd.eu>
Link: https://lore.kernel.org/all/20240717214409.3934333-3-stefan.maetje@esd.euSigned-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
parent 3e6cb3f2
...@@ -369,12 +369,13 @@ static int pci402_init_cores(struct pci_dev *pdev) ...@@ -369,12 +369,13 @@ static int pci402_init_cores(struct pci_dev *pdev)
SET_NETDEV_DEV(netdev, &pdev->dev); SET_NETDEV_DEV(netdev, &pdev->dev);
priv = netdev_priv(netdev); priv = netdev_priv(netdev);
priv->can.clock.freq = card->ov.core_frequency;
priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_LISTENONLY |
CAN_CTRLMODE_BERR_REPORTING | CAN_CTRLMODE_BERR_REPORTING |
CAN_CTRLMODE_CC_LEN8_DLC; CAN_CTRLMODE_CC_LEN8_DLC;
if (card->ov.features & ACC_OV_REG_FEAT_MASK_DAR)
priv->can.clock.freq = card->ov.core_frequency; priv->can.ctrlmode_supported |= CAN_CTRLMODE_ONE_SHOT;
if (card->ov.features & ACC_OV_REG_FEAT_MASK_CANFD) if (card->ov.features & ACC_OV_REG_FEAT_MASK_CANFD)
priv->can.bittiming_const = &pci402_bittiming_const_canfd; priv->can.bittiming_const = &pci402_bittiming_const_canfd;
else else
......
...@@ -17,6 +17,9 @@ ...@@ -17,6 +17,9 @@
/* esdACC DLC register layout */ /* esdACC DLC register layout */
#define ACC_DLC_DLC_MASK GENMASK(3, 0) #define ACC_DLC_DLC_MASK GENMASK(3, 0)
#define ACC_DLC_RTR_FLAG BIT(4) #define ACC_DLC_RTR_FLAG BIT(4)
#define ACC_DLC_SSTX_FLAG BIT(24) /* Single Shot TX */
/* esdACC DLC in struct acc_bmmsg_rxtxdone::acc_dlc.len only! */
#define ACC_DLC_TXD_FLAG BIT(5) #define ACC_DLC_TXD_FLAG BIT(5)
/* ecc value of esdACC equals SJA1000's ECC register */ /* ecc value of esdACC equals SJA1000's ECC register */
...@@ -59,7 +62,7 @@ static void acc_resetmode_leave(struct acc_core *core) ...@@ -59,7 +62,7 @@ static void acc_resetmode_leave(struct acc_core *core)
acc_resetmode_entered(core); acc_resetmode_entered(core);
} }
static void acc_txq_put(struct acc_core *core, u32 acc_id, u8 acc_dlc, static void acc_txq_put(struct acc_core *core, u32 acc_id, u32 acc_dlc,
const void *data) const void *data)
{ {
acc_write32_noswap(core, ACC_CORE_OF_TXFIFO_DATA_1, acc_write32_noswap(core, ACC_CORE_OF_TXFIFO_DATA_1,
...@@ -249,7 +252,7 @@ netdev_tx_t acc_start_xmit(struct sk_buff *skb, struct net_device *netdev) ...@@ -249,7 +252,7 @@ netdev_tx_t acc_start_xmit(struct sk_buff *skb, struct net_device *netdev)
u8 tx_fifo_head = core->tx_fifo_head; u8 tx_fifo_head = core->tx_fifo_head;
int fifo_usage; int fifo_usage;
u32 acc_id; u32 acc_id;
u8 acc_dlc; u32 acc_dlc;
if (can_dropped_invalid_skb(netdev, skb)) if (can_dropped_invalid_skb(netdev, skb))
return NETDEV_TX_OK; return NETDEV_TX_OK;
...@@ -274,6 +277,8 @@ netdev_tx_t acc_start_xmit(struct sk_buff *skb, struct net_device *netdev) ...@@ -274,6 +277,8 @@ netdev_tx_t acc_start_xmit(struct sk_buff *skb, struct net_device *netdev)
acc_dlc = can_get_cc_dlc(cf, priv->can.ctrlmode); acc_dlc = can_get_cc_dlc(cf, priv->can.ctrlmode);
if (cf->can_id & CAN_RTR_FLAG) if (cf->can_id & CAN_RTR_FLAG)
acc_dlc |= ACC_DLC_RTR_FLAG; acc_dlc |= ACC_DLC_RTR_FLAG;
if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
acc_dlc |= ACC_DLC_SSTX_FLAG;
if (cf->can_id & CAN_EFF_FLAG) { if (cf->can_id & CAN_EFF_FLAG) {
acc_id = cf->can_id & CAN_EFF_MASK; acc_id = cf->can_id & CAN_EFF_MASK;
......
...@@ -35,6 +35,7 @@ ...@@ -35,6 +35,7 @@
*/ */
#define ACC_OV_REG_FEAT_MASK_CANFD BIT(27 - 16) #define ACC_OV_REG_FEAT_MASK_CANFD BIT(27 - 16)
#define ACC_OV_REG_FEAT_MASK_NEW_PSC BIT(28 - 16) #define ACC_OV_REG_FEAT_MASK_NEW_PSC BIT(28 - 16)
#define ACC_OV_REG_FEAT_MASK_DAR BIT(30 - 16)
#define ACC_OV_REG_MODE_MASK_ENDIAN_LITTLE BIT(0) #define ACC_OV_REG_MODE_MASK_ENDIAN_LITTLE BIT(0)
#define ACC_OV_REG_MODE_MASK_BM_ENABLE BIT(1) #define ACC_OV_REG_MODE_MASK_BM_ENABLE BIT(1)
......
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