Commit c2a75586 authored by Dave Airlie's avatar Dave Airlie

Merge tag 'drm-intel-fixes-2015-10-16' of git://anongit.freedesktop.org/drm-intel into drm-fixes

The revert dance could use some explanation: we had stuff fixed in
-next, and initially backported one commit to v4.3. Now, turns out we
need more fixes, and we could cherry-pick them all without conflicts if
we reverted the backported one first. So did that to not have to edit
and backport them all.

* tag 'drm-intel-fixes-2015-10-16' of git://anongit.freedesktop.org/drm-intel:
  drm/i915: Add primary plane to mask if it's visible
  drm/i915: Move sprite/cursor plane disable to intel_sanitize_crtc()
  drm/i915: Assign hwmode after encoder state readout
  Revert "drm/i915: Add primary plane to mask if it's visible"
  drm/i915: Deny wrapping an userptr into a framebuffer
  drm/i915: Enable DPLL VGA mode before P1/P2 divider write
  drm/i915: Restore lost DPLL register write on gen2-4
  drm/i915: Flush pipecontrol post-sync writes
  drm/i915: Fix kerneldoc for i915_gem_shrink_all
parents 37363bc0 18e9345b
...@@ -143,7 +143,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv, ...@@ -143,7 +143,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv,
} }
/** /**
* i915_gem_shrink - Shrink buffer object caches completely * i915_gem_shrink_all - Shrink buffer object caches completely
* @dev_priv: i915 device * @dev_priv: i915 device
* *
* This is a simple wraper around i915_gem_shrink() to aggressively shrink all * This is a simple wraper around i915_gem_shrink() to aggressively shrink all
......
...@@ -804,7 +804,10 @@ static const struct drm_i915_gem_object_ops i915_gem_userptr_ops = { ...@@ -804,7 +804,10 @@ static const struct drm_i915_gem_object_ops i915_gem_userptr_ops = {
* Also note, that the object created here is not currently a "first class" * Also note, that the object created here is not currently a "first class"
* object, in that several ioctls are banned. These are the CPU access * object, in that several ioctls are banned. These are the CPU access
* ioctls: mmap(), pwrite and pread. In practice, you are expected to use * ioctls: mmap(), pwrite and pread. In practice, you are expected to use
* direct access via your pointer rather than use those ioctls. * direct access via your pointer rather than use those ioctls. Another
* restriction is that we do not allow userptr surfaces to be pinned to the
* hardware and so we reject any attempt to create a framebuffer out of a
* userptr.
* *
* If you think this is a good interface to use to pass GPU memory between * If you think this is a good interface to use to pass GPU memory between
* drivers, please use dma-buf instead. In fact, wherever possible use * drivers, please use dma-buf instead. In fact, wherever possible use
......
...@@ -1724,6 +1724,15 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) ...@@ -1724,6 +1724,15 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
} }
/*
* Apparently we need to have VGA mode enabled prior to changing
* the P1/P2 dividers. Otherwise the DPLL will keep using the old
* dividers, even though the register value does change.
*/
I915_WRITE(reg, 0);
I915_WRITE(reg, dpll);
/* Wait for the clocks to stabilize. */ /* Wait for the clocks to stabilize. */
POSTING_READ(reg); POSTING_READ(reg);
udelay(150); udelay(150);
...@@ -14107,6 +14116,11 @@ static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, ...@@ -14107,6 +14116,11 @@ static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
struct drm_i915_gem_object *obj = intel_fb->obj; struct drm_i915_gem_object *obj = intel_fb->obj;
if (obj->userptr.mm) {
DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
return -EINVAL;
}
return drm_gem_handle_create(file, &obj->base, handle); return drm_gem_handle_create(file, &obj->base, handle);
} }
...@@ -14897,9 +14911,19 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) ...@@ -14897,9 +14911,19 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
/* restore vblank interrupts to correct state */ /* restore vblank interrupts to correct state */
drm_crtc_vblank_reset(&crtc->base); drm_crtc_vblank_reset(&crtc->base);
if (crtc->active) { if (crtc->active) {
struct intel_plane *plane;
drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
update_scanline_offset(crtc); update_scanline_offset(crtc);
drm_crtc_vblank_on(&crtc->base); drm_crtc_vblank_on(&crtc->base);
/* Disable everything but the primary plane */
for_each_intel_plane_on_crtc(dev, crtc, plane) {
if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
continue;
plane->disable_plane(&plane->base, &crtc->base);
}
} }
/* We need to sanitize the plane -> pipe mapping first because this will /* We need to sanitize the plane -> pipe mapping first because this will
...@@ -15067,38 +15091,25 @@ void i915_redisable_vga(struct drm_device *dev) ...@@ -15067,38 +15091,25 @@ void i915_redisable_vga(struct drm_device *dev)
i915_redisable_vga_power_on(dev); i915_redisable_vga_power_on(dev);
} }
static bool primary_get_hw_state(struct intel_crtc *crtc) static bool primary_get_hw_state(struct intel_plane *plane)
{ {
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE); return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
} }
static void readout_plane_state(struct intel_crtc *crtc, /* FIXME read out full plane state for all planes */
struct intel_crtc_state *crtc_state) static void readout_plane_state(struct intel_crtc *crtc)
{ {
struct intel_plane *p; struct drm_plane *primary = crtc->base.primary;
struct intel_plane_state *plane_state; struct intel_plane_state *plane_state =
bool active = crtc_state->base.active; to_intel_plane_state(primary->state);
for_each_intel_plane(crtc->base.dev, p) {
if (crtc->pipe != p->pipe)
continue;
plane_state = to_intel_plane_state(p->base.state);
if (p->base.type == DRM_PLANE_TYPE_PRIMARY) { plane_state->visible =
plane_state->visible = primary_get_hw_state(crtc); primary_get_hw_state(to_intel_plane(primary));
if (plane_state->visible)
crtc->base.state->plane_mask |=
1 << drm_plane_index(&p->base);
} else {
if (active)
p->disable_plane(&p->base, &crtc->base);
plane_state->visible = false; if (plane_state->visible)
} crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
}
} }
static void intel_modeset_readout_hw_state(struct drm_device *dev) static void intel_modeset_readout_hw_state(struct drm_device *dev)
...@@ -15121,34 +15132,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) ...@@ -15121,34 +15132,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
crtc->base.state->active = crtc->active; crtc->base.state->active = crtc->active;
crtc->base.enabled = crtc->active; crtc->base.enabled = crtc->active;
memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); readout_plane_state(crtc);
if (crtc->base.state->active) {
intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
/*
* The initial mode needs to be set in order to keep
* the atomic core happy. It wants a valid mode if the
* crtc's enabled, so we do the above call.
*
* At this point some state updated by the connectors
* in their ->detect() callback has not run yet, so
* no recalculation can be done yet.
*
* Even if we could do a recalculation and modeset
* right now it would cause a double modeset if
* fbdev or userspace chooses a different initial mode.
*
* If that happens, someone indicated they wanted a
* mode change, which means it's safe to do a full
* recalculation.
*/
crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
}
crtc->base.hwmode = crtc->config->base.adjusted_mode;
readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
crtc->base.base.id, crtc->base.base.id,
...@@ -15207,6 +15191,36 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) ...@@ -15207,6 +15191,36 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
connector->base.name, connector->base.name,
connector->base.encoder ? "enabled" : "disabled"); connector->base.encoder ? "enabled" : "disabled");
} }
for_each_intel_crtc(dev, crtc) {
crtc->base.hwmode = crtc->config->base.adjusted_mode;
memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
if (crtc->base.state->active) {
intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
/*
* The initial mode needs to be set in order to keep
* the atomic core happy. It wants a valid mode if the
* crtc's enabled, so we do the above call.
*
* At this point some state updated by the connectors
* in their ->detect() callback has not run yet, so
* no recalculation can be done yet.
*
* Even if we could do a recalculation and modeset
* right now it would cause a double modeset if
* fbdev or userspace chooses a different initial mode.
*
* If that happens, someone indicated they wanted a
* mode change, which means it's safe to do a full
* recalculation.
*/
crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
}
}
} }
/* Scan out the current hw modeset state, /* Scan out the current hw modeset state,
......
...@@ -1659,6 +1659,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request, ...@@ -1659,6 +1659,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
if (flush_domains) { if (flush_domains) {
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
flags |= PIPE_CONTROL_FLUSH_ENABLE;
} }
if (invalidate_domains) { if (invalidate_domains) {
......
...@@ -347,6 +347,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req, ...@@ -347,6 +347,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
if (flush_domains) { if (flush_domains) {
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
flags |= PIPE_CONTROL_FLUSH_ENABLE;
} }
if (invalidate_domains) { if (invalidate_domains) {
flags |= PIPE_CONTROL_TLB_INVALIDATE; flags |= PIPE_CONTROL_TLB_INVALIDATE;
...@@ -418,6 +419,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req, ...@@ -418,6 +419,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
if (flush_domains) { if (flush_domains) {
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
flags |= PIPE_CONTROL_FLUSH_ENABLE;
} }
if (invalidate_domains) { if (invalidate_domains) {
flags |= PIPE_CONTROL_TLB_INVALIDATE; flags |= PIPE_CONTROL_TLB_INVALIDATE;
......
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