Commit c2ad2844 authored by Dinh Nguyen's avatar Dinh Nguyen Committed by Olof Johansson

arm: socfpga: Add new device tree source for actual socfpga HW

Up to this point, support for socfpga has only been on a virtual
platform. Now that actual hardware is available, we add the appropriate
device tree source files.
Signed-off-by: default avatarDinh Nguyen <dinguyen@altera.com>
Tested-by: default avatarPavel Machek <pavel@denx.de>
Reviewed-by: default avatarPavel Machek <pavel@denx.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 88b62b91
...@@ -25,6 +25,10 @@ aliases { ...@@ -25,6 +25,10 @@ aliases {
ethernet0 = &gmac0; ethernet0 = &gmac0;
serial0 = &uart0; serial0 = &uart0;
serial1 = &uart1; serial1 = &uart1;
timer0 = &timer0;
timer1 = &timer1;
timer2 = &timer2;
timer3 = &timer3;
}; };
cpus { cpus {
...@@ -98,47 +102,41 @@ timer@fffec600 { ...@@ -98,47 +102,41 @@ timer@fffec600 {
interrupts = <1 13 0xf04>; interrupts = <1 13 0xf04>;
}; };
timer0: timer@ffc08000 { timer0: timer0@ffc08000 {
compatible = "snps,dw-apb-timer-sp"; compatible = "snps,dw-apb-timer-sp";
interrupts = <0 167 4>; interrupts = <0 167 4>;
clock-frequency = <200000000>;
reg = <0xffc08000 0x1000>; reg = <0xffc08000 0x1000>;
}; };
timer1: timer@ffc09000 { timer1: timer1@ffc09000 {
compatible = "snps,dw-apb-timer-sp"; compatible = "snps,dw-apb-timer-sp";
interrupts = <0 168 4>; interrupts = <0 168 4>;
clock-frequency = <200000000>;
reg = <0xffc09000 0x1000>; reg = <0xffc09000 0x1000>;
}; };
timer2: timer@ffd00000 { timer2: timer2@ffd00000 {
compatible = "snps,dw-apb-timer-osc"; compatible = "snps,dw-apb-timer-osc";
interrupts = <0 169 4>; interrupts = <0 169 4>;
clock-frequency = <200000000>;
reg = <0xffd00000 0x1000>; reg = <0xffd00000 0x1000>;
}; };
timer3: timer@ffd01000 { timer3: timer3@ffd01000 {
compatible = "snps,dw-apb-timer-osc"; compatible = "snps,dw-apb-timer-osc";
interrupts = <0 170 4>; interrupts = <0 170 4>;
clock-frequency = <200000000>;
reg = <0xffd01000 0x1000>; reg = <0xffd01000 0x1000>;
}; };
uart0: uart@ffc02000 { uart0: serial0@ffc02000 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0xffc02000 0x1000>; reg = <0xffc02000 0x1000>;
clock-frequency = <7372800>;
interrupts = <0 162 4>; interrupts = <0 162 4>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
}; };
uart1: uart@ffc03000 { uart1: serial1@ffc03000 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0xffc03000 0x1000>; reg = <0xffc03000 0x1000>;
clock-frequency = <7372800>;
interrupts = <0 163 4>; interrupts = <0 163 4>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
......
...@@ -20,7 +20,7 @@ ...@@ -20,7 +20,7 @@
/ { / {
model = "Altera SOCFPGA Cyclone V"; model = "Altera SOCFPGA Cyclone V";
compatible = "altr,socfpga-cyclone5"; compatible = "altr,socfpga-cyclone5", "altr,socfpga";
chosen { chosen {
bootargs = "console=ttyS0,57600"; bootargs = "console=ttyS0,57600";
...@@ -29,6 +29,32 @@ chosen { ...@@ -29,6 +29,32 @@ chosen {
memory { memory {
name = "memory"; name = "memory";
device_type = "memory"; device_type = "memory";
reg = <0x0 0x10000000>; /* 256MB */ reg = <0x0 0x40000000>; /* 1GB */
};
soc {
timer0@ffc08000 {
clock-frequency = <100000000>;
};
timer1@ffc09000 {
clock-frequency = <100000000>;
};
timer2@ffd00000 {
clock-frequency = <25000000>;
};
timer3@ffd01000 {
clock-frequency = <25000000>;
};
serial0@ffc02000 {
clock-frequency = <100000000>;
};
serial1@ffc03000 {
clock-frequency = <100000000>;
};
}; };
}; };
/*
* Copyright (C) 2013 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/dts-v1/;
/include/ "socfpga.dtsi"
/ {
model = "Altera SOCFPGA VT";
compatible = "altr,socfpga-vt", "altr,socfpga";
chosen {
bootargs = "console=ttyS0,57600";
};
memory {
name = "memory";
device_type = "memory";
reg = <0x0 0x40000000>; /* 1 GB */
};
soc {
timer0@ffc08000 {
clock-frequency = <7000000>;
};
timer1@ffc09000 {
clock-frequency = <7000000>;
};
timer2@ffd00000 {
clock-frequency = <7000000>;
};
timer3@ffd01000 {
clock-frequency = <7000000>;
};
serial0@ffc02000 {
clock-frequency = <7372800>;
};
serial1@ffc03000 {
clock-frequency = <7372800>;
};
};
};
...@@ -98,7 +98,6 @@ static void __init socfpga_cyclone5_init(void) ...@@ -98,7 +98,6 @@ static void __init socfpga_cyclone5_init(void)
static const char *altera_dt_match[] = { static const char *altera_dt_match[] = {
"altr,socfpga", "altr,socfpga",
"altr,socfpga-cyclone5",
NULL NULL
}; };
......
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