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Commit c2d31305 authored by Russell King's avatar Russell King
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[ARM] Clean up Integrator interrupt number definitions. 

This allows us to expand the interrupt numbers on the primary
interrupt controller.
parent 112fa2ce
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Showing with 39 additions and 195 deletions
arch/arm/mach-integrator/integrator_ap.c
View file @ c2d31305
......@@ -92,7 +92,7 @@ static void __init ap_map_io(void)
iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
}
#define ALLPCI ( (1 << IRQ_PCIINT0) | (1 << IRQ_PCIINT1) | (1 << IRQ_PCIINT2) | (1 << IRQ_PCIINT3) )
#define INTEGRATOR_SC_VALID_INT 0x003fffff
static void sc_mask_irq(unsigned int irq)
{
......@@ -152,7 +152,7 @@ static int __init ap_init(void)
lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
lmdev->resource.flags = IORESOURCE_MEM;
lmdev->irq = IRQ_EXPINT0 + i;
lmdev->irq = IRQ_AP_EXPINT0 + i;
lmdev->id = i;
lm_device_register(lmdev);
......
arch/arm/mach-integrator/pci.c
View file @ c2d31305
......@@ -96,7 +96,7 @@ static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp)
}
static int irq_tab[4] __initdata = {
IRQ_PCIINT0, IRQ_PCIINT1, IRQ_PCIINT2, IRQ_PCIINT3
IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
};
/*
......
arch/arm/mach-integrator/pci_v3.c
View file @ c2d31305
......@@ -575,7 +575,7 @@ void __init pci_v3_preinit(void)
/*
* Grab the PCI error interrupt.
*/
ret = request_irq(IRQ_V3INT, v3_irq, 0, "V3", NULL);
ret = request_irq(IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
if (ret)
printk(KERN_ERR "PCI: unable to grab PCI error "
"interrupt: %d\n", ret);
......@@ -596,7 +596,7 @@ void __init pci_v3_postinit(void)
v3_writeb(V3_LB_IMASK, 0x68);
#if 0
ret = request_irq(IRQ_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL);
ret = request_irq(IRQ_AP_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL);
if (ret)
printk(KERN_ERR "PCI: unable to grab local bus timeout "
"interrupt: %d\n", ret);
......
include/asm-arm/arch-integrator/irqs.h
View file @ c2d31305
......@@ -19,116 +19,39 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/* Use the integrator definitions */
#include <asm/arch/platform.h>
/*
* IRQ interrupts definitions are the same the INT definitions
* held within platform.h
*/
#define IRQ_SOFTINT INT_SOFTINT
#define IRQ_UARTINT0 INT_UARTINT0
#define IRQ_UARTINT1 INT_UARTINT1
#define IRQ_KMIINT0 INT_KMIINT0
#define IRQ_KMIINT1 INT_KMIINT1
#define IRQ_TIMERINT0 INT_TIMERINT0
#define IRQ_TIMERINT1 INT_TIMERINT1
#define IRQ_TIMERINT2 INT_TIMERINT2
#define IRQ_RTCINT INT_RTCINT
#define IRQ_EXPINT0 INT_EXPINT0
#define IRQ_EXPINT1 INT_EXPINT1
#define IRQ_EXPINT2 INT_EXPINT2
#define IRQ_EXPINT3 INT_EXPINT3
#define IRQ_PCIINT0 INT_PCIINT0
#define IRQ_PCIINT1 INT_PCIINT1
#define IRQ_PCIINT2 INT_PCIINT2
#define IRQ_PCIINT3 INT_PCIINT3
#define IRQ_V3INT INT_V3INT
#define IRQ_CPINT0 INT_CPINT0
#define IRQ_CPINT1 INT_CPINT1
#define IRQ_LBUSTIMEOUT INT_LBUSTIMEOUT
#define IRQ_APCINT INT_APCINT
#define IRQMASK_SOFTINT INTMASK_SOFTINT
#define IRQMASK_UARTINT0 INTMASK_UARTINT0
#define IRQMASK_UARTINT1 INTMASK_UARTINT1
#define IRQMASK_KMIINT0 INTMASK_KMIINT0
#define IRQMASK_KMIINT1 INTMASK_KMIINT1
#define IRQMASK_TIMERINT0 INTMASK_TIMERINT0
#define IRQMASK_TIMERINT1 INTMASK_TIMERINT1
#define IRQMASK_TIMERINT2 INTMASK_TIMERINT2
#define IRQMASK_RTCINT INTMASK_RTCINT
#define IRQMASK_EXPINT0 INTMASK_EXPINT0
#define IRQMASK_EXPINT1 INTMASK_EXPINT1
#define IRQMASK_EXPINT2 INTMASK_EXPINT2
#define IRQMASK_EXPINT3 INTMASK_EXPINT3
#define IRQMASK_PCIINT0 INTMASK_PCIINT0
#define IRQMASK_PCIINT1 INTMASK_PCIINT1
#define IRQMASK_PCIINT2 INTMASK_PCIINT2
#define IRQMASK_PCIINT3 INTMASK_PCIINT3
#define IRQMASK_V3INT INTMASK_V3INT
#define IRQMASK_CPINT0 INTMASK_CPINT0
#define IRQMASK_CPINT1 INTMASK_CPINT1
#define IRQMASK_LBUSTIMEOUT INTMASK_LBUSTIMEOUT
#define IRQMASK_APCINT INTMASK_APCINT
/*
* FIQ interrupts definitions are the same the INT definitions.
* Interrupt numbers
*/
#define FIQ_SOFTINT INT_SOFTINT
#define FIQ_UARTINT0 INT_UARTINT0
#define FIQ_UARTINT1 INT_UARTINT1
#define FIQ_KMIINT0 INT_KMIINT0
#define FIQ_KMIINT1 INT_KMIINT1
#define FIQ_TIMERINT0 INT_TIMERINT0
#define FIQ_TIMERINT1 INT_TIMERINT1
#define FIQ_TIMERINT2 INT_TIMERINT2
#define FIQ_RTCINT INT_RTCINT
#define FIQ_EXPINT0 INT_EXPINT0
#define FIQ_EXPINT1 INT_EXPINT1
#define FIQ_EXPINT2 INT_EXPINT2
#define FIQ_EXPINT3 INT_EXPINT3
#define FIQ_PCIINT0 INT_PCIINT0
#define FIQ_PCIINT1 INT_PCIINT1
#define FIQ_PCIINT2 INT_PCIINT2
#define FIQ_PCIINT3 INT_PCIINT3
#define FIQ_V3INT INT_V3INT
#define FIQ_CPINT0 INT_CPINT0
#define FIQ_CPINT1 INT_CPINT1
#define FIQ_LBUSTIMEOUT INT_LBUSTIMEOUT
#define FIQ_APCINT INT_APCINT
#define FIQMASK_SOFTINT INTMASK_SOFTINT
#define FIQMASK_UARTINT0 INTMASK_UARTINT0
#define FIQMASK_UARTINT1 INTMASK_UARTINT1
#define FIQMASK_KMIINT0 INTMASK_KMIINT0
#define FIQMASK_KMIINT1 INTMASK_KMIINT1
#define FIQMASK_TIMERINT0 INTMASK_TIMERINT0
#define FIQMASK_TIMERINT1 INTMASK_TIMERINT1
#define FIQMASK_TIMERINT2 INTMASK_TIMERINT2
#define FIQMASK_RTCINT INTMASK_RTCINT
#define FIQMASK_EXPINT0 INTMASK_EXPINT0
#define FIQMASK_EXPINT1 INTMASK_EXPINT1
#define FIQMASK_EXPINT2 INTMASK_EXPINT2
#define FIQMASK_EXPINT3 INTMASK_EXPINT3
#define FIQMASK_PCIINT0 INTMASK_PCIINT0
#define FIQMASK_PCIINT1 INTMASK_PCIINT1
#define FIQMASK_PCIINT2 INTMASK_PCIINT2
#define FIQMASK_PCIINT3 INTMASK_PCIINT3
#define FIQMASK_V3INT INTMASK_V3INT
#define FIQMASK_CPINT0 INTMASK_CPINT0
#define FIQMASK_CPINT1 INTMASK_CPINT1
#define FIQMASK_LBUSTIMEOUT INTMASK_LBUSTIMEOUT
#define FIQMASK_APCINT INTMASK_APCINT
/*
* Misc. interrupt definitions
*/
#define IRQ_KEYBDINT INT_KMIINT0
#define IRQ_MOUSEINT INT_KMIINT1
#define IRQMASK_KEYBDINT INTMASK_KMIINT0
#define IRQMASK_MOUSEINT INTMASK_KMIINT1
#define NR_IRQS (MAXIRQNUM + 1)
#define IRQ_PIC_START 0
#define IRQ_SOFTINT 0
#define IRQ_UARTINT0 1
#define IRQ_UARTINT1 2
#define IRQ_KMIINT0 3
#define IRQ_KMIINT1 4
#define IRQ_TIMERINT0 5
#define IRQ_TIMERINT1 6
#define IRQ_TIMERINT2 7
#define IRQ_RTCINT 8
#define IRQ_AP_EXPINT0 9
#define IRQ_AP_EXPINT1 10
#define IRQ_AP_EXPINT2 11
#define IRQ_AP_EXPINT3 12
#define IRQ_AP_PCIINT0 13
#define IRQ_AP_PCIINT1 14
#define IRQ_AP_PCIINT2 15
#define IRQ_AP_PCIINT3 16
#define IRQ_AP_V3INT 17
#define IRQ_AP_CPINT0 18
#define IRQ_AP_CPINT1 19
#define IRQ_AP_LBUSTIMEOUT 20
#define IRQ_AP_APCINT 21
#define IRQ_PIC_END 31
#define IRQ_CIC_START 32
#define IRQ_CM_SOFTINT 32
#define IRQ_CM_COMMRX 33
#define IRQ_CM_COMMTX 34
#define IRQ_CIC_END 34
#define NR_IRQS 47
include/asm-arm/arch-integrator/platform.h
View file @ c2d31305
......@@ -386,85 +386,6 @@
*
*/
/*
* As the interrupt bit definitions for FIQ/IRQ there is a common
* set of definitions prefixed INT/INTMASK. The FIQ/IRQ definitions
* have been left to maintain backwards compatible.
*
*/
/*
* Interrupt numbers
*
*/
#define INT_SOFTINT 0
#define INT_UARTINT0 1
#define INT_UARTINT1 2
#define INT_KMIINT0 3
#define INT_KMIINT1 4
#define INT_TIMERINT0 5
#define INT_TIMERINT1 6
#define INT_TIMERINT2 7
#define INT_RTCINT 8
#define INT_EXPINT0 9
#define INT_EXPINT1 10
#define INT_EXPINT2 11
#define INT_EXPINT3 12
#define INT_PCIINT0 13
#define INT_PCIINT1 14
#define INT_PCIINT2 15
#define INT_PCIINT3 16
#define INT_V3INT 17
#define INT_CPINT0 18
#define INT_CPINT1 19
#define INT_LBUSTIMEOUT 20
#define INT_APCINT 21
#define INT_CM_SOFTINT 24
#define INT_CM_COMMRX 25
#define INT_CM_COMMTX 26
/*
* Interrupt bit positions
*
*/
#define INTMASK_SOFTINT (1 << INT_SOFTINT)
#define INTMASK_UARTINT0 (1 << INT_UARTINT0)
#define INTMASK_UARTINT1 (1 << INT_UARTINT1)
#define INTMASK_KMIINT0 (1 << INT_KMIINT0)
#define INTMASK_KMIINT1 (1 << INT_KMIINT1)
#define INTMASK_TIMERINT0 (1 << INT_TIMERINT0)
#define INTMASK_TIMERINT1 (1 << INT_TIMERINT1)
#define INTMASK_TIMERINT2 (1 << INT_TIMERINT2)
#define INTMASK_RTCINT (1 << INT_RTCINT)
#define INTMASK_EXPINT0 (1 << INT_EXPINT0)
#define INTMASK_EXPINT1 (1 << INT_EXPINT1)
#define INTMASK_EXPINT2 (1 << INT_EXPINT2)
#define INTMASK_EXPINT3 (1 << INT_EXPINT3)
#define INTMASK_PCIINT0 (1 << INT_PCIINT0)
#define INTMASK_PCIINT1 (1 << INT_PCIINT1)
#define INTMASK_PCIINT2 (1 << INT_PCIINT2)
#define INTMASK_PCIINT3 (1 << INT_PCIINT3)
#define INTMASK_V3INT (1 << INT_V3INT)
#define INTMASK_CPINT0 (1 << INT_CPINT0)
#define INTMASK_CPINT1 (1 << INT_CPINT1)
#define INTMASK_LBUSTIMEOUT (1 << INT_LBUSTIMEOUT)
#define INTMASK_APCINT (1 << INT_APCINT)
#define INTMASK_CM_SOFTINT (1 << INT_CM_SOFTINT)
#define INTMASK_CM_COMMRX (1 << INT_CM_COMMRX)
#define INTMASK_CM_COMMTX (1 << INT_CM_COMMTX)
/*
* INTEGRATOR_CM_INT0 - Interrupt number of first CM interrupt
* INTEGRATOR_SC_VALID_INT - Mask of valid system controller interrupts
*
*/
#define INTEGRATOR_CM_INT0 INT_CM_SOFTINT
#define INTEGRATOR_SC_VALID_INT 0x003FFFFF
#define MAXIRQNUM 31
#define MAXFIQNUM 31
#define MAXSWINUM 31
/* ------------------------------------------------------------------------
* LED's - The header LED is not accessible via the uHAL API
* ------------------------------------------------------------------------
......
include/asm-arm/arch-integrator/time.h
View file @ c2d31305
......@@ -86,7 +86,7 @@ static unsigned long integrator_gettimeoffset(void)
/*
* Interrupt pending? If so, we've reloaded once already.
*/
if (status & IRQMASK_TIMERINT1)
if (status & (1 << IRQ_TIMERINT1))
ticks1 += TIMER_RELOAD;
/*
......
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