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Commit c2e1ff39 authored by David S. Miller's avatar David S. Miller
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux 

Pull in Linus's tree to get the commits that blew away
ARCH_USES_GETTIMEOFFSET but didn't update Sparc correctly, so
that I can apply Stephen Rothwell's fix for that mis-merge.
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 456d3d42 b48b2c3e
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Documentation/arm/SPEAr/overview.txt
View file @ c2e1ff39
......@@ -8,9 +8,8 @@ Introduction
weblink : http://www.st.com/spear
The ST Microelectronics SPEAr range of ARM9/CortexA9 System-on-Chip CPUs are
supported by the 'spear' platform of ARM Linux. Currently SPEAr300,
SPEAr310, SPEAr320 and SPEAr600 SOCs are supported. Support for the SPEAr13XX
series is in progress.
supported by the 'spear' platform of ARM Linux. Currently SPEAr1310,
SPEAr1340, SPEAr300, SPEAr310, SPEAr320 and SPEAr600 SOCs are supported.
Hierarchy in SPEAr is as follows:
......@@ -26,33 +25,36 @@ Introduction
- SPEAr600 (SOC)
- SPEAr600 Evaluation Board
- SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
- SPEAr1300 (SOC)
- SPEAr1310 (SOC)
- SPEAr1310 Evaluation Board
- SPEAr1340 (SOC)
- SPEAr1340 Evaluation Board
Configuration
-------------
A generic configuration is provided for each machine, and can be used as the
default by
make spear600_defconfig
make spear300_defconfig
make spear310_defconfig
make spear320_defconfig
make spear13xx_defconfig
make spear3xx_defconfig
make spear6xx_defconfig
Layout
------
The common files for multiple machine families (SPEAr3XX, SPEAr6XX and
SPEAr13XX) are located in the platform code contained in arch/arm/plat-spear
The common files for multiple machine families (SPEAr3xx, SPEAr6xx and
SPEAr13xx) are located in the platform code contained in arch/arm/plat-spear
with headers in plat/.
Each machine series have a directory with name arch/arm/mach-spear followed by
series name. Like mach-spear3xx, mach-spear6xx and mach-spear13xx.
Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
mach-spear* doesn't contains board specific files as they fully support
Flattened Device Tree.
Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c, for
spear6xx is mach-spear6xx/spear6xx.c and for spear13xx family is
mach-spear13xx/spear13xx.c. mach-spear* also contain soc/machine specific
files, like spear1310.c, spear1340.c spear300.c, spear310.c, spear320.c and
spear600.c. mach-spear* doesn't contains board specific files as they fully
support Flattened Device Tree.
Document Author
......
Documentation/cris/README
View file @ c2e1ff39
Linux 2.4 on the CRIS architecture
==================================
$Id: README,v 1.7 2001/04/19 12:38:32 bjornw Exp $
Linux on the CRIS architecture
==============================
This is a port of Linux 2.4 to Axis Communications ETRAX 100LX embedded
network CPU. For more information about CRIS and ETRAX please see further
below.
This is a port of Linux to Axis Communications ETRAX 100LX,
ETRAX FS and ARTPEC-3 embedded network CPUs.
For more information about CRIS and ETRAX please see further below.
In order to compile this you need a version of gcc with support for the
ETRAX chip family. Please see this link for more information on how to
ETRAX chip family. Please see this link for more information on how to
download the compiler and other tools useful when building and booting
software for the ETRAX platform:
http://developer.axis.com/doc/software/devboard_lx/install-howto.html
<more specific information should come in this document later>
http://developer.axis.com/wiki/doku.php?id=axis:install-howto-2_20
What is CRIS ?
--------------
CRIS is an acronym for 'Code Reduced Instruction Set'. It is the CPU
architecture in Axis Communication AB's range of embedded network CPU's,
called ETRAX. The latest CPU is called ETRAX 100LX, where LX stands for
'Linux' because the chip was designed to be a good host for the Linux
operating system.
called ETRAX.
The ETRAX 100LX chip
--------------------
For reference, please see the press-release:
For reference, please see the following link:
http://www.axis.com/news/us/001101_etrax.htm
http://www.axis.com/products/dev_etrax_100lx/index.htm
The ETRAX 100LX is a 100 MIPS processor with 8kB cache, MMU, and a very broad
range of built-in interfaces, all with modern scatter/gather DMA.
The ETRAX 100LX is a 100 MIPS processor with 8kB cache, MMU, and a very broad
range of built-in interfaces, all with modern scatter/gather DMA.
Memory interfaces:
......@@ -51,20 +47,28 @@ I/O interfaces:
* SCSI
* two parallel-ports
* two generic 8-bit ports
(not all interfaces are available at the same time due to chip pin
(not all interfaces are available at the same time due to chip pin
multiplexing)
The previous version of the ETRAX, the ETRAX 100, sits in almost all of
Axis shipping thin-servers like the Axis 2100 web camera or the ETRAX 100
developer-board. It lacks an MMU so the Linux we run on that is a version
of uClinux (Linux 2.0 without MM-support) ported to the CRIS architecture.
The new Linux 2.4 port has full MM and needs a CPU with an MMU, so it will
not run on the ETRAX 100.
ETRAX 100LX is CRISv10 architecture.
The ETRAX FS and ARTPEC-3 chips
-------------------------------
A version of the Axis developer-board with ETRAX 100LX (running Linux
2.4) is now available. For more information please see developer.axis.com.
The ETRAX FS is a 200MHz 32-bit RISC processor with on-chip 16kB
I-cache and 16kB D-cache and with a wide range of device interfaces
including multiple high speed serial ports and an integrated USB 1.1 PHY.
The ARTPEC-3 is a variant of the ETRAX FS with additional IO-units
used by the Axis Communications network cameras.
See below link for more information:
http://www.axis.com/products/dev_etrax_fs/index.htm
ETRAX FS and ARTPEC-3 are both CRISv32 architectures.
Bootlog
-------
......@@ -182,10 +186,6 @@ SwapFree: 0 kB
-rwxr-xr-x 1 342 100 16252 Jan 01 00:00 telnetd
(All programs are statically linked to the libc at this point - we have not ported the
shared libraries yet)
......
Documentation/devicetree/bindings/arm/fsl.txt
View file @ c2e1ff39
Freescale i.MX Platforms Device Tree Bindings
-----------------------------------------------
i.MX23 Evaluation Kit
Required root node properties:
- compatible = "fsl,imx23-evk", "fsl,imx23";
i.MX28 Evaluation Kit
Required root node properties:
- compatible = "fsl,imx28-evk", "fsl,imx28";
i.MX51 Babbage Board
Required root node properties:
- compatible = "fsl,imx51-babbage", "fsl,imx51";
......@@ -29,6 +37,10 @@ i.MX6 Quad SABRE Lite Board
Required root node properties:
- compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
i.MX6 Quad SABRE Smart Device Board
Required root node properties:
- compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
Generic i.MX boards
-------------------
......
Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt 0 → 100644
View file @ c2e1ff39
* Samsung Exynos Interrupt Combiner Controller
Samsung's Exynos4 architecture includes a interrupt combiner controller which
can combine interrupt sources as a group and provide a single interrupt request
for the group. The interrupt request from each group are connected to a parent
interrupt controller, such as GIC in case of Exynos4210.
The interrupt combiner controller consists of multiple combiners. Upto eight
interrupt sources can be connected to a combiner. The combiner outputs one
combined interrupt for its eight interrupt sources. The combined interrupt
is usually connected to a parent interrupt controller.
A single node in the device tree is used to describe the interrupt combiner
controller module (which includes multiple combiners). A combiner in the
interrupt controller module shares config/control registers with other
combiners. For example, a 32-bit interrupt enable/disable config register
can accommodate upto 4 interrupt combiners (with each combiner supporting
upto 8 interrupt sources).
Required properties:
- compatible: should be "samsung,exynos4210-combiner".
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: should be <2>. The meaning of the cells are
* First Cell: Combiner Group Number.
* Second Cell: Interrupt number within the group.
- reg: Base address and size of interrupt combiner registers.
- interrupts: The list of interrupts generated by the combiners which are then
connected to a parent interrupt controller. The format of the interrupt
specifier depends in the interrupt parent controller.
Optional properties:
- samsung,combiner-nr: The number of interrupt combiners supported. If this
property is not specified, the default number of combiners is assumed
to be 16.
- interrupt-parent: pHandle of the parent interrupt controller, if not
inherited from the parent node.
Example:
The following is a an example from the Exynos4210 SoC dtsi file.
combiner:interrupt-controller@10440000 {
compatible = "samsung,exynos4210-combiner";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x10440000 0x1000>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
};
Documentation/devicetree/bindings/arm/spear-timer.txt 0 → 100644
View file @ c2e1ff39
* SPEAr ARM Timer
** Timer node required properties:
- compatible : Should be:
"st,spear-timer"
- reg: Address range of the timer registers
- interrupt-parent: Should be the phandle for the interrupt controller
that services interrupts for this device
- interrupt: Should contain the timer interrupt number
Example:
timer@f0000000 {
compatible = "st,spear-timer";
reg = <0xf0000000 0x400>;
interrupts = <2>;
};
Documentation/devicetree/bindings/arm/spear.txt
View file @ c2e1ff39
......@@ -2,25 +2,25 @@ ST SPEAr Platforms Device Tree Bindings
---------------------------------------
Boards with the ST SPEAr600 SoC shall have the following properties:
Required root node property:
compatible = "st,spear600";
Boards with the ST SPEAr300 SoC shall have the following properties:
Required root node property:
compatible = "st,spear300";
Boards with the ST SPEAr310 SoC shall have the following properties:
Required root node property:
compatible = "st,spear310";
Boards with the ST SPEAr320 SoC shall have the following properties:
Required root node property:
compatible = "st,spear320";
Boards with the ST SPEAr1310 SoC shall have the following properties:
Required root node property:
compatible = "st,spear1310";
compatible = "st,spear320";
Boards with the ST SPEAr1340 SoC shall have the following properties:
Required root node property:
compatible = "st,spear1340";
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt 0 → 100644
View file @ c2e1ff39
NVIDIA Tegra AHB
Required properties:
- compatible : "nvidia,tegra20-ahb" or "nvidia,tegra30-ahb"
- reg : Should contain 1 register ranges(address and length)
Example:
ahb: ahb@6000c004 {
compatible = "nvidia,tegra20-ahb";
reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
};
Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt 0 → 100644
View file @ c2e1ff39
* Freescale MXS DMA
Required properties:
- compatible : Should be "fsl,<chip>-dma-apbh" or "fsl,<chip>-dma-apbx"
- reg : Should contain registers location and length
Supported chips:
imx23, imx28.
Examples:
dma-apbh@80004000 {
compatible = "fsl,imx28-dma-apbh";
reg = <0x80004000 2000>;
};
dma-apbx@80024000 {
compatible = "fsl,imx28-dma-apbx";
reg = <0x80024000 2000>;
};
Documentation/devicetree/bindings/dma/snps-dma.txt 0 → 100644
View file @ c2e1ff39
* Synopsys Designware DMA Controller
Required properties:
- compatible: "snps,dma-spear1340"
- reg: Address range of the DMAC registers
- interrupt-parent: Should be the phandle for the interrupt controller
that services interrupts for this device
- interrupt: Should contain the DMAC interrupt number
Example:
dma@fc000000 {
compatible = "snps,dma-spear1340";
reg = <0xfc000000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <12>;
};
Documentation/devicetree/bindings/gpio/gpio-mxs.txt 0 → 100644
View file @ c2e1ff39
* Freescale MXS GPIO controller
The Freescale MXS GPIO controller is part of MXS PIN controller. The
GPIOs are organized in port/bank. Each port consists of 32 GPIOs.
As the GPIO controller is embedded in the PIN controller and all the
GPIO ports share the same IO space with PIN controller, the GPIO node
will be represented as sub-nodes of MXS pinctrl node.
Required properties for GPIO node:
- compatible : Should be "fsl,<soc>-gpio". The supported SoCs include
imx23 and imx28.
- interrupts : Should be the port interrupt shared by all 32 pins.
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells : Should be two. The first cell is the pin number and
the second cell is used to specify optional parameters (currently
unused).
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells : Should be 2. The first cell is the GPIO number.
The second cell bits[3:0] is used to specify trigger type and level flags:
1 = low-to-high edge triggered.
2 = high-to-low edge triggered.
4 = active high level-sensitive.
8 = active low level-sensitive.
Note: Each GPIO port should have an alias correctly numbered in "aliases"
node.
Examples:
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
};
pinctrl@80018000 {
compatible = "fsl,imx28-pinctrl", "simple-bus";
reg = <0x80018000 2000>;
gpio0: gpio@0 {
compatible = "fsl,imx28-gpio";
interrupts = <127>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@1 {
compatible = "fsl,imx28-gpio";
interrupts = <126>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@2 {
compatible = "fsl,imx28-gpio";
interrupts = <125>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@3 {
compatible = "fsl,imx28-gpio";
interrupts = <124>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@4 {
compatible = "fsl,imx28-gpio";
interrupts = <123>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
Documentation/devicetree/bindings/i2c/i2c-mxs.txt 0 → 100644
View file @ c2e1ff39
* Freescale MXS Inter IC (I2C) Controller
Required properties:
- compatible: Should be "fsl,<chip>-i2c"
- reg: Should contain registers location and length
- interrupts: Should contain ERROR and DMA interrupts
Examples:
i2c0: i2c@80058000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx28-i2c";
reg = <0x80058000 2000>;
interrupts = <111 68>;
};
Documentation/devicetree/bindings/i2c/mux.txt 0 → 100644
View file @ c2e1ff39
Common i2c bus multiplexer/switch properties.
An i2c bus multiplexer/switch will have several child busses that are
numbered uniquely in a device dependent manner. The nodes for an i2c bus
multiplexer/switch will have one child node for each child
bus.
Required properties:
- #address-cells = <1>;
- #size-cells = <0>;
Required properties for child nodes:
- #address-cells = <1>;
- #size-cells = <0>;
- reg : The sub-bus number.
Optional properties for child nodes:
- Other properties specific to the multiplexer/switch hardware.
- Child nodes conforming to i2c bus binding
Example :
/*
An NXP pca9548 8 channel I2C multiplexer at address 0x70
with two NXP pca8574 GPIO expanders attached, one each to
ports 3 and 4.
*/
mux@70 {
compatible = "nxp,pca9548";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
gpio1: gpio@38 {
compatible = "nxp,pca8574";
reg = <0x38>;
#gpio-cells = <2>;
gpio-controller;
};
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
gpio2: gpio@38 {
compatible = "nxp,pca8574";
reg = <0x38>;
#gpio-cells = <2>;
gpio-controller;
};
};
};
Documentation/devicetree/bindings/i2c/samsung-i2c.txt
View file @ c2e1ff39
......@@ -6,14 +6,18 @@ Required properties:
- compatible: value should be either of the following.
(a) "samsung, s3c2410-i2c", for i2c compatible with s3c2410 i2c.
(b) "samsung, s3c2440-i2c", for i2c compatible with s3c2440 i2c.
(c) "samsung, s3c2440-hdmiphy-i2c", for s3c2440-like i2c used
inside HDMIPHY block found on several samsung SoCs
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
- samsung,i2c-sda-delay: Delay (in ns) applied to data line (SDA) edges.
- gpios: The order of the gpios should be the following: <SDA, SCL>.
The gpio specifier depends on the gpio controller.
Optional properties:
- gpios: The order of the gpios should be the following: <SDA, SCL>.
The gpio specifier depends on the gpio controller. Required in all
cases except for "samsung,s3c2440-hdmiphy-i2c" whose input/output
lines are permanently wired to the respective client
- samsung,i2c-slave-addr: Slave address in multi-master enviroment. If not
specified, default value is 0.
- samsung,i2c-max-bus-freq: Desired frequency in Hz of the bus. If not
......
Documentation/devicetree/bindings/i2c/xiic.txt 0 → 100644
View file @ c2e1ff39
Xilinx IIC controller:
Required properties:
- compatible : Must be "xlnx,xps-iic-2.00.a"
- reg : IIC register location and length
- interrupts : IIC controller unterrupt
- #address-cells = <1>
- #size-cells = <0>
Optional properties:
- Child nodes conforming to i2c bus binding
Example:
axi_iic_0: i2c@40800000 {
compatible = "xlnx,xps-iic-2.00.a";
interrupts = < 1 2 >;
reg = < 0x40800000 0x10000 >;
#size-cells = <0>;
#address-cells = <1>;
};
Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
View file @ c2e1ff39
......@@ -11,9 +11,11 @@ Required properties:
- interrupt-parent : interrupt source phandle.
- clock-frequency : specifies eSDHC base clock frequency.
- sdhci,wp-inverted : (optional) specifies that eSDHC controller
reports inverted write-protect state;
reports inverted write-protect state; New devices should use
the generic "wp-inverted" property.
- sdhci,1-bit-only : (optional) specifies that a controller can
only handle 1-bit data transfers.
only handle 1-bit data transfers. New devices should use the
generic "bus-width = <1>" property.
- sdhci,auto-cmd12: (optional) specifies that a controller can
only handle auto CMD12.
......
Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
View file @ c2e1ff39
......@@ -9,7 +9,7 @@ Required properties:
- interrupts : Should contain eSDHC interrupt
Optional properties:
- fsl,card-wired : Indicate the card is wired to host permanently
- non-removable : Indicate the card is wired to host permanently
- fsl,cd-internal : Indicate to use controller internal card detection
- fsl,wp-internal : Indicate to use controller internal write protection
- cd-gpios : Specify GPIOs for card detection
......
Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt
View file @ c2e1ff39
......@@ -10,7 +10,8 @@ Required properties:
Optional properties:
- gpios : may specify GPIOs in this order: Card-Detect GPIO,
Write-Protect GPIO.
Write-Protect GPIO. Note that this does not follow the
binding from mmc.txt, for historic reasons.
- interrupts : the interrupt of a card detect interrupt.
- interrupt-parent : the phandle for the interrupt controller that
services interrupts for this device.
......
Documentation/devicetree/bindings/mmc/mmc.txt 0 → 100644
View file @ c2e1ff39
These properties are common to multiple MMC host controllers. Any host
that requires the respective functionality should implement them using
these definitions.
Required properties:
- bus-width: Number of data lines, can be <1>, <4>, or <8>
Optional properties:
- cd-gpios : Specify GPIOs for card detection, see gpio binding
- wp-gpios : Specify GPIOs for write protection, see gpio binding
- cd-inverted: when present, polarity on the wp gpio line is inverted
- wp-inverted: when present, polarity on the wp gpio line is inverted
- non-removable: non-removable slot (like eMMC)
- max-frequency: maximum operating clock frequency
Example:
sdhci@ab000000 {
compatible = "sdhci";
reg = <0xab000000 0x200>;
interrupts = <23>;
bus-width = <4>;
cd-gpios = <&gpio 69 0>;
cd-inverted;
wp-gpios = <&gpio 70 0>;
max-frequency = <50000000>;
}
Documentation/devicetree/bindings/mmc/mmci.txt 0 → 100644
View file @ c2e1ff39
* ARM PrimeCell MultiMedia Card Interface (MMCI) PL180/1
The ARM PrimeCell MMCI PL180 and PL181 provides and interface for
reading and writing to MultiMedia and SD cards alike.
Required properties:
- compatible : contains "arm,pl18x", "arm,primecell".
- reg : contains pl18x registers and length.
- interrupts : contains the device IRQ(s).
- arm,primecell-periphid : contains the PrimeCell Peripheral ID.
Optional properties:
- wp-gpios : contains any write protect (ro) gpios
- cd-gpios : contains any card detection gpios
- cd-inverted : indicates whether the cd gpio is inverted
- max-frequency : contains the maximum operating frequency
- bus-width : number of data lines, can be <1>, <4>, or <8>
- mmc-cap-mmc-highspeed : indicates whether MMC is high speed capable
- mmc-cap-sd-highspeed : indicates whether SD is high speed capable
Documentation/devicetree/bindings/mmc/mxs-mmc.txt 0 → 100644
View file @ c2e1ff39
* Freescale MXS MMC controller
The Freescale MXS Synchronous Serial Ports (SSP) can act as a MMC controller
to support MMC, SD, and SDIO types of memory cards.
Required properties:
- compatible: Should be "fsl,<chip>-mmc". The supported chips include
imx23 and imx28.
- reg: Should contain registers location and length
- interrupts: Should contain ERROR and DMA interrupts
- fsl,ssp-dma-channel: APBH DMA channel for the SSP
- bus-width: Number of data lines, can be <1>, <4>, or <8>
Optional properties:
- wp-gpios: Specify GPIOs for write protection
Examples:
ssp0: ssp@80010000 {
compatible = "fsl,imx28-mmc";
reg = <0x80010000 2000>;
interrupts = <96 82>;
fsl,ssp-dma-channel = <0>;
bus-width = <8>;
};
Documentation/devicetree/bindings/mmc/nvidia-sdhci.txt
View file @ c2e1ff39
......@@ -7,12 +7,12 @@ Required properties:
- compatible : Should be "nvidia,<chip>-sdhci"
- reg : Should contain SD/MMC registers location and length
- interrupts : Should contain SD/MMC interrupt
- bus-width : Number of data lines, can be <1>, <4>, or <8>
Optional properties:
- cd-gpios : Specify GPIOs for card detection
- wp-gpios : Specify GPIOs for write protection
- power-gpios : Specify GPIOs for power control
- support-8bit : Boolean, indicates if 8-bit mode should be used.
Example:
......@@ -23,5 +23,5 @@ sdhci@c8000200 {
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 155 0>; /* gpio PT3 */
support-8bit;
bus-width = <8>;
};
Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
View file @ c2e1ff39
......@@ -15,7 +15,7 @@ Optional properties:
ti,dual-volt: boolean, supports dual voltage cards
<supply-name>-supply: phandle to the regulator device tree node
"supply-name" examples are "vmmc", "vmmc_aux" etc
ti,bus-width: Number of data lines, default assumed is 1 if the property is missing.
bus-width: Number of data lines, default assumed is 1 if the property is missing.
cd-gpios: GPIOs for card detection
wp-gpios: GPIOs for write protection
ti,non-removable: non-removable slot (like eMMC)
......@@ -27,7 +27,7 @@ Example:
reg = <0x4809c000 0x400>;
ti,hwmods = "mmc1";
ti,dual-volt;
ti,bus-width = <4>;
bus-width = <4>;
vmmc-supply = <&vmmc>; /* phandle to regulator node */
ti,non-removable;
};
Documentation/devicetree/bindings/net/fsl-fec.txt
View file @ c2e1ff39
......@@ -14,7 +14,7 @@ Optional properties:
Example:
fec@83fec000 {
ethernet@83fec000 {
compatible = "fsl,imx51-fec", "fsl,imx27-fec";
reg = <0x83fec000 0x4000>;
interrupts = <87>;
......
Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
View file @ c2e1ff39
......@@ -4,6 +4,8 @@ Required properties:
- compatible : "st,spear300-pinmux"
: "st,spear310-pinmux"
: "st,spear320-pinmux"
: "st,spear1310-pinmux"
: "st,spear1340-pinmux"
- reg : Address range of the pinctrl registers
- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
- Its values for SPEAr300:
......@@ -89,6 +91,37 @@ For SPEAr320 machines:
"rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
"i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
For SPEAr1310 machines:
"i2c0_grp", "ssp0_grp", "ssp0_cs0_grp", "ssp0_cs1_2_grp", "i2s0_grp",
"i2s1_grp", "clcd_grp", "clcd_high_res_grp", "arm_gpio_grp",
"smi_2_chips_grp", "smi_4_chips_grp", "gmii_grp", "rgmii_grp",
"smii_0_1_2_grp", "ras_mii_txclk_grp", "nand_8bit_grp",
"nand_16bit_grp", "nand_4_chips_grp", "keyboard_6x6_grp",
"keyboard_rowcol6_8_grp", "uart0_grp", "uart0_modem_grp",
"gpt0_tmr0_grp", "gpt0_tmr1_grp", "gpt1_tmr0_grp", "gpt1_tmr1_grp",
"sdhci_grp", "cf_grp", "xd_grp", "touch_xy_grp",
"uart1_disable_i2c_grp", "uart1_disable_sd_grp", "uart2_3_grp",
"uart4_grp", "uart5_grp", "rs485_0_1_tdm_0_1_grp", "i2c_1_2_grp",
"i2c3_dis_smi_clcd_grp", "i2c3_dis_sd_i2s0_grp", "i2c_4_5_dis_smi_grp",
"i2c4_dis_sd_grp", "i2c5_dis_sd_grp", "i2c_6_7_dis_kbd_grp",
"i2c6_dis_sd_grp", "i2c7_dis_sd_grp", "can0_dis_nor_grp",
"can0_dis_sd_grp", "can1_dis_sd_grp", "can1_dis_kbd_grp", "pcie0_grp",
"pcie1_grp", "pcie2_grp", "sata0_grp", "sata1_grp", "sata2_grp",
"ssp1_dis_kbd_grp", "ssp1_dis_sd_grp", "gpt64_grp"
For SPEAr1340 machines:
"pads_as_gpio_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "fsmc_pnor_grp",
"keyboard_row_col_grp", "keyboard_col5_grp", "spdif_in_grp",
"spdif_out_grp", "gpt_0_1_grp", "pwm0_grp", "pwm1_grp", "pwm2_grp",
"pwm3_grp", "vip_mux_grp", "vip_mux_cam0_grp", "vip_mux_cam1_grp",
"vip_mux_cam2_grp", "vip_mux_cam3_grp", "cam0_grp", "cam1_grp",
"cam2_grp", "cam3_grp", "smi_grp", "ssp0_grp", "ssp0_cs1_grp",
"ssp0_cs2_grp", "ssp0_cs3_grp", "uart0_grp", "uart0_enh_grp",
"uart1_grp", "i2s_in_grp", "i2s_out_grp", "gmii_grp", "rgmii_grp",
"rmii_grp", "sgmii_grp", "i2c0_grp", "i2c1_grp", "cec0_grp", "cec1_grp",
"sdhci_grp", "cf_grp", "xd_grp", "clcd_grp", "arm_trace_grp",
"miphy_dbg_grp", "pcie_grp", "sata_grp"
Valid values for function names are:
For All SPEAr3xx machines:
"firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
......@@ -106,3 +139,17 @@ For SPEAr320 machines:
"uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
"can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
"mii0_1", "i2c1", "i2c2"
For SPEAr1310 machines:
"i2c0", "ssp0", "i2s0", "i2s1", "clcd", "arm_gpio", "smi", "gmii",
"rgmii", "smii_0_1_2", "ras_mii_txclk", "nand", "keyboard", "uart0",
"gpt0", "gpt1", "sdhci", "cf", "xd", "touchscreen", "uart1", "uart2_3",
"uart4", "uart5", "rs485_0_1_tdm_0_1", "i2c_1_2", "i2c3_i2s1",
"i2c_4_5", "i2c_6_7", "can0", "can1", "pci", "sata", "ssp1", "gpt64"
For SPEAr1340 machines:
"pads_as_gpio", "fsmc", "keyboard", "spdif_in", "spdif_out", "gpt_0_1",
"pwm", "vip", "cam0", "cam1", "cam2", "cam3", "smi", "ssp0", "uart0",
"uart1", "i2s", "gmac", "i2c0", "i2c1", "cec0", "cec1", "sdhci", "cf",
"xd", "clcd", "arm_trace", "miphy_dbg", "pcie", "sata"
Documentation/devicetree/bindings/sound/omap-dmic.txt 0 → 100644
View file @ c2e1ff39
* Texas Instruments OMAP4+ Digital Microphone Module
Required properties:
- compatible: "ti,omap4-dmic"
- reg: Register location and size as an array:
<MPU access base address, size>,
<L3 interconnect address, size>;
- interrupts: Interrupt number for DMIC
- interrupt-parent: The parent interrupt controller
- ti,hwmods: Name of the hwmod associated with OMAP dmic IP
Example:
dmic: dmic@4012e000 {
compatible = "ti,omap4-dmic";
reg = <0x4012e000 0x7f>, /* MPU private access */
<0x4902e000 0x7f>; /* L3 Interconnect */
interrupts = <0 114 0x4>;
interrupt-parent = <&gic>;
ti,hwmods = "dmic";
};
Documentation/devicetree/bindings/sound/omap-mcpdm.txt 0 → 100644
View file @ c2e1ff39
* Texas Instruments OMAP4+ McPDM
Required properties:
- compatible: "ti,omap4-mcpdm"
- reg: Register location and size as an array:
<MPU access base address, size>,
<L3 interconnect address, size>;
- interrupts: Interrupt number for McPDM
- interrupt-parent: The parent interrupt controller
- ti,hwmods: Name of the hwmod associated to the McPDM
Example:
mcpdm: mcpdm@40132000 {
compatible = "ti,omap4-mcpdm";
reg = <0x40132000 0x7f>, /* MPU private access */
<0x49032000 0x7f>; /* L3 Interconnect */
interrupts = <0 112 0x4>;
interrupt-parent = <&gic>;
ti,hwmods = "mcpdm";
};
Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt
View file @ c2e1ff39
......@@ -11,7 +11,7 @@ Optional properties:
Example:
uart@73fbc000 {
serial@73fbc000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fbc000 0x4000>;
interrupts = <31>;
......
Documentation/devicetree/bindings/usb/tegra-usb.txt
View file @ c2e1ff39
......@@ -12,6 +12,9 @@ Required properties :
- nvidia,vbus-gpio : If present, specifies a gpio that needs to be
activated for the bus to be powered.
Required properties for phy_type == ulpi:
- nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
Optional properties:
- dr_mode : dual role mode. Indicates the working mode for
nvidia,tegra20-ehci compatible controllers. Can be "host", "peripheral",
......
Documentation/dma-buf-sharing.txt
View file @ c2e1ff39
......@@ -29,13 +29,6 @@ The buffer-user
in memory, mapped into its own address space, so it can access the same area
of memory.
*IMPORTANT*: [see https://lkml.org/lkml/2011/12/20/211 for more details]
For this first version, A buffer shared using the dma_buf sharing API:
- *may* be exported to user space using "mmap" *ONLY* by exporter, outside of
this framework.
- with this new iteration of the dma-buf api cpu access from the kernel has been
enable, see below for the details.
dma-buf operations for device dma only
--------------------------------------
......@@ -300,6 +293,17 @@ Access to a dma_buf from the kernel context involves three steps:
Note that these calls need to always succeed. The exporter needs to complete
any preparations that might fail in begin_cpu_access.
For some cases the overhead of kmap can be too high, a vmap interface
is introduced. This interface should be used very carefully, as vmalloc
space is a limited resources on many architectures.
Interfaces:
void *dma_buf_vmap(struct dma_buf *dmabuf)
void dma_buf_vunmap(struct dma_buf *dmabuf, void *vaddr)
The vmap call can fail if there is no vmap support in the exporter, or if it
runs out of vmalloc space. Fallback to kmap should be implemented.
3. Finish access
When the importer is done accessing the range specified in begin_cpu_access,
......@@ -313,6 +317,83 @@ Access to a dma_buf from the kernel context involves three steps:
enum dma_data_direction dir);
Direct Userspace Access/mmap Support
------------------------------------
Being able to mmap an export dma-buf buffer object has 2 main use-cases:
- CPU fallback processing in a pipeline and
- supporting existing mmap interfaces in importers.
1. CPU fallback processing in a pipeline
In many processing pipelines it is sometimes required that the cpu can access
the data in a dma-buf (e.g. for thumbnail creation, snapshots, ...). To avoid
the need to handle this specially in userspace frameworks for buffer sharing
it's ideal if the dma_buf fd itself can be used to access the backing storage
from userspace using mmap.
Furthermore Android's ION framework already supports this (and is otherwise
rather similar to dma-buf from a userspace consumer side with using fds as
handles, too). So it's beneficial to support this in a similar fashion on
dma-buf to have a good transition path for existing Android userspace.
No special interfaces, userspace simply calls mmap on the dma-buf fd.
2. Supporting existing mmap interfaces in exporters
Similar to the motivation for kernel cpu access it is again important that
the userspace code of a given importing subsystem can use the same interfaces
with a imported dma-buf buffer object as with a native buffer object. This is
especially important for drm where the userspace part of contemporary OpenGL,
X, and other drivers is huge, and reworking them to use a different way to
mmap a buffer rather invasive.
The assumption in the current dma-buf interfaces is that redirecting the
initial mmap is all that's needed. A survey of some of the existing
subsystems shows that no driver seems to do any nefarious thing like syncing
up with outstanding asynchronous processing on the device or allocating
special resources at fault time. So hopefully this is good enough, since
adding interfaces to intercept pagefaults and allow pte shootdowns would
increase the complexity quite a bit.
Interface:
int dma_buf_mmap(struct dma_buf *, struct vm_area_struct *,
unsigned long);
If the importing subsystem simply provides a special-purpose mmap call to set
up a mapping in userspace, calling do_mmap with dma_buf->file will equally
achieve that for a dma-buf object.
3. Implementation notes for exporters
Because dma-buf buffers have invariant size over their lifetime, the dma-buf
core checks whether a vma is too large and rejects such mappings. The
exporter hence does not need to duplicate this check.
Because existing importing subsystems might presume coherent mappings for
userspace, the exporter needs to set up a coherent mapping. If that's not
possible, it needs to fake coherency by manually shooting down ptes when
leaving the cpu domain and flushing caches at fault time. Note that all the
dma_buf files share the same anon inode, hence the exporter needs to replace
the dma_buf file stored in vma->vm_file with it's own if pte shootdown is
requred. This is because the kernel uses the underlying inode's address_space
for vma tracking (and hence pte tracking at shootdown time with
unmap_mapping_range).
If the above shootdown dance turns out to be too expensive in certain
scenarios, we can extend dma-buf with a more explicit cache tracking scheme
for userspace mappings. But the current assumption is that using mmap is
always a slower path, so some inefficiencies should be acceptable.
Exporters that shoot down mappings (for any reasons) shall not do any
synchronization at fault time with outstanding device operations.
Synchronization is an orthogonal issue to sharing the backing storage of a
buffer and hence should not be handled by dma-buf itself. This is explictly
mentioned here because many people seem to want something like this, but if
different exporters handle this differently, buffer sharing can fail in
interesting ways depending upong the exporter (if userspace starts depending
upon this implicit synchronization).
Miscellaneous notes
-------------------
......@@ -336,6 +417,20 @@ Miscellaneous notes
the exporting driver to create a dmabuf fd must provide a way to let
userspace control setting of O_CLOEXEC flag passed in to dma_buf_fd().
- If an exporter needs to manually flush caches and hence needs to fake
coherency for mmap support, it needs to be able to zap all the ptes pointing
at the backing storage. Now linux mm needs a struct address_space associated
with the struct file stored in vma->vm_file to do that with the function
unmap_mapping_range. But the dma_buf framework only backs every dma_buf fd
with the anon_file struct file, i.e. all dma_bufs share the same file.
Hence exporters need to setup their own file (and address_space) association
by setting vma->vm_file and adjusting vma->vm_pgoff in the dma_buf mmap
callback. In the specific case of a gem driver the exporter could use the
shmem file already provided by gem (and set vm_pgoff = 0). Exporters can then
zap ptes by unmapping the corresponding range of the struct address_space
associated with their own file.
References:
[1] struct dma_buf_ops in include/linux/dma-buf.h
[2] All interfaces mentioned above defined in include/linux/dma-buf.h
......
Documentation/feature-removal-schedule.txt
View file @ c2e1ff39
......@@ -595,3 +595,14 @@ Why: KVM tracepoints provide mostly equivalent information in a much more
flexible fashion.
----------------------------
What: at91-mci driver ("CONFIG_MMC_AT91")
When: 3.7
Why: There are two mci drivers: at91-mci and atmel-mci. The PDC support
was added to atmel-mci as a first step to support more chips.
Then at91-mci was kept only for old IP versions (on at91rm9200 and
at91sam9261). The support of these IP versions has just been added
to atmel-mci, so atmel-mci can be used for all chips.
Who: Ludovic Desroches <ludovic.desroches@atmel.com>
----------------------------
Documentation/filesystems/ext3.txt
View file @ c2e1ff39
......@@ -59,9 +59,9 @@ commit=nrsec (*) Ext3 can be told to sync all its data and metadata
Setting it to very large values will improve
performance.
barrier=<0(*)|1> This enables/disables the use of write barriers in
barrier the jbd code. barrier=0 disables, barrier=1 enables.
nobarrier (*) This also requires an IO stack which can support
barrier=<0|1(*)> This enables/disables the use of write barriers in
barrier (*) the jbd code. barrier=0 disables, barrier=1 enables.
nobarrier This also requires an IO stack which can support
barriers, and if jbd gets an error on a barrier
write, it will disable again with a warning.
Write barriers enforce proper on-disk ordering
......
Documentation/i2c/muxes/gpio-i2cmux → Documentation/i2c/muxes/i2c-mux-gpio
View file @ c2e1ff39
Kernel driver gpio-i2cmux
Kernel driver i2c-gpio-mux
Author: Peter Korsgaard <peter.korsgaard@barco.com>
Description
-----------
gpio-i2cmux is an i2c mux driver providing access to I2C bus segments
i2c-gpio-mux is an i2c mux driver providing access to I2C bus segments
from a master I2C bus and a hardware MUX controlled through GPIO pins.
E.G.:
......@@ -26,16 +26,16 @@ according to the settings of the GPIO pins 1..N.
Usage
-----
gpio-i2cmux uses the platform bus, so you need to provide a struct
i2c-gpio-mux uses the platform bus, so you need to provide a struct
platform_device with the platform_data pointing to a struct
gpio_i2cmux_platform_data with the I2C adapter number of the master
bus, the number of bus segments to create and the GPIO pins used
to control it. See include/linux/gpio-i2cmux.h for details.
to control it. See include/linux/i2c-gpio-mux.h for details.
E.G. something like this for a MUX providing 4 bus segments
controlled through 3 GPIO pins:
#include <linux/gpio-i2cmux.h>
#include <linux/i2c-gpio-mux.h>
#include <linux/platform_device.h>
static const unsigned myboard_gpiomux_gpios[] = {
......@@ -57,7 +57,7 @@ static struct gpio_i2cmux_platform_data myboard_i2cmux_data = {
};
static struct platform_device myboard_i2cmux = {
.name = "gpio-i2cmux",
.name = "i2c-gpio-mux",
.id = 0,
.dev = {
.platform_data = &myboard_i2cmux_data,
......
Documentation/kernel-parameters.txt
View file @ c2e1ff39
......@@ -508,6 +508,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
Also note the kernel might malfunction if you disable
some critical bits.
cma=nn[MG] [ARM,KNL]
Sets the size of kernel global memory area for contiguous
memory allocations. For more information, see
include/linux/dma-contiguous.h
cmo_free_hint= [PPC] Format: { yes | no }
Specify whether pages are marked as being inactive
when they are freed. This is used in CMO environments
......@@ -515,6 +520,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
a hypervisor.
Default: yes
coherent_pool=nn[KMG] [ARM,KNL]
Sets the size of memory pool for coherent, atomic dma
allocations if Contiguous Memory Allocator (CMA) is used.
code_bytes [X86] How many bytes of object code to print
in an oops report.
Range: 0 - 8192
......
MAINTAINERS
View file @ c2e1ff39
......@@ -1905,6 +1905,16 @@ F: Documentation/filesystems/coda.txt
F: fs/coda/
F: include/linux/coda*.h
COMMON CLK FRAMEWORK
M: Mike Turquette <mturquette@ti.com>
M: Mike Turquette <mturquette@linaro.org>
L: linux-arm-kernel@lists.infradead.org (same as CLK API & CLKDEV)
T: git git://git.linaro.org/people/mturquette/linux.git
S: Maintained
F: drivers/clk/clk.c
F: drivers/clk/clk-*
F: include/linux/clk-pr*
COMMON INTERNET FILE SYSTEM (CIFS)
M: Steve French <sfrench@samba.org>
L: linux-cifs@vger.kernel.org
......@@ -2978,9 +2988,9 @@ GENERIC GPIO I2C MULTIPLEXER DRIVER
M: Peter Korsgaard <peter.korsgaard@barco.com>
L: linux-i2c@vger.kernel.org
S: Supported
F: drivers/i2c/muxes/gpio-i2cmux.c
F: include/linux/gpio-i2cmux.h
F: Documentation/i2c/muxes/gpio-i2cmux
F: drivers/i2c/muxes/i2c-mux-gpio.c
F: include/linux/i2c-mux-gpio.h
F: Documentation/i2c/muxes/i2c-mux-gpio
GENERIC HDLC (WAN) DRIVERS
M: Krzysztof Halasa <khc@pm.waw.pl>
......@@ -5138,7 +5148,7 @@ PCA9541 I2C BUS MASTER SELECTOR DRIVER
M: Guenter Roeck <guenter.roeck@ericsson.com>
L: linux-i2c@vger.kernel.org
S: Maintained
F: drivers/i2c/muxes/pca9541.c
F: drivers/i2c/muxes/i2c-mux-pca9541.c
PCA9564/PCA9665 I2C BUS DRIVER
M: Wolfram Sang <w.sang@pengutronix.de>
......@@ -6340,14 +6350,25 @@ F: include/linux/compiler.h
SPEAR PLATFORM SUPPORT
M: Viresh Kumar <viresh.kumar@st.com>
M: Shiraz Hashim <shiraz.hashim@st.com>
L: spear-devel@list.st.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.st.com/spear
S: Maintained
F: arch/arm/plat-spear/
SPEAR13XX MACHINE SUPPORT
M: Viresh Kumar <viresh.kumar@st.com>
M: Shiraz Hashim <shiraz.hashim@st.com>
L: spear-devel@list.st.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.st.com/spear
S: Maintained
F: arch/arm/mach-spear13xx/
SPEAR3XX MACHINE SUPPORT
M: Viresh Kumar <viresh.kumar@st.com>
M: Shiraz Hashim <shiraz.hashim@st.com>
L: spear-devel@list.st.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.st.com/spear
......@@ -6356,6 +6377,8 @@ F: arch/arm/mach-spear3xx/
SPEAR6XX MACHINE SUPPORT
M: Rajeev Kumar <rajeev-dlh.kumar@st.com>
M: Shiraz Hashim <shiraz.hashim@st.com>
M: Viresh Kumar <viresh.kumar@st.com>
L: spear-devel@list.st.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.st.com/spear
......@@ -6368,9 +6391,7 @@ L: spear-devel@list.st.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.st.com/spear
S: Maintained
F: arch/arm/mach-spear*/clock.c
F: arch/arm/plat-spear/clock.c
F: arch/arm/plat-spear/include/plat/clock.h
F: drivers/clk/spear/
SPI SUBSYSTEM
M: Grant Likely <grant.likely@secretlab.ca>
......
arch/Kconfig
View file @ c2e1ff39
......@@ -159,6 +159,9 @@ config HAVE_ARCH_TRACEHOOK
config HAVE_DMA_ATTRS
bool
config HAVE_DMA_CONTIGUOUS
bool
config USE_GENERIC_SMP_HELPERS
bool
......
arch/arm/Kconfig
View file @ c2e1ff39
......@@ -5,6 +5,9 @@ config ARM
select HAVE_AOUT
select HAVE_DMA_API_DEBUG
select HAVE_IDE if PCI || ISA || PCMCIA
select HAVE_DMA_ATTRS
select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
select CMA if (CPU_V6 || CPU_V6K || CPU_V7)
select HAVE_MEMBLOCK
select RTC_LIB
select SYS_SUPPORTS_APM_EMULATION
......@@ -54,6 +57,14 @@ config ARM
config ARM_HAS_SG_CHAIN
bool
config NEED_SG_DMA_LENGTH
bool
config ARM_DMA_USE_IOMMU
select NEED_SG_DMA_LENGTH
select ARM_HAS_SG_CHAIN
bool
config HAVE_PWM
bool
......@@ -445,8 +456,10 @@ config ARCH_MXS
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select COMMON_CLK
select HAVE_CLK_PREPARE
select PINCTRL
select USE_OF
help
Support for Freescale MXS-based family of processors
......@@ -936,6 +949,7 @@ config PLAT_SPEAR
select ARM_AMBA
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select COMMON_CLK
select CLKSRC_MMIO
select GENERIC_CLOCKEVENTS
select HAVE_CLK
......@@ -1040,7 +1054,6 @@ source "arch/arm/mach-sa1100/Kconfig"
source "arch/arm/plat-samsung/Kconfig"
source "arch/arm/plat-s3c24xx/Kconfig"
source "arch/arm/plat-s5p/Kconfig"
source "arch/arm/plat-spear/Kconfig"
......@@ -1091,6 +1104,7 @@ config PLAT_ORION
bool
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
select COMMON_CLK
config PLAT_PXA
bool
......
arch/arm/Kconfig.debug
View file @ c2e1ff39
......@@ -103,6 +103,35 @@ choice
Say Y here if you want the debug print routines to direct
their output to the second serial port on these devices.
config DEBUG_DAVINCI_DA8XX_UART1
bool "Kernel low-level debugging on DaVinci DA8XX using UART1"
depends on ARCH_DAVINCI_DA8XX
help
Say Y here if you want the debug print routines to direct
their output to UART1 serial port on DaVinci DA8XX devices.
config DEBUG_DAVINCI_DA8XX_UART2
bool "Kernel low-level debugging on DaVinci DA8XX using UART2"
depends on ARCH_DAVINCI_DA8XX
help
Say Y here if you want the debug print routines to direct
their output to UART2 serial port on DaVinci DA8XX devices.
config DEBUG_DAVINCI_DMx_UART0
bool "Kernel low-level debugging on DaVinci DMx using UART0"
depends on ARCH_DAVINCI_DMx
help
Say Y here if you want the debug print routines to direct
their output to UART0 serial port on DaVinci DMx devices.
config DEBUG_DAVINCI_TNETV107X_UART1
bool "Kernel low-level debugging on DaVinci TNETV107x using UART1"
depends on ARCH_DAVINCI_TNETV107X
help
Say Y here if you want the debug print routines to direct
their output to UART1 serial port on DaVinci TNETV107X
devices.
config DEBUG_DC21285_PORT
bool "Kernel low-level debugging messages via footbridge serial port"
depends on FOOTBRIDGE
......@@ -180,6 +209,14 @@ choice
Say Y here if you want kernel low-level debugging support
on i.MX50 or i.MX53.
config DEBUG_IMX6Q_UART2
bool "i.MX6Q Debug UART2"
depends on SOC_IMX6Q
help
Say Y here if you want kernel low-level debugging support
on i.MX6Q UART2. This is correct for e.g. the SabreLite
board.
config DEBUG_IMX6Q_UART4
bool "i.MX6Q Debug UART4"
depends on SOC_IMX6Q
......
arch/arm/Makefile
View file @ c2e1ff39
......@@ -160,9 +160,7 @@ machine-$(CONFIG_ARCH_MXS) := mxs
machine-$(CONFIG_ARCH_NETX) := netx
machine-$(CONFIG_ARCH_NOMADIK) := nomadik
machine-$(CONFIG_ARCH_OMAP1) := omap1
machine-$(CONFIG_ARCH_OMAP2) := omap2
machine-$(CONFIG_ARCH_OMAP3) := omap2
machine-$(CONFIG_ARCH_OMAP4) := omap2
machine-$(CONFIG_ARCH_OMAP2PLUS) := omap2
machine-$(CONFIG_ARCH_ORION5X) := orion5x
machine-$(CONFIG_ARCH_PICOXCELL) := picoxcell
machine-$(CONFIG_ARCH_PNX4008) := pnx4008
......@@ -188,6 +186,8 @@ machine-$(CONFIG_ARCH_VEXPRESS) := vexpress
machine-$(CONFIG_ARCH_VT8500) := vt8500
machine-$(CONFIG_ARCH_W90X900) := w90x900
machine-$(CONFIG_FOOTBRIDGE) := footbridge
machine-$(CONFIG_MACH_SPEAR1310) := spear13xx
machine-$(CONFIG_MACH_SPEAR1340) := spear13xx
machine-$(CONFIG_MACH_SPEAR300) := spear3xx
machine-$(CONFIG_MACH_SPEAR310) := spear3xx
machine-$(CONFIG_MACH_SPEAR320) := spear3xx
......@@ -205,7 +205,7 @@ plat-$(CONFIG_PLAT_NOMADIK) := nomadik
plat-$(CONFIG_PLAT_ORION) := orion
plat-$(CONFIG_PLAT_PXA) := pxa
plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx samsung
plat-$(CONFIG_PLAT_S5P) := s5p samsung
plat-$(CONFIG_PLAT_S5P) := samsung
plat-$(CONFIG_PLAT_SPEAR) := spear
plat-$(CONFIG_PLAT_VERSATILE) := versatile
......
arch/arm/boot/dts/exynos5250-smdk5250.dts
View file @ c2e1ff39
......@@ -23,4 +23,52 @@ memory {
chosen {
bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
};
i2c@12C60000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <20000>;
gpios = <&gpb3 0 2 3 0>,
<&gpb3 1 2 3 0>;
eeprom@50 {
compatible = "samsung,s524ad0xd1";
reg = <0x50>;
};
};
i2c@12C70000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <20000>;
gpios = <&gpb3 2 2 3 0>,
<&gpb3 3 2 3 0>;
eeprom@51 {
compatible = "samsung,s524ad0xd1";
reg = <0x51>;
};
};
i2c@12C80000 {
status = "disabled";
};
i2c@12C90000 {
status = "disabled";
};
i2c@12CA0000 {
status = "disabled";
};
i2c@12CB0000 {
status = "disabled";
};
i2c@12CC0000 {
status = "disabled";
};
i2c@12CD0000 {
status = "disabled";
};
};
arch/arm/boot/dts/exynos5250.dtsi
View file @ c2e1ff39
......@@ -23,11 +23,11 @@ / {
compatible = "samsung,exynos5250";
interrupt-parent = <&gic>;
gic:interrupt-controller@10490000 {
gic:interrupt-controller@10481000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x10490000 0x1000>, <0x10480000 0x100>;
reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
};
watchdog {
......@@ -42,30 +42,6 @@ rtc {
interrupts = <0 43 0>, <0 44 0>;
};
sdhci@12200000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12200000 0x100>;
interrupts = <0 75 0>;
};
sdhci@12210000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12210000 0x100>;
interrupts = <0 76 0>;
};
sdhci@12220000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12220000 0x100>;
interrupts = <0 77 0>;
};
sdhci@12230000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12230000 0x100>;
interrupts = <0 78 0>;
};
serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
......@@ -94,48 +70,64 @@ i2c@12C60000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C60000 0x100>;
interrupts = <0 56 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12C70000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C70000 0x100>;
interrupts = <0 57 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12C80000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C80000 0x100>;
interrupts = <0 58 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12C90000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C90000 0x100>;
interrupts = <0 59 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12CA0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CA0000 0x100>;
interrupts = <0 60 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12CB0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CB0000 0x100>;
interrupts = <0 61 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12CC0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CC0000 0x100>;
interrupts = <0 62 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12CD0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CD0000 0x100>;
interrupts = <0 63 0>;
#address-cells = <1>;
#size-cells = <0>;
};
amba {
......@@ -157,13 +149,13 @@ pdma1: pdma@121B0000 {
interrupts = <0 35 0>;
};
mdma0: pdma@10800000 {
mdma0: mdma@10800000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
interrupts = <0 33 0>;
};
mdma1: pdma@11C10000 {
mdma1: mdma@11C10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
interrupts = <0 124 0>;
......@@ -242,6 +234,12 @@ gpc3: gpio-controller@11400140 {
#gpio-cells = <4>;
};
gpc4: gpio-controller@114002E0 {
compatible = "samsung,exynos4-gpio";
reg = <0x114002E0 0x20>;
#gpio-cells = <4>;
};
gpd0: gpio-controller@11400160 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400160 0x20>;
......@@ -388,19 +386,19 @@ gpv1: gpio-controller@10D10020 {
gpv2: gpio-controller@10D10040 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10040 0x20>;
reg = <0x10D10060 0x20>;
#gpio-cells = <4>;
};
gpv3: gpio-controller@10D10060 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10060 0x20>;
reg = <0x10D10080 0x20>;
#gpio-cells = <4>;
};
gpv4: gpio-controller@10D10080 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10080 0x20>;
reg = <0x10D100C0 0x20>;
#gpio-cells = <4>;
};
......
arch/arm/boot/dts/imx23-evk.dts 0 → 100644
View file @ c2e1ff39
/*
* Copyright 2012 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "imx23.dtsi"
/ {
model = "Freescale i.MX23 Evaluation Kit";
compatible = "fsl,imx23-evk", "fsl,imx23";
memory {
reg = <0x40000000 0x08000000>;
};
apb@80000000 {
apbh@80000000 {
ssp0: ssp@80010000 {
compatible = "fsl,imx23-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_8bit_pins_a &mmc0_pins_fixup>;
bus-width = <8>;
wp-gpios = <&gpio1 30 0>;
status = "okay";
};
};
apbx@80040000 {
duart: serial@80070000 {
pinctrl-names = "default";
pinctrl-0 = <&duart_pins_a>;
status = "okay";
};
};
};
};
arch/arm/boot/dts/imx23.dtsi 0 → 100644
View file @ c2e1ff39
/*
* Copyright 2012 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "skeleton.dtsi"
/ {
interrupt-parent = <&icoll>;
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
};
cpus {
cpu@0 {
compatible = "arm,arm926ejs";
};
};
apb@80000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80000000 0x80000>;
ranges;
apbh@80000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80000000 0x40000>;
ranges;
icoll: interrupt-controller@80000000 {
compatible = "fsl,imx23-icoll", "fsl,mxs-icoll";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x80000000 0x2000>;
};
dma-apbh@80004000 {
compatible = "fsl,imx23-dma-apbh";
reg = <0x80004000 2000>;
};
ecc@80008000 {
reg = <0x80008000 2000>;
status = "disabled";
};
bch@8000a000 {
reg = <0x8000a000 2000>;
status = "disabled";
};
gpmi@8000c000 {
reg = <0x8000c000 2000>;
status = "disabled";
};
ssp0: ssp@80010000 {
reg = <0x80010000 2000>;
interrupts = <15 14>;
fsl,ssp-dma-channel = <1>;
status = "disabled";
};
etm@80014000 {
reg = <0x80014000 2000>;
status = "disabled";
};
pinctrl@80018000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx23-pinctrl", "simple-bus";
reg = <0x80018000 2000>;
gpio0: gpio@0 {
compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
interrupts = <16>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@1 {
compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
interrupts = <17>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@2 {
compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
interrupts = <18>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
duart_pins_a: duart@0 {
reg = <0>;
fsl,pinmux-ids = <0x11a2 0x11b2>;
fsl,drive-strength = <0>;
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
mmc0_8bit_pins_a: mmc0-8bit@0 {
reg = <0>;
fsl,pinmux-ids = <0x2020 0x2030 0x2040
0x2050 0x0082 0x0092 0x00a2
0x00b2 0x2000 0x2010 0x2060>;
fsl,drive-strength = <1>;
fsl,voltage = <1>;
fsl,pull-up = <1>;
};
mmc0_pins_fixup: mmc0-pins-fixup {
fsl,pinmux-ids = <0x2010 0x2060>;
fsl,pull-up = <0>;
};
};
digctl@8001c000 {
reg = <0x8001c000 2000>;
status = "disabled";
};
emi@80020000 {
reg = <0x80020000 2000>;
status = "disabled";
};
dma-apbx@80024000 {
compatible = "fsl,imx23-dma-apbx";
reg = <0x80024000 2000>;
};
dcp@80028000 {
reg = <0x80028000 2000>;
status = "disabled";
};
pxp@8002a000 {
reg = <0x8002a000 2000>;
status = "disabled";
};
ocotp@8002c000 {
reg = <0x8002c000 2000>;
status = "disabled";
};
axi-ahb@8002e000 {
reg = <0x8002e000 2000>;
status = "disabled";
};
lcdif@80030000 {
reg = <0x80030000 2000>;
status = "disabled";
};
ssp1: ssp@80034000 {
reg = <0x80034000 2000>;
interrupts = <2 20>;
fsl,ssp-dma-channel = <2>;
status = "disabled";
};
tvenc@80038000 {
reg = <0x80038000 2000>;
status = "disabled";
};
};
apbx@80040000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80040000 0x40000>;
ranges;
clkctl@80040000 {
reg = <0x80040000 2000>;
status = "disabled";
};
saif0: saif@80042000 {
reg = <0x80042000 2000>;
status = "disabled";
};
power@80044000 {
reg = <0x80044000 2000>;
status = "disabled";
};
saif1: saif@80046000 {
reg = <0x80046000 2000>;
status = "disabled";
};
audio-out@80048000 {
reg = <0x80048000 2000>;
status = "disabled";
};
audio-in@8004c000 {
reg = <0x8004c000 2000>;
status = "disabled";
};
lradc@80050000 {
reg = <0x80050000 2000>;
status = "disabled";
};
spdif@80054000 {
reg = <0x80054000 2000>;
status = "disabled";
};
i2c@80058000 {
reg = <0x80058000 2000>;
status = "disabled";
};
rtc@8005c000 {
reg = <0x8005c000 2000>;
status = "disabled";
};
pwm@80064000 {
reg = <0x80064000 2000>;
status = "disabled";
};
timrot@80068000 {
reg = <0x80068000 2000>;
status = "disabled";
};
auart0: serial@8006c000 {
reg = <0x8006c000 0x2000>;
status = "disabled";
};
auart1: serial@8006e000 {
reg = <0x8006e000 0x2000>;
status = "disabled";
};
duart: serial@80070000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x80070000 0x2000>;
interrupts = <0>;
status = "disabled";
};
usbphy@8007c000 {
reg = <0x8007c000 0x2000>;
status = "disabled";
};
};
};
ahb@80080000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80080000 0x80000>;
ranges;
usbctrl@80080000 {
reg = <0x80080000 0x10000>;
status = "disabled";
};
};
};
arch/arm/boot/dts/imx27-phytec-phycore.dts
View file @ c2e1ff39
......@@ -27,22 +27,22 @@ wdog@10002000 {
status = "okay";
};
uart@1000a000 {
serial@1000a000 {
fsl,uart-has-rtscts;
status = "okay";
};
uart@1000b000 {
serial@1000b000 {
fsl,uart-has-rtscts;
status = "okay";
};
uart@1000c000 {
serial@1000c000 {
fsl,uart-has-rtscts;
status = "okay";
};
fec@1002b000 {
ethernet@1002b000 {
status = "okay";
};
......
arch/arm/boot/dts/imx27.dtsi
View file @ c2e1ff39
......@@ -59,28 +59,28 @@ wdog@10002000 {
status = "disabled";
};
uart1: uart@1000a000 {
uart1: serial@1000a000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000a000 0x1000>;
interrupts = <20>;
status = "disabled";
};
uart2: uart@1000b000 {
uart2: serial@1000b000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000b000 0x1000>;
interrupts = <19>;
status = "disabled";
};
uart3: uart@1000c000 {
uart3: serial@1000c000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000c000 0x1000>;
interrupts = <18>;
status = "disabled";
};
uart4: uart@1000d000 {
uart4: serial@1000d000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000d000 0x1000>;
interrupts = <17>;
......@@ -183,14 +183,14 @@ cspi3: cspi@10017000 {
status = "disabled";
};
uart5: uart@1001b000 {
uart5: serial@1001b000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1001b000 0x1000>;
interrupts = <49>;
status = "disabled";
};
uart6: uart@1001c000 {
uart6: serial@1001c000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1001c000 0x1000>;
interrupts = <48>;
......@@ -206,7 +206,7 @@ i2c2: i2c@1001d000 {
status = "disabled";
};
fec: fec@1002b000 {
fec: ethernet@1002b000 {
compatible = "fsl,imx27-fec";
reg = <0x1002b000 0x4000>;
interrupts = <50>;
......
arch/arm/boot/dts/imx28-evk.dts 0 → 100644
View file @ c2e1ff39
/*
* Copyright 2012 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "imx28.dtsi"
/ {
model = "Freescale i.MX28 Evaluation Kit";
compatible = "fsl,imx28-evk", "fsl,imx28";
memory {
reg = <0x40000000 0x08000000>;
};
apb@80000000 {
apbh@80000000 {
ssp0: ssp@80010000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_8bit_pins_a
&mmc0_cd_cfg &mmc0_sck_cfg>;
bus-width = <8>;
wp-gpios = <&gpio2 12 0>;
status = "okay";
};
ssp1: ssp@80012000 {
compatible = "fsl,imx28-mmc";
bus-width = <8>;
wp-gpios = <&gpio0 28 0>;
status = "okay";
};
};
apbx@80040000 {
saif0: saif@80042000 {
pinctrl-names = "default";
pinctrl-0 = <&saif0_pins_a>;
status = "okay";
};
saif1: saif@80046000 {
pinctrl-names = "default";
pinctrl-0 = <&saif1_pins_a>;
fsl,saif-master = <&saif0>;
status = "okay";
};
i2c0: i2c@80058000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
};
};
duart: serial@80074000 {
pinctrl-names = "default";
pinctrl-0 = <&duart_pins_a>;
status = "okay";
};
};
};
ahb@80080000 {
mac0: ethernet@800f0000 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
status = "okay";
};
mac1: ethernet@800f4000 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac1_pins_a>;
status = "okay";
};
};
regulators {
compatible = "simple-bus";
reg_3p3v: 3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
sound {
compatible = "fsl,imx28-evk-sgtl5000",
"fsl,mxs-audio-sgtl5000";
model = "imx28-evk-sgtl5000";
saif-controllers = <&saif0 &saif1>;
audio-codec = <&sgtl5000>;
};
};
arch/arm/boot/dts/imx28.dtsi 0 → 100644
View file @ c2e1ff39
This diff is collapsed.
arch/arm/boot/dts/imx51-babbage.dts
View file @ c2e1ff39
......@@ -17,10 +17,6 @@ / {
model = "Freescale i.MX51 Babbage Board";
compatible = "fsl,imx51-babbage", "fsl,imx51";
chosen {
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
};
memory {
reg = <0x90000000 0x20000000>;
};
......@@ -40,7 +36,7 @@ esdhc@70008000 { /* ESDHC2 */
status = "okay";
};
uart3: uart@7000c000 {
uart3: serial@7000c000 {
fsl,uart-has-rtscts;
status = "okay";
};
......@@ -166,6 +162,11 @@ partition@40000 {
};
};
};
ssi2: ssi@70014000 {
fsl,mode = "i2s-slave";
status = "okay";
};
};
wdog@73f98000 { /* WDOG1 */
......@@ -177,12 +178,12 @@ iomuxc@73fa8000 {
reg = <0x73fa8000 0x4000>;
};
uart1: uart@73fbc000 {
uart1: serial@73fbc000 {
fsl,uart-has-rtscts;
status = "okay";
};
uart2: uart@73fc0000 {
uart2: serial@73fc0000 {
status = "okay";
};
};
......@@ -195,13 +196,20 @@ sdma@83fb0000 {
i2c@83fc4000 { /* I2C2 */
status = "okay";
codec: sgtl5000@0a {
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clock-frequency = <26000000>;
VDDA-supply = <&vdig_reg>;
VDDIO-supply = <&vvideo_reg>;
};
};
fec@83fec000 {
audmux@83fd0000 {
status = "okay";
};
ethernet@83fec000 {
phy-mode = "mii";
status = "okay";
};
......@@ -218,4 +226,18 @@ power {
gpio-key,wakeup;
};
};
sound {
compatible = "fsl,imx51-babbage-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx51-babbage-sgtl5000";
ssi-controller = <&ssi2>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <2>;
mux-ext-port = <3>;
};
};
arch/arm/boot/dts/imx51.dtsi
View file @ c2e1ff39
......@@ -86,7 +86,7 @@ esdhc@70008000 { /* ESDHC2 */
status = "disabled";
};
uart3: uart@7000c000 {
uart3: serial@7000c000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x7000c000 0x4000>;
interrupts = <33>;
......@@ -102,6 +102,15 @@ ecspi@70010000 { /* ECSPI1 */
status = "disabled";
};
ssi2: ssi@70014000 {
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x70014000 0x4000>;
interrupts = <30>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
};
esdhc@70020000 { /* ESDHC3 */
compatible = "fsl,imx51-esdhc";
reg = <0x70020000 0x4000>;
......@@ -171,14 +180,14 @@ wdog@73f9c000 { /* WDOG2 */
status = "disabled";
};
uart1: uart@73fbc000 {
uart1: serial@73fbc000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fbc000 0x4000>;
interrupts = <31>;
status = "disabled";
};
uart2: uart@73fc0000 {
uart2: serial@73fc0000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fc0000 0x4000>;
interrupts = <32>;
......@@ -235,7 +244,31 @@ i2c@83fc8000 { /* I2C1 */
status = "disabled";
};
fec@83fec000 {
ssi1: ssi@83fcc000 {
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x83fcc000 0x4000>;
interrupts = <29>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
};
audmux@83fd0000 {
compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
reg = <0x83fd0000 0x4000>;
status = "disabled";
};
ssi3: ssi@83fe8000 {
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x83fe8000 0x4000>;
interrupts = <96>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
};
ethernet@83fec000 {
compatible = "fsl,imx51-fec", "fsl,imx27-fec";
reg = <0x83fec000 0x4000>;
interrupts = <87>;
......
arch/arm/boot/dts/imx53-ard.dts
View file @ c2e1ff39
......@@ -17,10 +17,6 @@ / {
model = "Freescale i.MX53 Automotive Reference Design Board";
compatible = "fsl,imx53-ard", "fsl,imx53";
chosen {
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
};
memory {
reg = <0x70000000 0x40000000>;
};
......@@ -44,7 +40,7 @@ iomuxc@53fa8000 {
reg = <0x53fa8000 0x4000>;
};
uart1: uart@53fbc000 {
uart1: serial@53fbc000 {
status = "okay";
};
};
......
arch/arm/boot/dts/imx53-evk.dts
View file @ c2e1ff39
......@@ -17,10 +17,6 @@ / {
model = "Freescale i.MX53 Evaluation Kit";
compatible = "fsl,imx53-evk", "fsl,imx53";
chosen {
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
};
memory {
reg = <0x70000000 0x80000000>;
};
......@@ -75,7 +71,7 @@ iomuxc@53fa8000 {
reg = <0x53fa8000 0x4000>;
};
uart1: uart@53fbc000 {
uart1: serial@53fbc000 {
status = "okay";
};
};
......@@ -99,7 +95,7 @@ codec: sgtl5000@0a {
};
};
fec@63fec000 {
ethernet@63fec000 {
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
......
arch/arm/boot/dts/imx53-qsb.dts
View file @ c2e1ff39
......@@ -17,10 +17,6 @@ / {
model = "Freescale i.MX53 Quick Start Board";
compatible = "fsl,imx53-qsb", "fsl,imx53";
chosen {
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
};
memory {
reg = <0x70000000 0x40000000>;
};
......@@ -33,6 +29,11 @@ esdhc@50004000 { /* ESDHC1 */
status = "okay";
};
ssi2: ssi@50014000 {
fsl,mode = "i2s-slave";
status = "okay";
};
esdhc@50020000 { /* ESDHC3 */
cd-gpios = <&gpio3 11 0>;
wp-gpios = <&gpio3 12 0>;
......@@ -49,7 +50,7 @@ iomuxc@53fa8000 {
reg = <0x53fa8000 0x4000>;
};
uart1: uart@53fbc000 {
uart1: serial@53fbc000 {
status = "okay";
};
};
......@@ -62,9 +63,11 @@ sdma@63fb0000 {
i2c@63fc4000 { /* I2C2 */
status = "okay";
codec: sgtl5000@0a {
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
VDDA-supply = <&reg_3p2v>;
VDDIO-supply = <&reg_3p2v>;
};
};
......@@ -77,12 +80,88 @@ accelerometer: mma8450@1c {
};
pmic: dialog@48 {
compatible = "dialog,da9053", "dialog,da9052";
compatible = "dlg,da9053-aa", "dlg,da9052";
reg = <0x48>;
regulators {
buck0 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2075000>;
};
buck1 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2075000>;
};
buck2 {
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <2500000>;
};
buck3 {
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <2500000>;
};
ldo4 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1800000>;
};
ldo5 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1800000>;
};
ldo6 {
regulator-min-microvolt = <1725000>;
regulator-max-microvolt = <3300000>;
};
ldo7 {
regulator-min-microvolt = <1725000>;
regulator-max-microvolt = <3300000>;
};
ldo8 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
};
ldo9 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
};
ldo10 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
};
ldo11 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
};
ldo12 {
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <3650000>;
};
ldo13 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
};
};
};
};
fec@63fec000 {
audmux@63fd0000 {
status = "okay";
};
ethernet@63fec000 {
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
......@@ -122,4 +201,30 @@ user {
linux,default-trigger = "heartbeat";
};
};
regulators {
compatible = "simple-bus";
reg_3p2v: 3p2v {
compatible = "regulator-fixed";
regulator-name = "3P2V";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
};
sound {
compatible = "fsl,imx53-qsb-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx53-qsb-sgtl5000";
ssi-controller = <&ssi2>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <2>;
mux-ext-port = <5>;
};
};
arch/arm/boot/dts/imx53-smd.dts
View file @ c2e1ff39
......@@ -17,10 +17,6 @@ / {
model = "Freescale i.MX53 Smart Mobile Reference Design Board";
compatible = "fsl,imx53-smd", "fsl,imx53";
chosen {
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
};
memory {
reg = <0x70000000 0x40000000>;
};
......@@ -35,11 +31,11 @@ esdhc@50004000 { /* ESDHC1 */
};
esdhc@50008000 { /* ESDHC2 */
fsl,card-wired;
non-removable;
status = "okay";
};
uart3: uart@5000c000 {
uart3: serial@5000c000 {
fsl,uart-has-rtscts;
status = "okay";
};
......@@ -76,7 +72,7 @@ partition@40000 {
};
esdhc@50020000 { /* ESDHC3 */
fsl,card-wired;
non-removable;
status = "okay";
};
};
......@@ -90,11 +86,11 @@ iomuxc@53fa8000 {
reg = <0x53fa8000 0x4000>;
};
uart1: uart@53fbc000 {
uart1: serial@53fbc000 {
status = "okay";
};
uart2: uart@53fc0000 {
uart2: serial@53fc0000 {
status = "okay";
};
};
......@@ -142,7 +138,7 @@ pmic: dialog@48 {
};
};
fec@63fec000 {
ethernet@63fec000 {
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
......
arch/arm/boot/dts/imx53.dtsi
View file @ c2e1ff39
......@@ -88,7 +88,7 @@ esdhc@50008000 { /* ESDHC2 */
status = "disabled";
};
uart3: uart@5000c000 {
uart3: serial@5000c000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x5000c000 0x4000>;
interrupts = <33>;
......@@ -104,6 +104,15 @@ ecspi@50010000 { /* ECSPI1 */
status = "disabled";
};
ssi2: ssi@50014000 {
compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
reg = <0x50014000 0x4000>;
interrupts = <30>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
};
esdhc@50020000 { /* ESDHC3 */
compatible = "fsl,imx53-esdhc";
reg = <0x50020000 0x4000>;
......@@ -173,14 +182,14 @@ wdog@53f9c000 { /* WDOG2 */
status = "disabled";
};
uart1: uart@53fbc000 {
uart1: serial@53fbc000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53fbc000 0x4000>;
interrupts = <31>;
status = "disabled";
};
uart2: uart@53fc0000 {
uart2: serial@53fc0000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53fc0000 0x4000>;
interrupts = <32>;
......@@ -226,7 +235,7 @@ i2c@53fec000 { /* I2C3 */
status = "disabled";
};
uart4: uart@53ff0000 {
uart4: serial@53ff0000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53ff0000 0x4000>;
interrupts = <13>;
......@@ -241,7 +250,7 @@ aips@60000000 { /* AIPS2 */
reg = <0x60000000 0x10000000>;
ranges;
uart5: uart@63f90000 {
uart5: serial@63f90000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x63f90000 0x4000>;
interrupts = <86>;
......@@ -290,7 +299,31 @@ i2c@63fc8000 { /* I2C1 */
status = "disabled";
};
fec@63fec000 {
ssi1: ssi@63fcc000 {
compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
reg = <0x63fcc000 0x4000>;
interrupts = <29>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
};
audmux@63fd0000 {
compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
reg = <0x63fd0000 0x4000>;
status = "disabled";
};
ssi3: ssi@63fe8000 {
compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
reg = <0x63fe8000 0x4000>;
interrupts = <96>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
};
ethernet@63fec000 {
compatible = "fsl,imx53-fec", "fsl,imx25-fec";
reg = <0x63fec000 0x4000>;
interrupts = <87>;
......
arch/arm/boot/dts/imx6q-arm2.dts
View file @ c2e1ff39
......@@ -17,19 +17,14 @@ / {
model = "Freescale i.MX6 Quad Armadillo2 Board";
compatible = "fsl,imx6q-arm2", "fsl,imx6q";
chosen {
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait";
};
memory {
reg = <0x10000000 0x80000000>;
};
soc {
aips-bus@02100000 { /* AIPS2 */
enet@02188000 {
ethernet@02188000 {
phy-mode = "rgmii";
local-mac-address = [00 04 9F 01 1B 61];
status = "okay";
};
......@@ -37,16 +32,20 @@ usdhc@02198000 { /* uSDHC3 */
cd-gpios = <&gpio6 11 0>;
wp-gpios = <&gpio6 14 0>;
vmmc-supply = <&reg_3p3v>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1>;
status = "okay";
};
usdhc@0219c000 { /* uSDHC4 */
fsl,card-wired;
non-removable;
vmmc-supply = <&reg_3p3v>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4_1>;
status = "okay";
};
uart4: uart@021f0000 {
uart4: serial@021f0000 {
status = "okay";
};
};
......
arch/arm/boot/dts/imx6q-sabrelite.dts
View file @ c2e1ff39
......@@ -22,8 +22,30 @@ memory {
};
soc {
aips-bus@02000000 { /* AIPS1 */
spba-bus@02000000 {
ecspi@02008000 { /* eCSPI1 */
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
status = "okay";
flash: m25p80@0 {
compatible = "sst,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
ssi1: ssi@02028000 {
fsl,mode = "i2s-slave";
status = "okay";
};
};
};
aips-bus@02100000 { /* AIPS2 */
enet@02188000 {
ethernet@02188000 {
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
status = "okay";
......@@ -43,13 +65,23 @@ usdhc@0219c000 { /* uSDHC4 */
status = "okay";
};
uart2: uart@021e8000 {
audmux@021d8000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
};
uart2: serial@021e8000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial2_1>;
};
i2c@021a0000 { /* I2C1 */
status = "okay";
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
......@@ -80,4 +112,18 @@ reg_3p3v: 3p3v {
regulator-always-on;
};
};
sound {
compatible = "fsl,imx6q-sabrelite-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx6q-sabrelite-sgtl5000";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <4>;
};
};
arch/arm/boot/dts/imx6q-sabresd.dts 0 → 100644
View file @ c2e1ff39
/*
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "imx6q.dtsi"
/ {
model = "Freescale i.MX6Q SABRE Smart Device Board";
compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
memory {
reg = <0x10000000 0x40000000>;
};
soc {
aips-bus@02000000 { /* AIPS1 */
spba-bus@02000000 {
uart1: serial@02020000 {
status = "okay";
};
};
};
aips-bus@02100000 { /* AIPS2 */
ethernet@02188000 {
phy-mode = "rgmii";
status = "okay";
};
usdhc@02194000 { /* uSDHC2 */
cd-gpios = <&gpio2 2 0>;
wp-gpios = <&gpio2 3 0>;
status = "okay";
};
usdhc@02198000 { /* uSDHC3 */
cd-gpios = <&gpio2 0 0>;
wp-gpios = <&gpio2 1 0>;
status = "okay";
};
};
};
};
arch/arm/boot/dts/imx6q.dtsi
View file @ c2e1ff39
......@@ -165,7 +165,7 @@ ecspi@02018000 { /* eCSPI5 */
status = "disabled";
};
uart1: uart@02020000 {
uart1: serial@02020000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 0x04>;
......@@ -177,19 +177,31 @@ esai@02024000 {
interrupts = <0 51 0x04>;
};
ssi@02028000 { /* SSI1 */
ssi1: ssi@02028000 {
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
reg = <0x02028000 0x4000>;
interrupts = <0 46 0x04>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <38 37>;
status = "disabled";
};
ssi@0202c000 { /* SSI2 */
ssi2: ssi@0202c000 {
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
reg = <0x0202c000 0x4000>;
interrupts = <0 47 0x04>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <42 41>;
status = "disabled";
};
ssi@02030000 { /* SSI3 */
ssi3: ssi@02030000 {
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
reg = <0x02030000 0x4000>;
interrupts = <0 48 0x04>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <46 45>;
status = "disabled";
};
asrc@02034000 {
......@@ -346,6 +358,90 @@ anatop@020c8000 {
compatible = "fsl,imx6q-anatop";
reg = <0x020c8000 0x1000>;
interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
regulator-1p1@110 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1375000>;
regulator-always-on;
anatop-reg-offset = <0x110>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <4>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1375000>;
};
regulator-3p0@120 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3150000>;
regulator-always-on;
anatop-reg-offset = <0x120>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
};
regulator-2p5@130 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2750000>;
regulator-always-on;
anatop-reg-offset = <0x130>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <0>;
anatop-min-voltage = <2000000>;
anatop-max-voltage = <2750000>;
};
regulator-vddcore@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "cpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <0>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
regulator-vddpu@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <9>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
regulator-vddsoc@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <18>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
};
usbphy@020c9000 { /* USBPHY1 */
......@@ -386,7 +482,62 @@ gpc@020dc000 {
};
iomuxc@020e0000 {
compatible = "fsl,imx6q-iomuxc";
reg = <0x020e0000 0x4000>;
/* shared pinctrl settings */
audmux {
pinctrl_audmux_1: audmux-1 {
fsl,pins = <18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
3 0x80000000>; /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
};
};
i2c1 {
pinctrl_i2c1_1: i2c1grp-1 {
fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
196 0x4001b8b1>; /* MX6Q_PAD_EIM_D28__I2C1_SDA */
};
};
serial2 {
pinctrl_serial2_1: serial2grp-1 {
fsl,pins = <183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
191 0x1b0b1>; /* MX6Q_PAD_EIM_D27__UART2_RXD */
};
};
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
1241 0x17059>; /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
};
};
usdhc4 {
pinctrl_usdhc4_1: usdhc4grp-1 {
fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
};
};
};
dcic@020e4000 { /* DCIC1 */
......@@ -422,7 +573,7 @@ aipstz@0217c000 { /* AIPSTZ2 */
reg = <0x0217c000 0x4000>;
};
enet@02188000 {
ethernet@02188000 {
compatible = "fsl,imx6q-fec";
reg = <0x02188000 0x4000>;
interrupts = <0 118 0x04 0 119 0x04>;
......@@ -527,7 +678,9 @@ tzasc@021d4000 { /* TZASC2 */
};
audmux@021d8000 {
compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
reg = <0x021d8000 0x4000>;
status = "disabled";
};
mipi@021dc000 { /* MIPI-CSI */
......@@ -543,28 +696,28 @@ vdoa@021e4000 {
interrupts = <0 18 0x04>;
};
uart2: uart@021e8000 {
uart2: serial@021e8000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021e8000 0x4000>;
interrupts = <0 27 0x04>;
status = "disabled";
};
uart3: uart@021ec000 {
uart3: serial@021ec000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021ec000 0x4000>;
interrupts = <0 28 0x04>;
status = "disabled";
};
uart4: uart@021f0000 {
uart4: serial@021f0000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f0000 0x4000>;
interrupts = <0 29 0x04>;
status = "disabled";
};
uart5: uart@021f4000 {
uart5: serial@021f4000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f4000 0x4000>;
interrupts = <0 30 0x04>;
......
arch/arm/boot/dts/omap3-beagle.dts
View file @ c2e1ff39
......@@ -57,7 +57,7 @@ eeprom@50 {
&mmc1 {
vmmc-supply = <&vmmc1>;
vmmc_aux-supply = <&vsim>;
ti,bus-width = <8>;
bus-width = <8>;
};
&mmc2 {
......
arch/arm/boot/dts/omap4-panda.dts
View file @ c2e1ff39
......@@ -70,7 +70,7 @@ &i2c4 {
&mmc1 {
vmmc-supply = <&vmmc>;
ti,bus-width = <8>;
bus-width = <8>;
};
&mmc2 {
......@@ -87,5 +87,5 @@ &mmc4 {
&mmc5 {
ti,non-removable;
ti,bus-width = <4>;
bus-width = <4>;
};
arch/arm/boot/dts/omap4-sdp.dts
View file @ c2e1ff39
......@@ -137,12 +137,12 @@ eth@0 {
&mmc1 {
vmmc-supply = <&vmmc>;
ti,bus-width = <8>;
bus-width = <8>;
};
&mmc2 {
vmmc-supply = <&vaux1>;
ti,bus-width = <8>;
bus-width = <8>;
ti,non-removable;
};
......@@ -155,6 +155,6 @@ &mmc4 {
};
&mmc5 {
ti,bus-width = <4>;
bus-width = <4>;
ti,non-removable;
};
arch/arm/boot/dts/spear1310-evb.dts 0 → 100644
View file @ c2e1ff39
/*
* DTS file for SPEAr1310 Evaluation Baord
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "spear1310.dtsi"
/ {
model = "ST SPEAr1310 Evaluation Board";
compatible = "st,spear1310-evb", "st,spear1310";
#address-cells = <1>;
#size-cells = <1>;
memory {
reg = <0 0x40000000>;
};
ahb {
pinmux@e0700000 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
i2c0-pmx {
st,pins = "i2c0_grp";
st,function = "i2c0";
};
i2s1 {
st,pins = "i2s1_grp";
st,function = "i2s1";
};
gpio {
st,pins = "arm_gpio_grp";
st,function = "arm_gpio";
};
eth {
st,pins = "gmii_grp";
st,function = "gmii";
};
ssp0 {
st,pins = "ssp0_grp";
st,function = "ssp0";
};
kbd {
st,pins = "keyboard_6x6_grp";
st,function = "keyboard";
};
sdhci {
st,pins = "sdhci_grp";
st,function = "sdhci";
};
smi-pmx {
st,pins = "smi_2_chips_grp";
st,function = "smi";
};
uart0 {
st,pins = "uart0_grp";
st,function = "uart0";
};
rs485 {
st,pins = "rs485_0_1_tdm_0_1_grp";
st,function = "rs485_0_1_tdm_0_1";
};
i2c1_2 {
st,pins = "i2c_1_2_grp";
st,function = "i2c_1_2";
};
pci {
st,pins = "pcie0_grp","pcie1_grp",
"pcie2_grp";
st,function = "pci";
};
smii {
st,pins = "smii_0_1_2_grp";
st,function = "smii_0_1_2";
};
nand {
st,pins = "nand_8bit_grp",
"nand_16bit_grp";
st,function = "nand";
};
};
};
ahci@b1000000 {
status = "okay";
};
cf@b2800000 {
status = "okay";
};
dma@ea800000 {
status = "okay";
};
dma@eb000000 {
status = "okay";
};
fsmc: flash@b0000000 {
status = "okay";
};
gmac0: eth@e2000000 {
status = "okay";
};
sdhci@b3000000 {
status = "okay";
};
smi: flash@ea000000 {
status = "okay";
clock-rate=<50000000>;
flash@e6000000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xe6000000 0x800000>;
st,smi-fast-mode;
partition@0 {
label = "xloader";
reg = <0x0 0x10000>;
};
partition@10000 {
label = "u-boot";
reg = <0x10000 0x40000>;
};
partition@50000 {
label = "linux";
reg = <0x50000 0x2c0000>;
};
partition@310000 {
label = "rootfs";
reg = <0x310000 0x4f0000>;
};
};
};
spi0: spi@e0100000 {
status = "okay";
};
ehci@e4800000 {
status = "okay";
};
ehci@e5800000 {
status = "okay";
};
ohci@e4000000 {
status = "okay";
};
ohci@e5000000 {
status = "okay";
};
apb {
adc@e0080000 {
status = "okay";
};
gpio0: gpio@e0600000 {
status = "okay";
};
gpio1: gpio@e0680000 {
status = "okay";
};
i2c0: i2c@e0280000 {
status = "okay";
};
i2c1: i2c@5cd00000 {
status = "okay";
};
kbd@e0300000 {
linux,keymap = < 0x00000001
0x00010002
0x00020003
0x00030004
0x00040005
0x00050006
0x00060007
0x00070008
0x00080009
0x0100000a
0x0101000c
0x0102000d
0x0103000e
0x0104000f
0x01050010
0x01060011
0x01070012
0x01080013
0x02000014
0x02010015
0x02020016
0x02030017
0x02040018
0x02050019
0x0206001a
0x0207001b
0x0208001c
0x0300001d
0x0301001e
0x0302001f
0x03030020
0x03040021
0x03050022
0x03060023
0x03070024
0x03080025
0x04000026
0x04010027
0x04020028
0x04030029
0x0404002a
0x0405002b
0x0406002c
0x0407002d
0x0408002e
0x0500002f
0x05010030
0x05020031
0x05030032
0x05040033
0x05050034
0x05060035
0x05070036
0x05080037
0x06000038
0x06010039
0x0602003a
0x0603003b
0x0604003c
0x0605003d
0x0606003e
0x0607003f
0x06080040
0x07000041
0x07010042
0x07020043
0x07030044
0x07040045
0x07050046
0x07060047
0x07070048
0x07080049
0x0800004a
0x0801004b
0x0802004c
0x0803004d
0x0804004e
0x0805004f
0x08060050
0x08070051
0x08080052 >;
autorepeat;
st,mode = <0>;
status = "okay";
};
rtc@e0580000 {
status = "okay";
};
serial@e0000000 {
status = "okay";
};
wdt@ec800620 {
status = "okay";
};
};
};
};
arch/arm/boot/dts/spear1310.dtsi 0 → 100644
View file @ c2e1ff39
/*
* DTS file for all SPEAr1310 SoCs
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "spear13xx.dtsi"
/ {
compatible = "st,spear1310";
ahb {
ahci@b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 68 0x4>;
status = "disabled";
};
ahci@b1800000 {
compatible = "snps,spear-ahci";
reg = <0xb1800000 0x10000>;
interrupts = <0 69 0x4>;
status = "disabled";
};
ahci@b4000000 {
compatible = "snps,spear-ahci";
reg = <0xb4000000 0x10000>;
interrupts = <0 70 0x4>;
status = "disabled";
};
gmac1: eth@5c400000 {
compatible = "st,spear600-gmac";
reg = <0x5c400000 0x8000>;
interrupts = <0 95 0x4>;
interrupt-names = "macirq";
status = "disabled";
};
gmac2: eth@5c500000 {
compatible = "st,spear600-gmac";
reg = <0x5c500000 0x8000>;
interrupts = <0 96 0x4>;
interrupt-names = "macirq";
status = "disabled";
};
gmac3: eth@5c600000 {
compatible = "st,spear600-gmac";
reg = <0x5c600000 0x8000>;
interrupts = <0 97 0x4>;
interrupt-names = "macirq";
status = "disabled";
};
gmac4: eth@5c700000 {
compatible = "st,spear600-gmac";
reg = <0x5c700000 0x8000>;
interrupts = <0 98 0x4>;
interrupt-names = "macirq";
status = "disabled";
};
spi1: spi@5d400000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x5d400000 0x1000>;
interrupts = <0 99 0x4>;
status = "disabled";
};
apb {
i2c1: i2c@5cd00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5cd00000 0x1000>;
interrupts = <0 87 0x4>;
status = "disabled";
};
i2c2: i2c@5ce00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5ce00000 0x1000>;
interrupts = <0 88 0x4>;
status = "disabled";
};
i2c3: i2c@5cf00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5cf00000 0x1000>;
interrupts = <0 89 0x4>;
status = "disabled";
};
i2c4: i2c@5d000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5d000000 0x1000>;
interrupts = <0 90 0x4>;
status = "disabled";
};
i2c5: i2c@5d100000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5d100000 0x1000>;
interrupts = <0 91 0x4>;
status = "disabled";
};
i2c6: i2c@5d200000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5d200000 0x1000>;
interrupts = <0 92 0x4>;
status = "disabled";
};
i2c7: i2c@5d300000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x5d300000 0x1000>;
interrupts = <0 93 0x4>;
status = "disabled";
};
serial@5c800000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x5c800000 0x1000>;
interrupts = <0 82 0x4>;
status = "disabled";
};
serial@5c900000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x5c900000 0x1000>;
interrupts = <0 83 0x4>;
status = "disabled";
};
serial@5ca00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x5ca00000 0x1000>;
interrupts = <0 84 0x4>;
status = "disabled";
};
serial@5cb00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x5cb00000 0x1000>;
interrupts = <0 85 0x4>;
status = "disabled";
};
serial@5cc00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x5cc00000 0x1000>;
interrupts = <0 86 0x4>;
status = "disabled";
};
thermal@e07008c4 {
st,thermal-flags = <0x7000>;
};
};
};
};
arch/arm/boot/dts/spear1340-evb.dts 0 → 100644
View file @ c2e1ff39
/*
* DTS file for SPEAr1340 Evaluation Baord
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "spear1340.dtsi"
/ {
model = "ST SPEAr1340 Evaluation Board";
compatible = "st,spear1340-evb", "st,spear1340";
#address-cells = <1>;
#size-cells = <1>;
memory {
reg = <0 0x40000000>;
};
ahb {
pinmux@e0700000 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
pads_as_gpio {
st,pins = "pads_as_gpio_grp";
st,function = "pads_as_gpio";
};
fsmc {
st,pins = "fsmc_8bit_grp";
st,function = "fsmc";
};
kbd {
st,pins = "keyboard_row_col_grp",
"keyboard_col5_grp";
st,function = "keyboard";
};
uart0 {
st,pins = "uart0_grp", "uart0_enh_grp";
st,function = "uart0";
};
i2c0-pmx {
st,pins = "i2c0_grp";
st,function = "i2c0";
};
i2c1-pmx {
st,pins = "i2c1_grp";
st,function = "i2c1";
};
spdif-in {
st,pins = "spdif_in_grp";
st,function = "spdif_in";
};
spdif-out {
st,pins = "spdif_out_grp";
st,function = "spdif_out";
};
ssp0 {
st,pins = "ssp0_grp", "ssp0_cs1_grp",
"ssp0_cs3_grp";
st,function = "ssp0";
};
pwm {
st,pins = "pwm2_grp", "pwm3_grp";
st,function = "pwm";
};
smi-pmx {
st,pins = "smi_grp";
st,function = "smi";
};
i2s {
st,pins = "i2s_in_grp", "i2s_out_grp";
st,function = "i2s";
};
gmac {
st,pins = "gmii_grp", "rgmii_grp";
st,function = "gmac";
};
cam3 {
st,pins = "cam3_grp";
st,function = "cam3";
};
cec0 {
st,pins = "cec0_grp";
st,function = "cec0";
};
cec1 {
st,pins = "cec1_grp";
st,function = "cec1";
};
sdhci {
st,pins = "sdhci_grp";
st,function = "sdhci";
};
clcd {
st,pins = "clcd_grp";
st,function = "clcd";
};
sata {
st,pins = "sata_grp";
st,function = "sata";
};
};
};
dma@ea800000 {
status = "okay";
};
dma@eb000000 {
status = "okay";
};
fsmc: flash@b0000000 {
status = "okay";
};
gmac0: eth@e2000000 {
status = "okay";
};
sdhci@b3000000 {
status = "okay";
};
smi: flash@ea000000 {
status = "okay";
clock-rate=<50000000>;
flash@e6000000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xe6000000 0x800000>;
st,smi-fast-mode;
partition@0 {
label = "xloader";
reg = <0x0 0x10000>;
};
partition@10000 {
label = "u-boot";
reg = <0x10000 0x40000>;
};
partition@50000 {
label = "linux";
reg = <0x50000 0x2c0000>;
};
partition@310000 {
label = "rootfs";
reg = <0x310000 0x4f0000>;
};
};
};
spi0: spi@e0100000 {
status = "okay";
};
ehci@e4800000 {
status = "okay";
};
ehci@e5800000 {
status = "okay";
};
ohci@e4000000 {
status = "okay";
};
ohci@e5000000 {
status = "okay";
};
apb {
adc@e0080000 {
status = "okay";
};
gpio0: gpio@e0600000 {
status = "okay";
};
gpio1: gpio@e0680000 {
status = "okay";
};
i2c0: i2c@e0280000 {
status = "okay";
};
i2c1: i2c@b4000000 {
status = "okay";
};
kbd@e0300000 {
linux,keymap = < 0x00000001
0x00010002
0x00020003
0x00030004
0x00040005
0x00050006
0x00060007
0x00070008
0x00080009
0x0100000a
0x0101000c
0x0102000d
0x0103000e
0x0104000f
0x01050010
0x01060011
0x01070012
0x01080013
0x02000014
0x02010015
0x02020016
0x02030017
0x02040018
0x02050019
0x0206001a
0x0207001b
0x0208001c
0x0300001d
0x0301001e
0x0302001f
0x03030020
0x03040021
0x03050022
0x03060023
0x03070024
0x03080025
0x04000026
0x04010027
0x04020028
0x04030029
0x0404002a
0x0405002b
0x0406002c
0x0407002d
0x0408002e
0x0500002f
0x05010030
0x05020031
0x05030032
0x05040033
0x05050034
0x05060035
0x05070036
0x05080037
0x06000038
0x06010039
0x0602003a
0x0603003b
0x0604003c
0x0605003d
0x0606003e
0x0607003f
0x06080040
0x07000041
0x07010042
0x07020043
0x07030044
0x07040045
0x07050046
0x07060047
0x07070048
0x07080049
0x0800004a
0x0801004b
0x0802004c
0x0803004d
0x0804004e
0x0805004f
0x08060050
0x08070051
0x08080052 >;
autorepeat;
st,mode = <0>;
status = "okay";
};
rtc@e0580000 {
status = "okay";
};
serial@e0000000 {
status = "okay";
};
serial@b4100000 {
status = "okay";
};
wdt@ec800620 {
status = "okay";
};
};
};
};
arch/arm/boot/dts/spear1340.dtsi 0 → 100644
View file @ c2e1ff39
/*
* DTS file for all SPEAr1340 SoCs
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "spear13xx.dtsi"
/ {
compatible = "st,spear1340";
ahb {
ahci@b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 72 0x4>;
status = "disabled";
};
spi1: spi@5d400000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x5d400000 0x1000>;
interrupts = <0 99 0x4>;
status = "disabled";
};
apb {
i2c1: i2c@b4000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xb4000000 0x1000>;
interrupts = <0 104 0x4>;
status = "disabled";
};
serial@b4100000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb4100000 0x1000>;
interrupts = <0 105 0x4>;
status = "disabled";
};
thermal@e07008c4 {
st,thermal-flags = <0x2a00>;
};
};
};
};
arch/arm/boot/dts/spear13xx.dtsi 0 → 100644
View file @ c2e1ff39
/*
* DTS file for all SPEAr13xx SoCs
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "skeleton.dtsi"
/ {
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
reg = <0>;
next-level-cache = <&L2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
reg = <1>;
next-level-cache = <&L2>;
};
};
gic: interrupt-controller@ec801000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = < 0xec801000 0x1000 >,
< 0xec800100 0x0100 >;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 8 0x04
0 9 0x04>;
};
L2: l2-cache {
compatible = "arm,pl310-cache";
reg = <0xed000000 0x1000>;
cache-unified;
cache-level = <2>;
};
memory {
name = "memory";
device_type = "memory";
reg = <0 0x40000000>;
};
chosen {
bootargs = "console=ttyAMA0,115200";
};
ahb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x50000000 0x50000000 0x10000000
0xb0000000 0xb0000000 0x10000000
0xe0000000 0xe0000000 0x10000000>;
sdhci@b3000000 {
compatible = "st,sdhci-spear";
reg = <0xb3000000 0x100>;
interrupts = <0 28 0x4>;
status = "disabled";
};
cf@b2800000 {
compatible = "arasan,cf-spear1340";
reg = <0xb2800000 0x100>;
interrupts = <0 29 0x4>;
status = "disabled";
};
dma@ea800000 {
compatible = "snps,dma-spear1340";
reg = <0xea800000 0x1000>;
interrupts = <0 19 0x4>;
status = "disabled";
};
dma@eb000000 {
compatible = "snps,dma-spear1340";
reg = <0xeb000000 0x1000>;
interrupts = <0 59 0x4>;
status = "disabled";
};
fsmc: flash@b0000000 {
compatible = "st,spear600-fsmc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb0000000 0x1000 /* FSMC Register */
0xb0800000 0x0010>; /* NAND Base */
reg-names = "fsmc_regs", "nand_data";
interrupts = <0 20 0x4
0 21 0x4
0 22 0x4
0 23 0x4>;
st,ale-off = <0x20000>;
st,cle-off = <0x10000>;
status = "disabled";
};
gmac0: eth@e2000000 {
compatible = "st,spear600-gmac";
reg = <0xe2000000 0x8000>;
interrupts = <0 23 0x4
0 24 0x4>;
interrupt-names = "macirq", "eth_wake_irq";
status = "disabled";
};
smi: flash@ea000000 {
compatible = "st,spear600-smi";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xea000000 0x1000>;
interrupts = <0 30 0x4>;
status = "disabled";
};
spi0: spi@e0100000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xe0100000 0x1000>;
interrupts = <0 31 0x4>;
status = "disabled";
};
ehci@e4800000 {
compatible = "st,spear600-ehci", "usb-ehci";
reg = <0xe4800000 0x1000>;
interrupts = <0 64 0x4>;
status = "disabled";
};
ehci@e5800000 {
compatible = "st,spear600-ehci", "usb-ehci";
reg = <0xe5800000 0x1000>;
interrupts = <0 66 0x4>;
status = "disabled";
};
ohci@e4000000 {
compatible = "st,spear600-ohci", "usb-ohci";
reg = <0xe4000000 0x1000>;
interrupts = <0 65 0x4>;
status = "disabled";
};
ohci@e5000000 {
compatible = "st,spear600-ohci", "usb-ohci";
reg = <0xe5000000 0x1000>;
interrupts = <0 67 0x4>;
status = "disabled";
};
apb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x50000000 0x50000000 0x10000000
0xb0000000 0xb0000000 0x10000000
0xe0000000 0xe0000000 0x10000000>;
gpio0: gpio@e0600000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xe0600000 0x1000>;
interrupts = <0 24 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio1: gpio@e0680000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xe0680000 0x1000>;
interrupts = <0 25 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
kbd@e0300000 {
compatible = "st,spear300-kbd";
reg = <0xe0300000 0x1000>;
status = "disabled";
};
i2c0: i2c@e0280000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xe0280000 0x1000>;
interrupts = <0 41 0x4>;
status = "disabled";
};
rtc@e0580000 {
compatible = "st,spear-rtc";
reg = <0xe0580000 0x1000>;
interrupts = <0 36 0x4>;
status = "disabled";
};
serial@e0000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xe0000000 0x1000>;
interrupts = <0 36 0x4>;
status = "disabled";
};
adc@e0080000 {
compatible = "st,spear600-adc";
reg = <0xe0080000 0x1000>;
interrupts = <0 44 0x4>;
status = "disabled";
};
timer@e0380000 {
compatible = "st,spear-timer";
reg = <0xe0380000 0x400>;
interrupts = <0 37 0x4>;
};
timer@ec800600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xec800600 0x20>;
interrupts = <1 13 0x301>;
};
wdt@ec800620 {
compatible = "arm,cortex-a9-twd-wdt";
reg = <0xec800620 0x20>;
status = "disabled";
};
thermal@e07008c4 {
compatible = "st,thermal-spear1340";
reg = <0xe07008c4 0x4>;
};
};
};
};
arch/arm/boot/dts/spear300-evb.dts
View file @ c2e1ff39
......@@ -87,6 +87,31 @@ sdhci@70000000 {
smi: flash@fc000000 {
status = "okay";
clock-rate=<50000000>;
flash@f8000000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xf8000000 0x800000>;
st,smi-fast-mode;
partition@0 {
label = "xloader";
reg = <0x0 0x10000>;
};
partition@10000 {
label = "u-boot";
reg = <0x10000 0x40000>;
};
partition@50000 {
label = "linux";
reg = <0x50000 0x2c0000>;
};
partition@310000 {
label = "rootfs";
reg = <0x310000 0x4f0000>;
};
};
};
spi0: spi@d0100000 {
......
arch/arm/boot/dts/spear310-evb.dts
View file @ c2e1ff39
......@@ -103,11 +103,27 @@ smi: flash@fc000000 {
clock-rate=<50000000>;
flash@f8000000 {
label = "m25p64";
reg = <0xf8000000 0x800000>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0xf8000000 0x800000>;
st,smi-fast-mode;
partition@0 {
label = "xloader";
reg = <0x0 0x10000>;
};
partition@10000 {
label = "u-boot";
reg = <0x10000 0x40000>;
};
partition@50000 {
label = "linux";
reg = <0x50000 0x2c0000>;
};
partition@310000 {
label = "rootfs";
reg = <0x310000 0x4f0000>;
};
};
};
......
arch/arm/boot/dts/spear320-evb.dts
View file @ c2e1ff39
......@@ -110,6 +110,31 @@ sdhci@70000000 {
smi: flash@fc000000 {
status = "okay";
clock-rate=<50000000>;
flash@f8000000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xf8000000 0x800000>;
st,smi-fast-mode;
partition@0 {
label = "xloader";
reg = <0x0 0x10000>;
};
partition@10000 {
label = "u-boot";
reg = <0x10000 0x40000>;
};
partition@50000 {
label = "linux";
reg = <0x50000 0x2c0000>;
};
partition@310000 {
label = "rootfs";
reg = <0x310000 0x4f0000>;
};
};
};
spi0: spi@d0100000 {
......
arch/arm/boot/dts/spear3xx.dtsi
View file @ c2e1ff39
......@@ -139,6 +139,12 @@ wdt@fc880000 {
interrupts = <12>;
status = "disabled";
};
timer@f0000000 {
compatible = "st,spear-timer";
reg = <0xf0000000 0x400>;
interrupts = <2>;
};
};
};
};
arch/arm/boot/dts/spear600-evb.dts
View file @ c2e1ff39
......@@ -33,6 +33,35 @@ gmac: ethernet@e0800000 {
status = "okay";
};
smi: flash@fc000000 {
status = "okay";
clock-rate=<50000000>;
flash@f8000000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xf8000000 0x800000>;
st,smi-fast-mode;
partition@0 {
label = "xloader";
reg = <0x0 0x10000>;
};
partition@10000 {
label = "u-boot";
reg = <0x10000 0x40000>;
};
partition@50000 {
label = "linux";
reg = <0x50000 0x2c0000>;
};
partition@310000 {
label = "rootfs";
reg = <0x310000 0x4f0000>;
};
};
};
apb {
serial@d0000000 {
status = "okay";
......
arch/arm/boot/dts/spear600.dtsi
View file @ c2e1ff39
......@@ -177,6 +177,12 @@ i2c@d0200000 {
interrupts = <28>;
status = "disabled";
};
timer@f0000000 {
compatible = "st,spear-timer";
reg = <0xf0000000 0x400>;
interrupts = <16>;
};
};
};
};
arch/arm/boot/dts/tegra-cardhu.dts
View file @ c2e1ff39
......@@ -7,10 +7,10 @@ / {
compatible = "nvidia,cardhu", "nvidia,tegra30";
memory {
reg = < 0x80000000 0x40000000 >;
reg = <0x80000000 0x40000000>;
};
pinmux@70000000 {
pinmux {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
......@@ -51,64 +51,122 @@ sdmmc4_dat0_paa0 {
nvidia,pull = <2>;
nvidia,tristate = <0>;
};
dap2_fs_pa2 {
nvidia,pins = "dap2_fs_pa2",
"dap2_sclk_pa3",
"dap2_din_pa4",
"dap2_dout_pa5";
nvidia,function = "i2s1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
};
};
};
serial@70006000 {
clock-frequency = < 408000000 >;
};
serial@70006040 {
status = "disable";
};
serial@70006200 {
status = "disable";
};
serial@70006300 {
status = "disable";
};
serial@70006400 {
status = "disable";
status = "okay";
clock-frequency = <408000000>;
};
i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
};
i2c@7000c400 {
status = "okay";
clock-frequency = <100000>;
};
i2c@7000c500 {
status = "okay";
clock-frequency = <100000>;
/* ALS and Proximity sensor */
isl29028@44 {
compatible = "isil,isl29028";
reg = <0x44>;
interrupt-parent = <&gpio>;
interrupts = <88 0x04>; /*gpio PL0 */
};
};
i2c@7000c700 {
status = "okay";
clock-frequency = <100000>;
};
i2c@7000d000 {
status = "okay";
clock-frequency = <100000>;
wm8903: wm8903@1a {
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
interrupts = <179 0x04>; /* gpio PW3 */
gpio-controller;
#gpio-cells = <2>;
micdet-cfg = <0>;
micdet-delay = <100>;
gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
};
tps62361 {
compatible = "ti,tps62361";
reg = <0x60>;
regulator-name = "tps62361-vout";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
ti,vsel0-state-high;
ti,vsel1-state-high;
};
};
ahub {
i2s@70080400 {
status = "okay";
};
};
sdhci@78000000 {
status = "okay";
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
wp-gpios = <&gpio 155 0>; /* gpio PT3 */
power-gpios = <&gpio 31 0>; /* gpio PD7 */
bus-width = <4>;
};
sdhci@78000200 {
status = "disable";
sdhci@78000600 {
status = "okay";
support-8bit;
bus-width = <8>;
};
sdhci@78000400 {
status = "disable";
};
sound {
compatible = "nvidia,tegra-audio-wm8903-cardhu",
"nvidia,tegra-audio-wm8903";
nvidia,model = "NVIDIA Tegra Cardhu";
sdhci@78000400 {
support-8bit;
nvidia,audio-routing =
"Headphone Jack", "HPOUTR",
"Headphone Jack", "HPOUTL",
"Int Spk", "ROP",
"Int Spk", "RON",
"Int Spk", "LOP",
"Int Spk", "LON",
"Mic Jack", "MICBIAS",
"IN1L", "Mic Jack";
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
};
};
arch/arm/boot/dts/tegra-harmony.dts
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arch/arm/boot/dts/tegra-paz00.dts
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arch/arm/boot/dts/tegra-seaboard.dts
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arch/arm/boot/dts/tegra-trimslice.dts
View file @ c2e1ff39
......@@ -6,11 +6,11 @@ / {
model = "Compulab TrimSlice board";
compatible = "compulab,trimslice", "nvidia,tegra20";
memory@0 {
reg = < 0x00000000 0x40000000 >;
memory {
reg = <0x00000000 0x40000000>;
};
pinmux@70000000 {
pinmux {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
......@@ -182,23 +182,23 @@ conf_ata {
nvidia,tristate = <1>;
};
conf_atb {
nvidia,pins = "atb", "cdev1", "dap1", "gma",
"gmc", "gmd", "gpu", "gpu7", "gpv",
"sdio1", "slxa", "slxk", "uac";
nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
"gma", "gmc", "gmd", "gpu", "gpu7",
"gpv", "sdio1", "slxa", "slxk", "uac";
nvidia,pull = <0>;
nvidia,tristate = <0>;
};
conf_cdev2 {
nvidia,pins = "cdev2", "csus", "spia", "spib",
"spid", "spif";
nvidia,pull = <1>;
nvidia,tristate = <1>;
};
conf_ck32 {
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
nvidia,pull = <0>;
};
conf_csus {
nvidia,pins = "csus", "spia", "spib",
"spid", "spif";
nvidia,pull = <1>;
nvidia,tristate = <1>;
};
conf_ddc {
nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
nvidia,pull = <2>;
......@@ -240,68 +240,67 @@ conf_ld17_0 {
};
};
i2s@70002800 {
status = "okay";
};
serial@70006000 {
status = "okay";
clock-frequency = <216000000>;
};
i2c@7000c000 {
status = "okay";
clock-frequency = <400000>;
};
i2c@7000c400 {
status = "okay";
clock-frequency = <400000>;
};
i2c@7000c500 {
status = "okay";
clock-frequency = <400000>;
};
i2c@7000d000 {
status = "disable";
};
i2s@70002800 {
status = "disable";
};
i2s@70002a00 {
status = "disable";
};
das@70000c00 {
status = "disable";
};
serial@70006000 {
clock-frequency = < 216000000 >;
};
codec: codec@1a {
compatible = "ti,tlv320aic23";
reg = <0x1a>;
};
serial@70006040 {
status = "disable";
rtc@56 {
compatible = "emmicro,em3027";
reg = <0x56>;
};
};
serial@70006200 {
status = "disable";
usb@c5000000 {
status = "okay";
};
serial@70006300 {
status = "disable";
usb@c5004000 {
nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
};
serial@70006400 {
status = "disable";
usb@c5008000 {
status = "okay";
};
sdhci@c8000000 {
status = "disable";
status = "okay";
bus-width = <4>;
};
sdhci@c8000200 {
status = "disable";
};
sdhci@c8000400 {
status = "disable";
sdhci@c8000600 {
status = "okay";
cd-gpios = <&gpio 121 0>; /* gpio PP1 */
wp-gpios = <&gpio 122 0>; /* gpio PP2 */
bus-width = <4>;
};
sdhci@c8000600 {
cd-gpios = <&gpio 121 0>;
wp-gpios = <&gpio 122 0>;
sound {
compatible = "nvidia,tegra-audio-trimslice";
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&codec>;
};
};
arch/arm/boot/dts/tegra-ventana.dts
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arch/arm/boot/dts/tegra20.dtsi
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arch/arm/boot/dts/tegra30.dtsi
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arch/arm/common/dmabounce.c
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arch/arm/configs/imx_v4_v5_defconfig
View file @ c2e1ff39
......@@ -33,6 +33,7 @@ CONFIG_MACH_IMX27LITE=y
CONFIG_MACH_PCA100=y
CONFIG_MACH_MXT_TD60=y
CONFIG_MACH_IMX27IPCAM=y
CONFIG_MACH_IMX27_DT=y
CONFIG_MXC_IRQ_PRIOR=y
CONFIG_MXC_PWM=y
CONFIG_NO_HZ=y
......
arch/arm/configs/imx_v6_v7_defconfig
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arch/arm/configs/mxs_defconfig
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arch/arm/configs/prima2_defconfig 0 → 100644
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arch/arm/configs/spear13xx_defconfig 0 → 100644
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arch/arm/configs/spear3xx_defconfig
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arch/arm/configs/spear6xx_defconfig
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arch/arm/configs/tegra_defconfig
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arch/arm/include/asm/device.h
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arch/arm/include/asm/dma-contiguous.h 0 → 100644
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arch/arm/include/asm/dma-iommu.h 0 → 100644
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arch/arm/include/asm/dma-mapping.h
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arch/arm/include/asm/hardware/pl080.h
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arch/arm/include/asm/mach/arch.h
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arch/arm/include/asm/mach/map.h
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arch/arm/kernel/setup.c
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arch/arm/mach-at91/at91sam9g45_devices.c
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arch/arm/mach-at91/include/mach/at_hdmac.h
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arch/arm/mach-davinci/board-da830-evm.c
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arch/arm/mach-davinci/board-da850-evm.c
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