Commit c3310e77 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc:
  powerpc/ps3: Fix build error on UP
  powerpc/cell: Select PCI for IBM_CELL_BLADE AND CELLEB
  powerpc: ppc32 needs elf_read_implies_exec()
  powerpc/86xx: Add device_type entry to soc for ppc9a
  powerpc/44x: Correct memory size calculation for denali-based boards
  maintainers: Fix PowerPC 4xx git tree
  powerpc: fix for long standing bug noticed by gcc 4.4.0
  Revert "powerpc: Add support for early tlbilx opcode"
parents 13beadd9 d8f48457
...@@ -3448,7 +3448,7 @@ P: Matt Porter ...@@ -3448,7 +3448,7 @@ P: Matt Porter
M: mporter@kernel.crashing.org M: mporter@kernel.crashing.org
W: http://www.penguinppc.org/ W: http://www.penguinppc.org/
L: linuxppc-dev@ozlabs.org L: linuxppc-dev@ozlabs.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx.git
S: Maintained S: Maintained
LINUX FOR POWERPC EMBEDDED XILINX VIRTEX LINUX FOR POWERPC EMBEDDED XILINX VIRTEX
......
...@@ -158,21 +158,33 @@ void ibm440spe_fixup_memsize(void) ...@@ -158,21 +158,33 @@ void ibm440spe_fixup_memsize(void)
#define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask)) #define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask))
void ibm4xx_denali_fixup_memsize(void) /*
* Some U-Boot versions set the number of chipselects to two
* for Sequoia/Rainier boards while they only have one chipselect
* hardwired. Hardcode the number of chipselects to one
* for sequioa/rainer board models or read the actual value
* from the memory controller register DDR0_10 otherwise.
*/
static inline u32 ibm4xx_denali_get_cs(void)
{ {
u32 val, max_cs, max_col, max_row; void *devp;
u32 cs, col, row, bank, dpath; char model[64];
unsigned long memsize; u32 val, cs;
val = SDRAM0_READ(DDR0_02); devp = finddevice("/");
if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT)) if (!devp)
fatal("DDR controller is not initialized\n"); goto read_cs;
/* get maximum cs col and row values */ if (getprop(devp, "model", model, sizeof(model)) <= 0)
max_cs = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT); goto read_cs;
max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT);
max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
model[sizeof(model)-1] = 0;
if (!strcmp(model, "amcc,sequoia") ||
!strcmp(model, "amcc,rainier"))
return 1;
read_cs:
/* get CS value */ /* get CS value */
val = SDRAM0_READ(DDR0_10); val = SDRAM0_READ(DDR0_10);
...@@ -183,7 +195,25 @@ void ibm4xx_denali_fixup_memsize(void) ...@@ -183,7 +195,25 @@ void ibm4xx_denali_fixup_memsize(void)
cs++; cs++;
val = val >> 1; val = val >> 1;
} }
return cs;
}
void ibm4xx_denali_fixup_memsize(void)
{
u32 val, max_cs, max_col, max_row;
u32 cs, col, row, bank, dpath;
unsigned long memsize;
val = SDRAM0_READ(DDR0_02);
if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT))
fatal("DDR controller is not initialized\n");
/* get maximum cs col and row values */
max_cs = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT);
max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT);
max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
cs = ibm4xx_denali_get_cs();
if (!cs) if (!cs)
fatal("No memory installed\n"); fatal("No memory installed\n");
if (cs > max_cs) if (cs > max_cs)
...@@ -193,9 +223,9 @@ void ibm4xx_denali_fixup_memsize(void) ...@@ -193,9 +223,9 @@ void ibm4xx_denali_fixup_memsize(void)
val = SDRAM0_READ(DDR0_14); val = SDRAM0_READ(DDR0_14);
if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT)) if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT))
dpath = 8; /* 64 bits */
else
dpath = 4; /* 32 bits */ dpath = 4; /* 32 bits */
else
dpath = 8; /* 64 bits */
/* get address pins (rows) */ /* get address pins (rows) */
val = SDRAM0_READ(DDR0_42); val = SDRAM0_READ(DDR0_42);
......
...@@ -161,6 +161,7 @@ soc@fef00000 { ...@@ -161,6 +161,7 @@ soc@fef00000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
device_type = "soc";
compatible = "fsl,mpc8641-soc", "simple-bus"; compatible = "fsl,mpc8641-soc", "simple-bus";
ranges = <0x0 0xfef00000 0x00100000>; ranges = <0x0 0xfef00000 0x00100000>;
reg = <0xfef00000 0x100000>; // CCSRBAR 1M reg = <0xfef00000 0x100000>; // CCSRBAR 1M
......
...@@ -260,6 +260,7 @@ do { \ ...@@ -260,6 +260,7 @@ do { \
#else #else
# define SET_PERSONALITY(ex) \ # define SET_PERSONALITY(ex) \
set_personality(PER_LINUX | (current->personality & (~PER_MASK))) set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
# define elf_read_implies_exec(ex, exec_stk) (exec_stk != EXSTACK_DISABLE_X)
#endif /* __powerpc64__ */ #endif /* __powerpc64__ */
extern int dcache_bsize; extern int dcache_bsize;
......
...@@ -52,12 +52,6 @@ ...@@ -52,12 +52,6 @@
*/ */
#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
/* This indicates that the processor uses the wrong opcode for tlbilx
* instructions. During the ISA 2.06 development the opcode for tlbilx
* changed and some early implementations used to old opcode
*/
#define MMU_FTR_TLBILX_EARLY_OPCODE ASM_CONST(0x00400000)
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
#include <asm/cputable.h> #include <asm/cputable.h>
......
...@@ -44,7 +44,6 @@ ...@@ -44,7 +44,6 @@
#define PPC_INST_STSWI 0x7c0005aa #define PPC_INST_STSWI 0x7c0005aa
#define PPC_INST_STSWX 0x7c00052a #define PPC_INST_STSWX 0x7c00052a
#define PPC_INST_TLBILX 0x7c000024 #define PPC_INST_TLBILX 0x7c000024
#define PPC_INST_TLBILX_EARLY 0x7c000626
#define PPC_INST_WAIT 0x7c00007c #define PPC_INST_WAIT 0x7c00007c
/* macros to insert fields into opcodes */ /* macros to insert fields into opcodes */
...@@ -64,18 +63,10 @@ ...@@ -64,18 +63,10 @@
#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) #define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) #define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \ #define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \
__PPC_T_TLB(t) | \ __PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b))
__PPC_RA(a) | __PPC_RB(b))
#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b) #define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b) #define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
#define PPC_TLBILX_EARLY(t, a, b) stringify_in_c(.long PPC_INST_TLBILX_EARLY | \
__PPC_T_TLB(t) | \
__PPC_RA(a) | __PPC_RB(b))
#define PPC_TLBILX_ALL_EARLY(a, b) PPC_TLBILX_EARLY(0, a, b)
#define PPC_TLBILX_PID_EARLY(a, b) PPC_TLBILX_EARLY(1, a, b)
#define PPC_TLBILX_VA_EARLY(a, b) PPC_TLBILX_EARLY(3, a, b)
#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
__PPC_WC(w)) __PPC_WC(w))
......
...@@ -1766,7 +1766,7 @@ static struct cpu_spec __initdata cpu_specs[] = { ...@@ -1766,7 +1766,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_features = CPU_FTRS_E500MC, .cpu_features = CPU_FTRS_E500MC,
.cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
.mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
MMU_FTR_USE_TLBILX | MMU_FTR_TLBILX_EARLY_OPCODE, MMU_FTR_USE_TLBILX,
.icache_bsize = 64, .icache_bsize = 64,
.dcache_bsize = 64, .dcache_bsize = 64,
.num_pmcs = 4, .num_pmcs = 4,
......
...@@ -138,11 +138,7 @@ BEGIN_MMU_FTR_SECTION ...@@ -138,11 +138,7 @@ BEGIN_MMU_FTR_SECTION
andi. r3,r3,MMUCSR0_TLBFI@l andi. r3,r3,MMUCSR0_TLBFI@l
bne 1b bne 1b
MMU_FTR_SECTION_ELSE MMU_FTR_SECTION_ELSE
BEGIN_MMU_FTR_SECTION_NESTED(96) PPC_TLBILX_ALL(0,0)
PPC_TLBILX_ALL(0,r3)
MMU_FTR_SECTION_ELSE_NESTED(96)
PPC_TLBILX_ALL_EARLY(0,r3)
ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96)
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
msync msync
isync isync
...@@ -155,11 +151,7 @@ BEGIN_MMU_FTR_SECTION ...@@ -155,11 +151,7 @@ BEGIN_MMU_FTR_SECTION
wrteei 0 wrteei 0
mfspr r4,SPRN_MAS6 /* save MAS6 */ mfspr r4,SPRN_MAS6 /* save MAS6 */
mtspr SPRN_MAS6,r3 mtspr SPRN_MAS6,r3
BEGIN_MMU_FTR_SECTION_NESTED(96)
PPC_TLBILX_PID(0,0) PPC_TLBILX_PID(0,0)
MMU_FTR_SECTION_ELSE_NESTED(96)
PPC_TLBILX_PID_EARLY(0,0)
ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96)
mtspr SPRN_MAS6,r4 /* restore MAS6 */ mtspr SPRN_MAS6,r4 /* restore MAS6 */
wrtee r10 wrtee r10
MMU_FTR_SECTION_ELSE MMU_FTR_SECTION_ELSE
...@@ -193,16 +185,12 @@ BEGIN_MMU_FTR_SECTION ...@@ -193,16 +185,12 @@ BEGIN_MMU_FTR_SECTION
mtspr SPRN_MAS1,r4 mtspr SPRN_MAS1,r4
tlbwe tlbwe
MMU_FTR_SECTION_ELSE MMU_FTR_SECTION_ELSE
BEGIN_MMU_FTR_SECTION_NESTED(96)
PPC_TLBILX_VA(0,r3) PPC_TLBILX_VA(0,r3)
MMU_FTR_SECTION_ELSE_NESTED(96)
PPC_TLBILX_VA_EARLY(0,r3)
ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96)
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
msync msync
isync isync
1: wrtee r10 1: wrtee r10
blr blr
#elif #else
#error Unsupported processor type ! #error Unsupported processor type !
#endif #endif
...@@ -13,7 +13,6 @@ config PPC_CELL_COMMON ...@@ -13,7 +13,6 @@ config PPC_CELL_COMMON
config PPC_CELL_NATIVE config PPC_CELL_NATIVE
bool bool
select PPC_CELL_COMMON select PPC_CELL_COMMON
select PPC_OF_PLATFORM_PCI
select MPIC select MPIC
select IBM_NEW_EMAC_EMAC4 select IBM_NEW_EMAC_EMAC4
select IBM_NEW_EMAC_RGMII select IBM_NEW_EMAC_RGMII
...@@ -25,6 +24,8 @@ config PPC_IBM_CELL_BLADE ...@@ -25,6 +24,8 @@ config PPC_IBM_CELL_BLADE
bool "IBM Cell Blade" bool "IBM Cell Blade"
depends on PPC64 && PPC_BOOK3S depends on PPC64 && PPC_BOOK3S
select PPC_CELL_NATIVE select PPC_CELL_NATIVE
select PPC_OF_PLATFORM_PCI
select PCI
select MMIO_NVRAM select MMIO_NVRAM
select PPC_UDBG_16550 select PPC_UDBG_16550
select UDBG_RTAS_CONSOLE select UDBG_RTAS_CONSOLE
...@@ -33,6 +34,8 @@ config PPC_CELLEB ...@@ -33,6 +34,8 @@ config PPC_CELLEB
bool "Toshiba's Cell Reference Set 'Celleb' Architecture" bool "Toshiba's Cell Reference Set 'Celleb' Architecture"
depends on PPC64 && PPC_BOOK3S depends on PPC64 && PPC_BOOK3S
select PPC_CELL_NATIVE select PPC_CELL_NATIVE
select PPC_OF_PLATFORM_PCI
select PCI
select HAS_TXX9_SERIAL select HAS_TXX9_SERIAL
select PPC_UDBG_BEAT select PPC_UDBG_BEAT
select USB_OHCI_BIG_ENDIAN_MMIO select USB_OHCI_BIG_ENDIAN_MMIO
......
...@@ -45,10 +45,6 @@ ...@@ -45,10 +45,6 @@
DEFINE_MUTEX(ps3_gpu_mutex); DEFINE_MUTEX(ps3_gpu_mutex);
EXPORT_SYMBOL_GPL(ps3_gpu_mutex); EXPORT_SYMBOL_GPL(ps3_gpu_mutex);
#if !defined(CONFIG_SMP)
static void smp_send_stop(void) {}
#endif
static union ps3_firmware_version ps3_firmware_version; static union ps3_firmware_version ps3_firmware_version;
void ps3_get_firmware_version(union ps3_firmware_version *v) void ps3_get_firmware_version(union ps3_firmware_version *v)
......
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