Commit c3e0e1e2 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'irq_urgent_for_v6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull more irqchip fixes from Borislav Petkov:
 "More irqchip fixes for 6.0 from Marc Zyngier. Stuff got left hanging
  due to the whole Plumbers and vacations commotion.

   - A couple of configuration fixes for the recently merged Loongarch
     drivers

   - A fix to avoid dynamic allocation of a cpumask which was causing
     issues with PREEMPT_RT and the GICv3 ITS

   - A tightening of an error check in the stm32 exti driver"

* tag 'irq_urgent_for_v6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/loongson-pch-lpc: Add dependence on LoongArch
  irqchip: Select downstream irqchip drivers for LoongArch CPU
  irqchip/gic-v3-its: Remove cpumask_var_t allocation
  irqchip/stm32-exti: Remove check on always false condition
parents e817c070 c0cca6a6
...@@ -561,6 +561,11 @@ config IRQ_LOONGARCH_CPU ...@@ -561,6 +561,11 @@ config IRQ_LOONGARCH_CPU
select GENERIC_IRQ_CHIP select GENERIC_IRQ_CHIP
select IRQ_DOMAIN select IRQ_DOMAIN
select GENERIC_IRQ_EFFECTIVE_AFF_MASK select GENERIC_IRQ_EFFECTIVE_AFF_MASK
select LOONGSON_LIOINTC
select LOONGSON_EIOINTC
select LOONGSON_PCH_PIC
select LOONGSON_PCH_MSI
select LOONGSON_PCH_LPC
help help
Support for the LoongArch CPU Interrupt Controller. For details of Support for the LoongArch CPU Interrupt Controller. For details of
irq chip hierarchy on LoongArch platforms please read the document irq chip hierarchy on LoongArch platforms please read the document
...@@ -623,8 +628,9 @@ config LOONGSON_PCH_MSI ...@@ -623,8 +628,9 @@ config LOONGSON_PCH_MSI
config LOONGSON_PCH_LPC config LOONGSON_PCH_LPC
bool "Loongson PCH LPC Controller" bool "Loongson PCH LPC Controller"
depends on LOONGARCH
depends on MACH_LOONGSON64 depends on MACH_LOONGSON64
default (MACH_LOONGSON64 && LOONGARCH) default MACH_LOONGSON64
select IRQ_DOMAIN_HIERARCHY select IRQ_DOMAIN_HIERARCHY
help help
Support for the Loongson PCH LPC Controller. Support for the Loongson PCH LPC Controller.
......
...@@ -1574,13 +1574,15 @@ static int its_select_cpu(struct irq_data *d, ...@@ -1574,13 +1574,15 @@ static int its_select_cpu(struct irq_data *d,
const struct cpumask *aff_mask) const struct cpumask *aff_mask)
{ {
struct its_device *its_dev = irq_data_get_irq_chip_data(d); struct its_device *its_dev = irq_data_get_irq_chip_data(d);
cpumask_var_t tmpmask; static DEFINE_RAW_SPINLOCK(tmpmask_lock);
static struct cpumask __tmpmask;
struct cpumask *tmpmask;
unsigned long flags;
int cpu, node; int cpu, node;
if (!alloc_cpumask_var(&tmpmask, GFP_ATOMIC))
return -ENOMEM;
node = its_dev->its->numa_node; node = its_dev->its->numa_node;
tmpmask = &__tmpmask;
raw_spin_lock_irqsave(&tmpmask_lock, flags);
if (!irqd_affinity_is_managed(d)) { if (!irqd_affinity_is_managed(d)) {
/* First try the NUMA node */ /* First try the NUMA node */
...@@ -1634,7 +1636,7 @@ static int its_select_cpu(struct irq_data *d, ...@@ -1634,7 +1636,7 @@ static int its_select_cpu(struct irq_data *d,
cpu = cpumask_pick_least_loaded(d, tmpmask); cpu = cpumask_pick_least_loaded(d, tmpmask);
} }
out: out:
free_cpumask_var(tmpmask); raw_spin_unlock_irqrestore(&tmpmask_lock, flags);
pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu); pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu);
return cpu; return cpu;
......
...@@ -716,7 +716,7 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm, ...@@ -716,7 +716,7 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data); irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data);
if (!host_data->drv_data || !host_data->drv_data->desc_irqs) if (!host_data->drv_data->desc_irqs)
return -EINVAL; return -EINVAL;
desc_irq = host_data->drv_data->desc_irqs[hwirq]; desc_irq = host_data->drv_data->desc_irqs[hwirq];
......
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