Commit c49154ff authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo

rtw89: update scheduler setting

Update IC specific settings accordingly.
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220325060055.58482-14-pkshih@realtek.com
parent b61adeed
......@@ -1731,6 +1731,17 @@ static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx)
if (ret)
return ret;
reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_1, mac_idx);
rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, SIFS_MACTXEN_T1);
if (rtwdev->chip->chip_id == RTL8852B) {
reg = rtw89_mac_reg_by_idx(R_AX_SCH_EXT_CTRL, mac_idx);
rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV);
}
reg = rtw89_mac_reg_by_idx(R_AX_CCA_CFG_0, mac_idx);
rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN);
reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx);
rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, SCH_PREBKF_24US);
......
......@@ -977,6 +977,14 @@
#define R_AX_PREBKF_CFG_0_C1 0xE338
#define B_AX_PREBKF_TIME_MASK GENMASK(4, 0)
#define R_AX_PREBKF_CFG_1 0xC33C
#define R_AX_PREBKF_CFG_1_C1 0xE33C
#define B_AX_SIFS_TIMEOUT_TB_AGGR_MASK GENMASK(30, 24)
#define B_AX_SIFS_PREBKF_MASK GENMASK(23, 16)
#define B_AX_SIFS_TIMEOUT_T2_MASK GENMASK(14, 8)
#define B_AX_SIFS_MACTXEN_T1_MASK GENMASK(6, 0)
#define SIFS_MACTXEN_T1 0x47
#define R_AX_CCA_CFG_0 0xC340
#define R_AX_CCA_CFG_0_C1 0xE340
#define B_AX_BTCCA_BRK_TXOP_EN BIT(9)
......@@ -1076,6 +1084,10 @@
#define R_AX_SCH_DBG_C1 0xE3F8
#define B_AX_SCHEDULER_DBG_MASK GENMASK(31, 0)
#define R_AX_SCH_EXT_CTRL 0xC3FC
#define R_AX_SCH_EXT_CTRL_C1 0xE3FC
#define B_AX_PORT_RST_TSF_ADV BIT(1)
#define R_AX_PORT_CFG_P0 0xC400
#define R_AX_PORT_CFG_P1 0xC440
#define R_AX_PORT_CFG_P2 0xC480
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment