Commit c50c84c3 authored by Martin Schwidefsky's avatar Martin Schwidefsky

s390/kernel: use expoline for indirect branches

The assember code in arch/s390/kernel uses a few more indirect branches
which need to be done with execute trampolines for CONFIG_EXPOLINE=y.

Cc: stable@vger.kernel.org # 4.16
Fixes: f19fbd5e ("s390: introduce execute-trampolines for branches")
Reviewed-by: default avatarHendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: default avatarMartin Schwidefsky <schwidefsky@de.ibm.com>
parent 23a4d7fd
...@@ -9,18 +9,22 @@ ...@@ -9,18 +9,22 @@
#include <linux/linkage.h> #include <linux/linkage.h>
#include <asm/asm-offsets.h> #include <asm/asm-offsets.h>
#include <asm/nospec-insn.h>
#include <asm/ptrace.h> #include <asm/ptrace.h>
#include <asm/sigp.h> #include <asm/sigp.h>
GEN_BR_THUNK %r9
GEN_BR_THUNK %r14
ENTRY(s390_base_mcck_handler) ENTRY(s390_base_mcck_handler)
basr %r13,0 basr %r13,0
0: lg %r15,__LC_PANIC_STACK # load panic stack 0: lg %r15,__LC_PANIC_STACK # load panic stack
aghi %r15,-STACK_FRAME_OVERHEAD aghi %r15,-STACK_FRAME_OVERHEAD
larl %r1,s390_base_mcck_handler_fn larl %r1,s390_base_mcck_handler_fn
lg %r1,0(%r1) lg %r9,0(%r1)
ltgr %r1,%r1 ltgr %r9,%r9
jz 1f jz 1f
basr %r14,%r1 BASR_EX %r14,%r9
1: la %r1,4095 1: la %r1,4095
lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1) lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)
lpswe __LC_MCK_OLD_PSW lpswe __LC_MCK_OLD_PSW
...@@ -37,10 +41,10 @@ ENTRY(s390_base_ext_handler) ...@@ -37,10 +41,10 @@ ENTRY(s390_base_ext_handler)
basr %r13,0 basr %r13,0
0: aghi %r15,-STACK_FRAME_OVERHEAD 0: aghi %r15,-STACK_FRAME_OVERHEAD
larl %r1,s390_base_ext_handler_fn larl %r1,s390_base_ext_handler_fn
lg %r1,0(%r1) lg %r9,0(%r1)
ltgr %r1,%r1 ltgr %r9,%r9
jz 1f jz 1f
basr %r14,%r1 BASR_EX %r14,%r9
1: lmg %r0,%r15,__LC_SAVE_AREA_ASYNC 1: lmg %r0,%r15,__LC_SAVE_AREA_ASYNC
ni __LC_EXT_OLD_PSW+1,0xfd # clear wait state bit ni __LC_EXT_OLD_PSW+1,0xfd # clear wait state bit
lpswe __LC_EXT_OLD_PSW lpswe __LC_EXT_OLD_PSW
...@@ -57,10 +61,10 @@ ENTRY(s390_base_pgm_handler) ...@@ -57,10 +61,10 @@ ENTRY(s390_base_pgm_handler)
basr %r13,0 basr %r13,0
0: aghi %r15,-STACK_FRAME_OVERHEAD 0: aghi %r15,-STACK_FRAME_OVERHEAD
larl %r1,s390_base_pgm_handler_fn larl %r1,s390_base_pgm_handler_fn
lg %r1,0(%r1) lg %r9,0(%r1)
ltgr %r1,%r1 ltgr %r9,%r9
jz 1f jz 1f
basr %r14,%r1 BASR_EX %r14,%r9
lmg %r0,%r15,__LC_SAVE_AREA_SYNC lmg %r0,%r15,__LC_SAVE_AREA_SYNC
lpswe __LC_PGM_OLD_PSW lpswe __LC_PGM_OLD_PSW
1: lpswe disabled_wait_psw-0b(%r13) 1: lpswe disabled_wait_psw-0b(%r13)
...@@ -117,7 +121,7 @@ ENTRY(diag308_reset) ...@@ -117,7 +121,7 @@ ENTRY(diag308_reset)
larl %r4,.Lcontinue_psw # Restore PSW flags larl %r4,.Lcontinue_psw # Restore PSW flags
lpswe 0(%r4) lpswe 0(%r4)
.Lcontinue: .Lcontinue:
br %r14 BR_EX %r14
.align 16 .align 16
.Lrestart_psw: .Lrestart_psw:
.long 0x00080000,0x80000000 + .Lrestart_part2 .long 0x00080000,0x80000000 + .Lrestart_part2
......
...@@ -7,8 +7,11 @@ ...@@ -7,8 +7,11 @@
#include <linux/linkage.h> #include <linux/linkage.h>
#include <asm/asm-offsets.h> #include <asm/asm-offsets.h>
#include <asm/nospec-insn.h>
#include <asm/sigp.h> #include <asm/sigp.h>
GEN_BR_THUNK %r9
# #
# Issue "store status" for the current CPU to its prefix page # Issue "store status" for the current CPU to its prefix page
# and call passed function afterwards # and call passed function afterwards
...@@ -67,9 +70,9 @@ ENTRY(store_status) ...@@ -67,9 +70,9 @@ ENTRY(store_status)
st %r4,0(%r1) st %r4,0(%r1)
st %r5,4(%r1) st %r5,4(%r1)
stg %r2,8(%r1) stg %r2,8(%r1)
lgr %r1,%r2 lgr %r9,%r2
lgr %r2,%r3 lgr %r2,%r3
br %r1 BR_EX %r9
.section .bss .section .bss
.align 8 .align 8
......
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
#include <asm/ptrace.h> #include <asm/ptrace.h>
#include <asm/thread_info.h> #include <asm/thread_info.h>
#include <asm/asm-offsets.h> #include <asm/asm-offsets.h>
#include <asm/nospec-insn.h>
#include <asm/sigp.h> #include <asm/sigp.h>
/* /*
...@@ -24,6 +25,8 @@ ...@@ -24,6 +25,8 @@
* (see below) in the resume process. * (see below) in the resume process.
* This function runs with disabled interrupts. * This function runs with disabled interrupts.
*/ */
GEN_BR_THUNK %r14
.section .text .section .text
ENTRY(swsusp_arch_suspend) ENTRY(swsusp_arch_suspend)
stmg %r6,%r15,__SF_GPRS(%r15) stmg %r6,%r15,__SF_GPRS(%r15)
...@@ -103,7 +106,7 @@ ENTRY(swsusp_arch_suspend) ...@@ -103,7 +106,7 @@ ENTRY(swsusp_arch_suspend)
spx 0x318(%r1) spx 0x318(%r1)
lmg %r6,%r15,STACK_FRAME_OVERHEAD + __SF_GPRS(%r15) lmg %r6,%r15,STACK_FRAME_OVERHEAD + __SF_GPRS(%r15)
lghi %r2,0 lghi %r2,0
br %r14 BR_EX %r14
/* /*
* Restore saved memory image to correct place and restore register context. * Restore saved memory image to correct place and restore register context.
...@@ -197,11 +200,10 @@ pgm_check_entry: ...@@ -197,11 +200,10 @@ pgm_check_entry:
larl %r15,init_thread_union larl %r15,init_thread_union
ahi %r15,1<<(PAGE_SHIFT+THREAD_SIZE_ORDER) ahi %r15,1<<(PAGE_SHIFT+THREAD_SIZE_ORDER)
larl %r2,.Lpanic_string larl %r2,.Lpanic_string
larl %r3,sclp_early_printk
lghi %r1,0 lghi %r1,0
sam31 sam31
sigp %r1,%r0,SIGP_SET_ARCHITECTURE sigp %r1,%r0,SIGP_SET_ARCHITECTURE
basr %r14,%r3 brasl %r14,sclp_early_printk
larl %r3,.Ldisabled_wait_31 larl %r3,.Ldisabled_wait_31
lpsw 0(%r3) lpsw 0(%r3)
4: 4:
...@@ -267,7 +269,7 @@ restore_registers: ...@@ -267,7 +269,7 @@ restore_registers:
/* Return 0 */ /* Return 0 */
lmg %r6,%r15,STACK_FRAME_OVERHEAD + __SF_GPRS(%r15) lmg %r6,%r15,STACK_FRAME_OVERHEAD + __SF_GPRS(%r15)
lghi %r2,0 lghi %r2,0
br %r14 BR_EX %r14
.section .data..nosave,"aw",@progbits .section .data..nosave,"aw",@progbits
.align 8 .align 8
......
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