Commit c58a27a4 authored by Olof Johansson's avatar Olof Johansson

Merge tag 'omap-for-v3.16/fixes-rc4' of...

Merge tag 'omap-for-v3.16/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes

Merge "omap fixes against v3.16-rc4" from Tony Lindgren:

Fixes for omaps for the -rc series. It's mostly fixes for clock rates,
restart handling and phy regulators and SATA interconnect data.

Also few build fixes related to the DSP driver in staging, and trivial
stuff like removal of broken and soon to be unused platform data init
for HDMI audio that would be good to get into the -rc series if not
too late.

* tag 'omap-for-v3.16/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: Remove non working OMAP HDMI audio initialization
  ARM: dts: Fix TI CPSW Phy mode selection on IGEP COM AQUILA.
  ARM: dts: am335x-evmsk: Enable the McASP FIFO for audio
  ARM: dts: am335x-evm: Enable the McASP FIFO for audio
  ARM: OMAP2+: Make GPMC skip disabled devices
  ARM: OMAP2+: create dsp device only on OMAP3 SoCs
  ARM: dts: dra7-evm: Make VDDA_1V8_PHY supply always on
  ARM: DRA7/AM43XX: fix header definition for omap44xx_restart
  ARM: OMAP2+: clock/dpll: fix _dpll_test_fint arithmetics overflow
  ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss
  ARM: DRA7: hwmod: Fixup SATA hwmod
  ARM: OMAP3: PRM/CM: Add back macros used by TI DSP/Bridge driver
  ARM: dts: dra7xx-clocks: Fix the l3 and l4 clock rates
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 63288b72 1d29a072
...@@ -529,8 +529,8 @@ &mcasp1 { ...@@ -529,8 +529,8 @@ &mcasp1 {
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
0 0 1 2 0 0 1 2
>; >;
tx-num-evt = <1>; tx-num-evt = <32>;
rx-num-evt = <1>; rx-num-evt = <32>;
}; };
&tps { &tps {
......
...@@ -560,8 +560,8 @@ &mcasp1 { ...@@ -560,8 +560,8 @@ &mcasp1 {
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
0 0 1 2 0 0 1 2
>; >;
tx-num-evt = <1>; tx-num-evt = <32>;
rx-num-evt = <1>; rx-num-evt = <32>;
}; };
&tscadc { &tscadc {
......
...@@ -105,10 +105,16 @@ &davinci_mdio { ...@@ -105,10 +105,16 @@ &davinci_mdio {
&cpsw_emac0 { &cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>; phy_id = <&davinci_mdio>, <0>;
phy-mode = "rmii";
}; };
&cpsw_emac1 { &cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>; phy_id = <&davinci_mdio>, <1>;
phy-mode = "rmii";
};
&phy_sel {
rmii-clock-ext;
}; };
&elm { &elm {
......
...@@ -240,6 +240,7 @@ ldo3_reg: ldo3 { ...@@ -240,6 +240,7 @@ ldo3_reg: ldo3 {
regulator-name = "ldo3"; regulator-name = "ldo3";
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on; regulator-boot-on;
}; };
......
...@@ -673,10 +673,12 @@ hdmi_div_clk: hdmi_div_clk { ...@@ -673,10 +673,12 @@ hdmi_div_clk: hdmi_div_clk {
l3_iclk_div: l3_iclk_div { l3_iclk_div: l3_iclk_div {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-factor-clock"; compatible = "ti,divider-clock";
ti,max-div = <2>;
ti,bit-shift = <4>;
reg = <0x0100>;
clocks = <&dpll_core_h12x2_ck>; clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>; ti,index-power-of-two;
clock-div = <1>;
}; };
l4_root_clk_div: l4_root_clk_div { l4_root_clk_div: l4_root_clk_div {
...@@ -684,7 +686,7 @@ l4_root_clk_div: l4_root_clk_div { ...@@ -684,7 +686,7 @@ l4_root_clk_div: l4_root_clk_div {
compatible = "fixed-factor-clock"; compatible = "fixed-factor-clock";
clocks = <&l3_iclk_div>; clocks = <&l3_iclk_div>;
clock-mult = <1>; clock-mult = <1>;
clock-div = <1>; clock-div = <2>;
}; };
video1_clk2_div: video1_clk2_div { video1_clk2_div: video1_clk2_div {
......
...@@ -76,7 +76,7 @@ ...@@ -76,7 +76,7 @@
* (assuming that it is counting N upwards), or -2 if the enclosing loop * (assuming that it is counting N upwards), or -2 if the enclosing loop
* should skip to the next iteration (again assuming N is increasing). * should skip to the next iteration (again assuming N is increasing).
*/ */
static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n) static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
{ {
struct dpll_data *dd; struct dpll_data *dd;
long fint, fint_min, fint_max; long fint, fint_min, fint_max;
......
...@@ -26,11 +26,14 @@ ...@@ -26,11 +26,14 @@
#define OMAP3430_EN_WDT3_SHIFT 12 #define OMAP3430_EN_WDT3_SHIFT 12
#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0)
#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0
#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4
#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)
#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3
#define OMAP3430_EN_IVA2_DPLL_SHIFT 0
#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
#define OMAP3430_ST_IVA2_SHIFT 0 #define OMAP3430_ST_IVA2_SHIFT 0
#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)
#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0
#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)
#define OMAP3430_IVA2_CLK_SRC_SHIFT 19 #define OMAP3430_IVA2_CLK_SRC_SHIFT 19
#define OMAP3430_IVA2_CLK_SRC_WIDTH 3 #define OMAP3430_IVA2_CLK_SRC_WIDTH 3
......
...@@ -162,7 +162,8 @@ static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd) ...@@ -162,7 +162,8 @@ static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
} }
#endif #endif
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
void omap44xx_restart(enum reboot_mode mode, const char *cmd); void omap44xx_restart(enum reboot_mode mode, const char *cmd);
#else #else
static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd) static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd)
......
...@@ -297,33 +297,6 @@ static void omap_init_audio(void) ...@@ -297,33 +297,6 @@ static void omap_init_audio(void)
static inline void omap_init_audio(void) {} static inline void omap_init_audio(void) {}
#endif #endif
#if defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI) || \
defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI_MODULE)
static struct platform_device omap_hdmi_audio = {
.name = "omap-hdmi-audio",
.id = -1,
};
static void __init omap_init_hdmi_audio(void)
{
struct omap_hwmod *oh;
struct platform_device *pdev;
oh = omap_hwmod_lookup("dss_hdmi");
if (!oh)
return;
pdev = omap_device_build("omap-hdmi-audio-dai", -1, oh, NULL, 0);
WARN(IS_ERR(pdev),
"Can't build omap_device for omap-hdmi-audio-dai.\n");
platform_device_register(&omap_hdmi_audio);
}
#else
static inline void omap_init_hdmi_audio(void) {}
#endif
#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
#include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/platform_data/spi-omap2-mcspi.h>
...@@ -459,7 +432,6 @@ static int __init omap2_init_devices(void) ...@@ -459,7 +432,6 @@ static int __init omap2_init_devices(void)
*/ */
omap_init_audio(); omap_init_audio();
omap_init_camera(); omap_init_camera();
omap_init_hdmi_audio();
omap_init_mbox(); omap_init_mbox();
/* If dtb is there, the devices will be created dynamically */ /* If dtb is there, the devices will be created dynamically */
if (!of_have_populated_dt()) { if (!of_have_populated_dt()) {
......
...@@ -29,6 +29,7 @@ ...@@ -29,6 +29,7 @@
#ifdef CONFIG_TIDSPBRIDGE_DVFS #ifdef CONFIG_TIDSPBRIDGE_DVFS
#include "omap-pm.h" #include "omap-pm.h"
#endif #endif
#include "soc.h"
#include <linux/platform_data/dsp-omap.h> #include <linux/platform_data/dsp-omap.h>
...@@ -59,6 +60,9 @@ void __init omap_dsp_reserve_sdram_memblock(void) ...@@ -59,6 +60,9 @@ void __init omap_dsp_reserve_sdram_memblock(void)
phys_addr_t size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE; phys_addr_t size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE;
phys_addr_t paddr; phys_addr_t paddr;
if (!cpu_is_omap34xx())
return;
if (!size) if (!size)
return; return;
...@@ -83,6 +87,9 @@ static int __init omap_dsp_init(void) ...@@ -83,6 +87,9 @@ static int __init omap_dsp_init(void)
int err = -ENOMEM; int err = -ENOMEM;
struct omap_dsp_platform_data *pdata = &omap_dsp_pdata; struct omap_dsp_platform_data *pdata = &omap_dsp_pdata;
if (!cpu_is_omap34xx())
return 0;
pdata->phys_mempool_base = omap_dsp_get_mempool_base(); pdata->phys_mempool_base = omap_dsp_get_mempool_base();
if (pdata->phys_mempool_base) { if (pdata->phys_mempool_base) {
...@@ -115,6 +122,9 @@ module_init(omap_dsp_init); ...@@ -115,6 +122,9 @@ module_init(omap_dsp_init);
static void __exit omap_dsp_exit(void) static void __exit omap_dsp_exit(void)
{ {
if (!cpu_is_omap34xx())
return;
platform_device_unregister(omap_dsp_pdev); platform_device_unregister(omap_dsp_pdev);
} }
module_exit(omap_dsp_exit); module_exit(omap_dsp_exit);
......
...@@ -1615,7 +1615,7 @@ static int gpmc_probe_dt(struct platform_device *pdev) ...@@ -1615,7 +1615,7 @@ static int gpmc_probe_dt(struct platform_device *pdev)
return ret; return ret;
} }
for_each_child_of_node(pdev->dev.of_node, child) { for_each_available_child_of_node(pdev->dev.of_node, child) {
if (!child->name) if (!child->name)
continue; continue;
......
...@@ -1268,9 +1268,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = { ...@@ -1268,9 +1268,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
}; };
/* sata */ /* sata */
static struct omap_hwmod_opt_clk sata_opt_clks[] = {
{ .role = "ref_clk", .clk = "sata_ref_clk" },
};
static struct omap_hwmod dra7xx_sata_hwmod = { static struct omap_hwmod dra7xx_sata_hwmod = {
.name = "sata", .name = "sata",
...@@ -1278,6 +1275,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = { ...@@ -1278,6 +1275,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
.clkdm_name = "l3init_clkdm", .clkdm_name = "l3init_clkdm",
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "func_48m_fclk", .main_clk = "func_48m_fclk",
.mpu_rt_idx = 1,
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET, .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
...@@ -1285,8 +1283,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = { ...@@ -1285,8 +1283,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
.modulemode = MODULEMODE_SWCTRL, .modulemode = MODULEMODE_SWCTRL,
}, },
}, },
.opt_clks = sata_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
}; };
/* /*
...@@ -1731,8 +1727,20 @@ static struct omap_hwmod dra7xx_uart6_hwmod = { ...@@ -1731,8 +1727,20 @@ static struct omap_hwmod dra7xx_uart6_hwmod = {
* *
*/ */
static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
SYSC_HAS_SIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = { static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
.name = "usb_otg_ss", .name = "usb_otg_ss",
.sysc = &dra7xx_usb_otg_ss_sysc,
}; };
/* usb_otg_ss1 */ /* usb_otg_ss1 */
......
...@@ -35,6 +35,8 @@ ...@@ -35,6 +35,8 @@
#define OMAP3430_LOGICSTATEST_MASK (1 << 2) #define OMAP3430_LOGICSTATEST_MASK (1 << 2)
#define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2) #define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2)
#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) #define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0)
#define OMAP3430_GRPSEL_MCBSP5_MASK (1 << 10)
#define OMAP3430_GRPSEL_MCBSP1_MASK (1 << 9)
#define OMAP3630_GRPSEL_UART4_MASK (1 << 18) #define OMAP3630_GRPSEL_UART4_MASK (1 << 18)
#define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17) #define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17)
#define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16) #define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16)
...@@ -42,6 +44,10 @@ ...@@ -42,6 +44,10 @@
#define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14) #define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14)
#define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13) #define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13)
#define OMAP3430_GRPSEL_UART3_MASK (1 << 11) #define OMAP3430_GRPSEL_UART3_MASK (1 << 11)
#define OMAP3430_GRPSEL_GPT8_MASK (1 << 9)
#define OMAP3430_GRPSEL_GPT7_MASK (1 << 8)
#define OMAP3430_GRPSEL_GPT6_MASK (1 << 7)
#define OMAP3430_GRPSEL_GPT5_MASK (1 << 6)
#define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2) #define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2)
#define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1) #define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1)
#define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0) #define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0)
......
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