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Commit c5b3b850 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
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drm/radeon/kms: reorganize gart callbacks 

tidy up the radeon_asic struct.
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König<christian.koenig@amd.com>
Reviewed-by: default avatarMichel Dänzer <michel.daenzer@amd.com>
Reviewed-by: default avatarJerome Glisse <jglisse@redhat.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent f712812e
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Showing with 84 additions and 46 deletions
drivers/gpu/drm/radeon/r100.c
View file @ c5b3b850
...@@ -630,8 +630,8 @@ int r100_pci_gart_init(struct radeon_device *rdev) ...@@ -630,8 +630,8 @@ int r100_pci_gart_init(struct radeon_device *rdev)
if (r) if (r)
return r; return r;
rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
rdev->asic->gart_set_page = &r100_pci_gart_set_page; rdev->asic->gart.set_page = &r100_pci_gart_set_page;
return radeon_gart_table_ram_alloc(rdev); return radeon_gart_table_ram_alloc(rdev);
} }
......
drivers/gpu/drm/radeon/r300.c
View file @ c5b3b850
...@@ -105,8 +105,8 @@ int rv370_pcie_gart_init(struct radeon_device *rdev) ...@@ -105,8 +105,8 @@ int rv370_pcie_gart_init(struct radeon_device *rdev)
if (r) if (r)
DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
return radeon_gart_table_vram_alloc(rdev); return radeon_gart_table_vram_alloc(rdev);
} }
......
drivers/gpu/drm/radeon/radeon.h
View file @ c5b3b850
...@@ -1133,8 +1133,12 @@ struct radeon_asic { ...@@ -1133,8 +1133,12 @@ struct radeon_asic {
void (*vga_set_state)(struct radeon_device *rdev, bool state); void (*vga_set_state)(struct radeon_device *rdev, bool state);
bool (*gpu_is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); bool (*gpu_is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
int (*asic_reset)(struct radeon_device *rdev); int (*asic_reset)(struct radeon_device *rdev);
void (*gart_tlb_flush)(struct radeon_device *rdev);
int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); struct {
void (*tlb_flush)(struct radeon_device *rdev);
int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
} gart;
struct { struct {
void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
...@@ -1673,8 +1677,8 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v); ...@@ -1673,8 +1677,8 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
#define radeon_gpu_is_lockup(rdev, cp) (rdev)->asic->gpu_is_lockup((rdev), (cp)) #define radeon_gpu_is_lockup(rdev, cp) (rdev)->asic->gpu_is_lockup((rdev), (cp))
#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
......
drivers/gpu/drm/radeon/radeon_asic.c
View file @ c5b3b850
...@@ -114,13 +114,13 @@ void radeon_agp_disable(struct radeon_device *rdev) ...@@ -114,13 +114,13 @@ void radeon_agp_disable(struct radeon_device *rdev)
rdev->family == CHIP_R423) { rdev->family == CHIP_R423) {
DRM_INFO("Forcing AGP to PCIE mode\n"); DRM_INFO("Forcing AGP to PCIE mode\n");
rdev->flags |= RADEON_IS_PCIE; rdev->flags |= RADEON_IS_PCIE;
rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
} else { } else {
DRM_INFO("Forcing AGP to PCI mode\n"); DRM_INFO("Forcing AGP to PCI mode\n");
rdev->flags |= RADEON_IS_PCI; rdev->flags |= RADEON_IS_PCI;
rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
rdev->asic->gart_set_page = &r100_pci_gart_set_page; rdev->asic->gart.set_page = &r100_pci_gart_set_page;
} }
rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
} }
...@@ -136,8 +136,10 @@ static struct radeon_asic r100_asic = { ...@@ -136,8 +136,10 @@ static struct radeon_asic r100_asic = {
.vga_set_state = &r100_vga_set_state, .vga_set_state = &r100_vga_set_state,
.gpu_is_lockup = &r100_gpu_is_lockup, .gpu_is_lockup = &r100_gpu_is_lockup,
.asic_reset = &r100_asic_reset, .asic_reset = &r100_asic_reset,
.gart_tlb_flush = &r100_pci_gart_tlb_flush, .gart = {
.gart_set_page = &r100_pci_gart_set_page, .tlb_flush = &r100_pci_gart_tlb_flush,
.set_page = &r100_pci_gart_set_page,
},
.ring = { .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = { [RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute, .ib_execute = &r100_ring_ib_execute,
...@@ -204,8 +206,10 @@ static struct radeon_asic r200_asic = { ...@@ -204,8 +206,10 @@ static struct radeon_asic r200_asic = {
.vga_set_state = &r100_vga_set_state, .vga_set_state = &r100_vga_set_state,
.gpu_is_lockup = &r100_gpu_is_lockup, .gpu_is_lockup = &r100_gpu_is_lockup,
.asic_reset = &r100_asic_reset, .asic_reset = &r100_asic_reset,
.gart_tlb_flush = &r100_pci_gart_tlb_flush, .gart = {
.gart_set_page = &r100_pci_gart_set_page, .tlb_flush = &r100_pci_gart_tlb_flush,
.set_page = &r100_pci_gart_set_page,
},
.ring = { .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = { [RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute, .ib_execute = &r100_ring_ib_execute,
...@@ -271,8 +275,10 @@ static struct radeon_asic r300_asic = { ...@@ -271,8 +275,10 @@ static struct radeon_asic r300_asic = {
.vga_set_state = &r100_vga_set_state, .vga_set_state = &r100_vga_set_state,
.gpu_is_lockup = &r300_gpu_is_lockup, .gpu_is_lockup = &r300_gpu_is_lockup,
.asic_reset = &r300_asic_reset, .asic_reset = &r300_asic_reset,
.gart_tlb_flush = &r100_pci_gart_tlb_flush, .gart = {
.gart_set_page = &r100_pci_gart_set_page, .tlb_flush = &r100_pci_gart_tlb_flush,
.set_page = &r100_pci_gart_set_page,
},
.ring = { .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = { [RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute, .ib_execute = &r100_ring_ib_execute,
...@@ -339,8 +345,10 @@ static struct radeon_asic r300_asic_pcie = { ...@@ -339,8 +345,10 @@ static struct radeon_asic r300_asic_pcie = {
.vga_set_state = &r100_vga_set_state, .vga_set_state = &r100_vga_set_state,
.gpu_is_lockup = &r300_gpu_is_lockup, .gpu_is_lockup = &r300_gpu_is_lockup,
.asic_reset = &r300_asic_reset, .asic_reset = &r300_asic_reset,
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush, .gart = {
.gart_set_page = &rv370_pcie_gart_set_page, .tlb_flush = &rv370_pcie_gart_tlb_flush,
.set_page = &rv370_pcie_gart_set_page,
},
.ring = { .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = { [RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute, .ib_execute = &r100_ring_ib_execute,
...@@ -406,8 +414,10 @@ static struct radeon_asic r420_asic = { ...@@ -406,8 +414,10 @@ static struct radeon_asic r420_asic = {
.vga_set_state = &r100_vga_set_state, .vga_set_state = &r100_vga_set_state,
.gpu_is_lockup = &r300_gpu_is_lockup, .gpu_is_lockup = &r300_gpu_is_lockup,
.asic_reset = &r300_asic_reset, .asic_reset = &r300_asic_reset,
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush, .gart = {
.gart_set_page = &rv370_pcie_gart_set_page, .tlb_flush = &rv370_pcie_gart_tlb_flush,
.set_page = &rv370_pcie_gart_set_page,
},
.ring = { .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = { [RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute, .ib_execute = &r100_ring_ib_execute,
...@@ -474,8 +484,10 @@ static struct radeon_asic rs400_asic = { ...@@ -474,8 +484,10 @@ static struct radeon_asic rs400_asic = {
.vga_set_state = &r100_vga_set_state, .vga_set_state = &r100_vga_set_state,
.gpu_is_lockup = &r300_gpu_is_lockup, .gpu_is_lockup = &r300_gpu_is_lockup,
.asic_reset = &r300_asic_reset, .asic_reset = &r300_asic_reset,
.gart_tlb_flush = &rs400_gart_tlb_flush, .gart = {
.gart_set_page = &rs400_gart_set_page, .tlb_flush = &rs400_gart_tlb_flush,
.set_page = &rs400_gart_set_page,
},
.ring = { .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = { [RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute, .ib_execute = &r100_ring_ib_execute,
...@@ -542,8 +554,10 @@ static struct radeon_asic rs600_asic = { ...@@ -542,8 +554,10 @@ static struct radeon_asic rs600_asic = {
.vga_set_state = &r100_vga_set_state, .vga_set_state = &r100_vga_set_state,
.gpu_is_lockup = &r300_gpu_is_lockup, .gpu_is_lockup = &r300_gpu_is_lockup,
.asic_reset = &rs600_asic_reset, .asic_reset = &rs600_asic_reset,
.gart_tlb_flush = &rs600_gart_tlb_flush, .gart = {
.gart_set_page = &rs600_gart_set_page, .tlb_flush = &rs600_gart_tlb_flush,
.set_page = &rs600_gart_set_page,
},
.ring = { .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = { [RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute, .ib_execute = &r100_ring_ib_execute,
...@@ -610,8 +624,10 @@ static struct radeon_asic rs690_asic = { ...@@ -610,8 +624,10 @@ static struct radeon_asic rs690_asic = {
.vga_set_state = &r100_vga_set_state, .vga_set_state = &r100_vga_set_state,
.gpu_is_lockup = &r300_gpu_is_lockup, .gpu_is_lockup = &r300_gpu_is_lockup,
.asic_reset = &rs600_asic_reset, .asic_reset = &rs600_asic_reset,
.gart_tlb_flush = &rs400_gart_tlb_flush, .gart = {
.gart_set_page = &rs400_gart_set_page, .tlb_flush = &rs400_gart_tlb_flush,
.set_page = &rs400_gart_set_page,
},
.ring = { .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = { [RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute, .ib_execute = &r100_ring_ib_execute,
...@@ -678,8 +694,10 @@ static struct radeon_asic rv515_asic = { ...@@ -678,8 +694,10 @@ static struct radeon_asic rv515_asic = {
.vga_set_state = &r100_vga_set_state, .vga_set_state = &r100_vga_set_state,
.gpu_is_lockup = &r300_gpu_is_lockup, .gpu_is_lockup = &r300_gpu_is_lockup,
.asic_reset = &rs600_asic_reset, .asic_reset = &rs600_asic_reset,
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush, .gart = {
.gart_set_page = &rv370_pcie_gart_set_page, .tlb_flush = &rv370_pcie_gart_tlb_flush,
.set_page = &rv370_pcie_gart_set_page,
},
.ring = { .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = { [RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute, .ib_execute = &r100_ring_ib_execute,
...@@ -746,8 +764,10 @@ static struct radeon_asic r520_asic = { ...@@ -746,8 +764,10 @@ static struct radeon_asic r520_asic = {
.vga_set_state = &r100_vga_set_state, .vga_set_state = &r100_vga_set_state,
.gpu_is_lockup = &r300_gpu_is_lockup, .gpu_is_lockup = &r300_gpu_is_lockup,
.asic_reset = &rs600_asic_reset, .asic_reset = &rs600_asic_reset,
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush, .gart = {
.gart_set_page = &rv370_pcie_gart_set_page, .tlb_flush = &rv370_pcie_gart_tlb_flush,
.set_page = &rv370_pcie_gart_set_page,
},
.ring = { .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = { [RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute, .ib_execute = &r100_ring_ib_execute,
...@@ -814,8 +834,10 @@ static struct radeon_asic r600_asic = { ...@@ -814,8 +834,10 @@ static struct radeon_asic r600_asic = {
.vga_set_state = &r600_vga_set_state, .vga_set_state = &r600_vga_set_state,
.gpu_is_lockup = &r600_gpu_is_lockup, .gpu_is_lockup = &r600_gpu_is_lockup,
.asic_reset = &r600_asic_reset, .asic_reset = &r600_asic_reset,
.gart_tlb_flush = &r600_pcie_gart_tlb_flush, .gart = {
.gart_set_page = &rs600_gart_set_page, .tlb_flush = &r600_pcie_gart_tlb_flush,
.set_page = &rs600_gart_set_page,
},
.ring = { .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = { [RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r600_ring_ib_execute, .ib_execute = &r600_ring_ib_execute,
...@@ -881,8 +903,10 @@ static struct radeon_asic rs780_asic = { ...@@ -881,8 +903,10 @@ static struct radeon_asic rs780_asic = {
.gpu_is_lockup = &r600_gpu_is_lockup, .gpu_is_lockup = &r600_gpu_is_lockup,
.vga_set_state = &r600_vga_set_state, .vga_set_state = &r600_vga_set_state,
.asic_reset = &r600_asic_reset, .asic_reset = &r600_asic_reset,
.gart_tlb_flush = &r600_pcie_gart_tlb_flush, .gart = {
.gart_set_page = &rs600_gart_set_page, .tlb_flush = &r600_pcie_gart_tlb_flush,
.set_page = &rs600_gart_set_page,
},
.ring = { .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = { [RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r600_ring_ib_execute, .ib_execute = &r600_ring_ib_execute,
...@@ -948,8 +972,10 @@ static struct radeon_asic rv770_asic = { ...@@ -948,8 +972,10 @@ static struct radeon_asic rv770_asic = {
.asic_reset = &r600_asic_reset, .asic_reset = &r600_asic_reset,
.gpu_is_lockup = &r600_gpu_is_lockup, .gpu_is_lockup = &r600_gpu_is_lockup,
.vga_set_state = &r600_vga_set_state, .vga_set_state = &r600_vga_set_state,
.gart_tlb_flush = &r600_pcie_gart_tlb_flush, .gart = {
.gart_set_page = &rs600_gart_set_page, .tlb_flush = &r600_pcie_gart_tlb_flush,
.set_page = &rs600_gart_set_page,
},
.ring = { .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = { [RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r600_ring_ib_execute, .ib_execute = &r600_ring_ib_execute,
...@@ -1015,8 +1041,10 @@ static struct radeon_asic evergreen_asic = { ...@@ -1015,8 +1041,10 @@ static struct radeon_asic evergreen_asic = {
.gpu_is_lockup = &evergreen_gpu_is_lockup, .gpu_is_lockup = &evergreen_gpu_is_lockup,
.asic_reset = &evergreen_asic_reset, .asic_reset = &evergreen_asic_reset,
.vga_set_state = &r600_vga_set_state, .vga_set_state = &r600_vga_set_state,
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, .gart = {
.gart_set_page = &rs600_gart_set_page, .tlb_flush = &evergreen_pcie_gart_tlb_flush,
.set_page = &rs600_gart_set_page,
},
.ring = { .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = { [RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &evergreen_ring_ib_execute, .ib_execute = &evergreen_ring_ib_execute,
...@@ -1082,8 +1110,10 @@ static struct radeon_asic sumo_asic = { ...@@ -1082,8 +1110,10 @@ static struct radeon_asic sumo_asic = {
.gpu_is_lockup = &evergreen_gpu_is_lockup, .gpu_is_lockup = &evergreen_gpu_is_lockup,
.asic_reset = &evergreen_asic_reset, .asic_reset = &evergreen_asic_reset,
.vga_set_state = &r600_vga_set_state, .vga_set_state = &r600_vga_set_state,
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, .gart = {
.gart_set_page = &rs600_gart_set_page, .tlb_flush = &evergreen_pcie_gart_tlb_flush,
.set_page = &rs600_gart_set_page,
},
.ring = { .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = { [RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &evergreen_ring_ib_execute, .ib_execute = &evergreen_ring_ib_execute,
...@@ -1149,8 +1179,10 @@ static struct radeon_asic btc_asic = { ...@@ -1149,8 +1179,10 @@ static struct radeon_asic btc_asic = {
.gpu_is_lockup = &evergreen_gpu_is_lockup, .gpu_is_lockup = &evergreen_gpu_is_lockup,
.asic_reset = &evergreen_asic_reset, .asic_reset = &evergreen_asic_reset,
.vga_set_state = &r600_vga_set_state, .vga_set_state = &r600_vga_set_state,
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, .gart = {
.gart_set_page = &rs600_gart_set_page, .tlb_flush = &evergreen_pcie_gart_tlb_flush,
.set_page = &rs600_gart_set_page,
},
.ring = { .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = { [RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &evergreen_ring_ib_execute, .ib_execute = &evergreen_ring_ib_execute,
...@@ -1226,8 +1258,10 @@ static struct radeon_asic cayman_asic = { ...@@ -1226,8 +1258,10 @@ static struct radeon_asic cayman_asic = {
.gpu_is_lockup = &cayman_gpu_is_lockup, .gpu_is_lockup = &cayman_gpu_is_lockup,
.asic_reset = &cayman_asic_reset, .asic_reset = &cayman_asic_reset,
.vga_set_state = &r600_vga_set_state, .vga_set_state = &r600_vga_set_state,
.gart_tlb_flush = &cayman_pcie_gart_tlb_flush, .gart = {
.gart_set_page = &rs600_gart_set_page, .tlb_flush = &cayman_pcie_gart_tlb_flush,
.set_page = &rs600_gart_set_page,
},
.ring = { .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = { [RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &cayman_ring_ib_execute, .ib_execute = &cayman_ring_ib_execute,
......
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