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Commit c6265ff5 authored by Alan Cox's avatar Alan Cox Committed by Dave Airlie
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gma500: rework register stuff sanely 

Rework registers handling to prepare for Medfield.
Signed-off-by: default avatarAlan Cox <alan@linux.intel.com>
[split out from a single big patch]
Signed-off-by: default avatarKirill A. Shutemov <kirill.shutemov@linux.intel.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent c715bc1b
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Showing with 148 additions and 138 deletions
drivers/gpu/drm/gma500/cdv_intel_display.c
View file @ c6265ff5
......@@ -968,7 +968,7 @@ void cdv_intel_crtc_load_lut(struct drm_crtc *crtc)
gma_power_end(dev);
} else {
for (i = 0; i < 256; i++) {
dev_priv->regs.save_palette_a[i] =
dev_priv->regs.psb.save_palette_a[i] =
((psb_intel_crtc->lut_r[i] +
psb_intel_crtc->lut_adj[i]) << 16) |
((psb_intel_crtc->lut_g[i] +
......@@ -1338,19 +1338,20 @@ static int cdv_intel_crtc_clock_get(struct drm_device *dev,
gma_power_end(dev);
} else {
dpll = (pipe == 0) ?
dev_priv->regs.saveDPLL_A : dev_priv->regs.saveDPLL_B;
dev_priv->regs.psb.saveDPLL_A :
dev_priv->regs.psb.saveDPLL_B;
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
fp = (pipe == 0) ?
dev_priv->regs.saveFPA0 :
dev_priv->regs.saveFPB0;
dev_priv->regs.psb.saveFPA0 :
dev_priv->regs.psb.saveFPB0;
else
fp = (pipe == 0) ?
dev_priv->regs.saveFPA1 :
dev_priv->regs.saveFPB1;
dev_priv->regs.psb.saveFPA1 :
dev_priv->regs.psb.saveFPB1;
is_lvds = (pipe == 1) &&
(dev_priv->regs.saveLVDS & LVDS_PORT_EN);
(dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);
}
clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
......@@ -1420,17 +1421,17 @@ struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
gma_power_end(dev);
} else {
htot = (pipe == 0) ?
dev_priv->regs.saveHTOTAL_A :
dev_priv->regs.saveHTOTAL_B;
dev_priv->regs.psb.saveHTOTAL_A :
dev_priv->regs.psb.saveHTOTAL_B;
hsync = (pipe == 0) ?
dev_priv->regs.saveHSYNC_A :
dev_priv->regs.saveHSYNC_B;
dev_priv->regs.psb.saveHSYNC_A :
dev_priv->regs.psb.saveHSYNC_B;
vtot = (pipe == 0) ?
dev_priv->regs.saveVTOTAL_A :
dev_priv->regs.saveVTOTAL_B;
dev_priv->regs.psb.saveVTOTAL_A :
dev_priv->regs.psb.saveVTOTAL_B;
vsync = (pipe == 0) ?
dev_priv->regs.saveVSYNC_A :
dev_priv->regs.saveVSYNC_B;
dev_priv->regs.psb.saveVSYNC_A :
dev_priv->regs.psb.saveVSYNC_B;
}
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
......
drivers/gpu/drm/gma500/oaktrail_device.c
View file @ c6265ff5
This diff is collapsed.
drivers/gpu/drm/gma500/oaktrail_hdmi.c
View file @ c6265ff5
......@@ -766,7 +766,7 @@ void oaktrail_hdmi_save(struct drm_device *dev)
{
struct drm_psb_private *dev_priv = dev->dev_private;
struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
struct psb_state *regs = &dev_priv->regs;
struct psb_state *regs = &dev_priv->regs.psb;
int i;
/* dpll */
......@@ -818,7 +818,7 @@ void oaktrail_hdmi_restore(struct drm_device *dev)
{
struct drm_psb_private *dev_priv = dev->dev_private;
struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
struct psb_state *regs = &dev_priv->regs;
struct psb_state *regs = &dev_priv->regs.psb;
int i;
/* dpll */
......
drivers/gpu/drm/gma500/psb_device.c
View file @ c6265ff5
......@@ -177,7 +177,7 @@ static int psb_save_display_registers(struct drm_device *dev)
struct drm_psb_private *dev_priv = dev->dev_private;
struct drm_crtc *crtc;
struct drm_connector *connector;
struct psb_state *regs = &dev_priv->regs;
struct psb_state *regs = &dev_priv->regs.psb;
/* Display arbitration control + watermarks */
regs->saveDSPARB = PSB_RVDC32(DSPARB);
......@@ -214,7 +214,7 @@ static int psb_restore_display_registers(struct drm_device *dev)
struct drm_psb_private *dev_priv = dev->dev_private;
struct drm_crtc *crtc;
struct drm_connector *connector;
struct psb_state *regs = &dev_priv->regs;
struct psb_state *regs = &dev_priv->regs.psb;
/* Display arbitration + watermarks */
PSB_WVDC32(regs->saveDSPARB, DSPARB);
......
drivers/gpu/drm/gma500/psb_drv.h
View file @ c6265ff5
......@@ -337,8 +337,6 @@ struct psb_state {
uint32_t savePFIT_CONTROL;
uint32_t savePaletteA[256];
uint32_t savePaletteB[256];
uint32_t saveBLC_PWM_CTL2;
uint32_t saveBLC_PWM_CTL;
uint32_t saveCLOCKGATING;
uint32_t saveDSPARB;
uint32_t saveDSPATILEOFF;
......@@ -350,8 +348,6 @@ struct psb_state {
uint32_t savePP_ON_DELAYS;
uint32_t savePP_OFF_DELAYS;
uint32_t savePP_DIVISOR;
uint32_t saveBSM;
uint32_t saveVBT;
uint32_t saveBCLRPAT_A;
uint32_t saveBCLRPAT_B;
uint32_t saveDSPALINOFF;
......@@ -393,6 +389,16 @@ struct psb_state {
uint32_t savePWM_CONTROL_LOGIC;
};
struct psb_save_area {
uint32_t saveBSM;
uint32_t saveVBT;
union {
struct psb_state psb;
};
uint32_t saveBLC_PWM_CTL2;
uint32_t saveBLC_PWM_CTL;
};
struct psb_ops;
#define PSB_NUM_PIPE 3
......@@ -520,7 +526,9 @@ struct drm_psb_private {
/*
* Register state
*/
struct psb_state regs;
struct psb_save_area regs;
/* MSI reg save */
uint32_t msi_addr;
uint32_t msi_data;
......
drivers/gpu/drm/gma500/psb_intel_display.c
View file @ c6265ff5
......@@ -845,7 +845,7 @@ void psb_intel_crtc_load_lut(struct drm_crtc *crtc)
gma_power_end(dev);
} else {
for (i = 0; i < 256; i++) {
dev_priv->regs.save_palette_a[i] =
dev_priv->regs.psb.save_palette_a[i] =
((psb_intel_crtc->lut_r[i] +
psb_intel_crtc->lut_adj[i]) << 16) |
((psb_intel_crtc->lut_g[i] +
......@@ -1141,18 +1141,19 @@ static int psb_intel_crtc_clock_get(struct drm_device *dev,
gma_power_end(dev);
} else {
dpll = (pipe == 0) ?
dev_priv->regs.saveDPLL_A : dev_priv->regs.saveDPLL_B;
dev_priv->regs.psb.saveDPLL_A :
dev_priv->regs.psb.saveDPLL_B;
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
fp = (pipe == 0) ?
dev_priv->regs.saveFPA0 :
dev_priv->regs.saveFPB0;
dev_priv->regs.psb.saveFPA0 :
dev_priv->regs.psb.saveFPB0;
else
fp = (pipe == 0) ?
dev_priv->regs.saveFPA1 :
dev_priv->regs.saveFPB1;
dev_priv->regs.psb.saveFPA1 :
dev_priv->regs.psb.saveFPB1;
is_lvds = (pipe == 1) && (dev_priv->regs.saveLVDS &
is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS &
LVDS_PORT_EN);
}
......@@ -1219,17 +1220,17 @@ struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
gma_power_end(dev);
} else {
htot = (pipe == 0) ?
dev_priv->regs.saveHTOTAL_A :
dev_priv->regs.saveHTOTAL_B;
dev_priv->regs.psb.saveHTOTAL_A :
dev_priv->regs.psb.saveHTOTAL_B;
hsync = (pipe == 0) ?
dev_priv->regs.saveHSYNC_A :
dev_priv->regs.saveHSYNC_B;
dev_priv->regs.psb.saveHSYNC_A :
dev_priv->regs.psb.saveHSYNC_B;
vtot = (pipe == 0) ?
dev_priv->regs.saveVTOTAL_A :
dev_priv->regs.saveVTOTAL_B;
dev_priv->regs.psb.saveVTOTAL_A :
dev_priv->regs.psb.saveVTOTAL_B;
vsync = (pipe == 0) ?
dev_priv->regs.saveVSYNC_A :
dev_priv->regs.saveVSYNC_B;
dev_priv->regs.psb.saveVSYNC_A :
dev_priv->regs.psb.saveVSYNC_B;
}
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
......
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