[PATCH] sparc32: fix for HyperSPARC DMA errors

I found a solution for the HyperSPARC DMA problems in 2.6.  This allows my
SS20 with HyperSPARCs to boot to single user.  It's not efficient, but I
hope it points out whats needed for a proper fix.  Seems that the iotlb
entries need to flushed to ram or uncached since the iommu changes between
2.5.60 and 2.5.70.

The second part seems to be needed to allow consistent sbus dma mappings to
be cached on HyperSPARC.  I have also tested this change on 2.4.27 with no
noticeable difference.
Acked-by: William Irwin <wli@holomorphy.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

arch/sparc/mm/iommu.c

@@ -173,6 +173,7 @@ static u32 iommu_get_one(struct page *page, int npages, struct sbus_bus *sbus)
 	}
 
 	iommu_viking_flush_iotlb(iopte0, npages);
+	flush_cache_all(); // hack to fix dma errors with hypersparc
 
 	return busa0;
 }

arch/sparc/mm/srmmu.c

@@ -1463,6 +1463,7 @@ static void __init poke_hypersparc(void)
 static void __init init_hypersparc(void)
 {
 	srmmu_name = "ROSS HyperSparc";
+	srmmu_modtype = HyperSparc;
 
 	init_vac_layout();