Commit c71ad41c authored by Feras Daoud's avatar Feras Daoud Committed by Saeed Mahameed

net/mlx5: FW tracer, events handling

The tracer has one event, event 0x26, with two subtypes:
- Subtype 0: Ownership change
- Subtype 1: Traces available

An ownership change occurs in the following cases:
1- Owner releases his ownership, in this case, an event will be
sent to inform others to reattempt acquire ownership.
2- Ownership was taken by a higher priority tool, in this case
the owner should understand that it lost ownership, and go through
tear down flow.

The second subtype indicates that there are traces in the trace buffer,
in this case, the driver polls the tracer buffer for new traces, parse
them and prepares the messages for printing.

The HW starts tracing from the first address in the tracer buffer.
Driver receives an event notifying that new trace block exists.
HW posts a timestamp event at the last 8B of every 256B block.
Comparing the timestamp to the last handled timestamp would indicate
that this is a new trace block. Once the new timestamp is detected,
the entire block is considered valid.

Block validation and parsing, should be done after copying the current
block to a different location, in order to avoid block overwritten
during processing.
Signed-off-by: default avatarFeras Daoud <ferasda@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
parent e9cad2ce
...@@ -43,6 +43,9 @@ ...@@ -43,6 +43,9 @@
#define TRACER_BUFFER_CHUNK 4096 #define TRACER_BUFFER_CHUNK 4096
#define TRACE_BUFFER_SIZE_BYTE (TRACER_BUFFER_PAGE_NUM * TRACER_BUFFER_CHUNK) #define TRACE_BUFFER_SIZE_BYTE (TRACER_BUFFER_PAGE_NUM * TRACER_BUFFER_CHUNK)
#define TRACER_BLOCK_SIZE_BYTE 256
#define TRACES_PER_BLOCK 32
struct mlx5_fw_tracer { struct mlx5_fw_tracer {
struct mlx5_core_dev *dev; struct mlx5_core_dev *dev;
bool owner; bool owner;
...@@ -69,8 +72,11 @@ struct mlx5_fw_tracer { ...@@ -69,8 +72,11 @@ struct mlx5_fw_tracer {
dma_addr_t dma; dma_addr_t dma;
u32 size; u32 size;
struct mlx5_core_mkey mkey; struct mlx5_core_mkey mkey;
u32 consumer_index;
} buff; } buff;
u64 last_timestamp;
struct work_struct handle_traces_work;
}; };
enum mlx5_fw_tracer_ownership_state { enum mlx5_fw_tracer_ownership_state {
...@@ -78,7 +84,70 @@ enum mlx5_fw_tracer_ownership_state { ...@@ -78,7 +84,70 @@ enum mlx5_fw_tracer_ownership_state {
MLX5_FW_TRACER_ACQUIRE_OWNERSHIP, MLX5_FW_TRACER_ACQUIRE_OWNERSHIP,
}; };
enum tracer_ctrl_fields_select {
TRACE_STATUS = 1 << 0,
};
enum tracer_event_type {
TRACER_EVENT_TYPE_STRING,
TRACER_EVENT_TYPE_TIMESTAMP = 0xFF,
TRACER_EVENT_TYPE_UNRECOGNIZED,
};
enum tracing_mode {
TRACE_TO_MEMORY = 1 << 0,
};
struct tracer_timestamp_event {
u64 timestamp;
u8 unreliable;
};
struct tracer_string_event {
u32 timestamp;
u32 tmsn;
u32 tdsn;
u32 string_param;
};
struct tracer_event {
bool lost_event;
u32 type;
u8 event_id;
union {
struct tracer_string_event string_event;
struct tracer_timestamp_event timestamp_event;
};
};
struct mlx5_ifc_tracer_event_bits {
u8 lost[0x1];
u8 timestamp[0x7];
u8 event_id[0x8];
u8 event_data[0x30];
};
struct mlx5_ifc_tracer_string_event_bits {
u8 lost[0x1];
u8 timestamp[0x7];
u8 event_id[0x8];
u8 tmsn[0xd];
u8 tdsn[0x3];
u8 string_param[0x20];
};
struct mlx5_ifc_tracer_timestamp_event_bits {
u8 timestamp7_0[0x8];
u8 event_id[0x8];
u8 urts[0x3];
u8 timestamp52_40[0xd];
u8 timestamp39_8[0x20];
};
struct mlx5_fw_tracer *mlx5_fw_tracer_create(struct mlx5_core_dev *dev); struct mlx5_fw_tracer *mlx5_fw_tracer_create(struct mlx5_core_dev *dev);
int mlx5_fw_tracer_init(struct mlx5_fw_tracer *tracer);
void mlx5_fw_tracer_cleanup(struct mlx5_fw_tracer *tracer);
void mlx5_fw_tracer_destroy(struct mlx5_fw_tracer *tracer); void mlx5_fw_tracer_destroy(struct mlx5_fw_tracer *tracer);
void mlx5_fw_tracer_event(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe) { return; }
#endif #endif
...@@ -40,6 +40,7 @@ ...@@ -40,6 +40,7 @@
#include "mlx5_core.h" #include "mlx5_core.h"
#include "fpga/core.h" #include "fpga/core.h"
#include "eswitch.h" #include "eswitch.h"
#include "diag/fw_tracer.h"
enum { enum {
MLX5_EQE_SIZE = sizeof(struct mlx5_eqe), MLX5_EQE_SIZE = sizeof(struct mlx5_eqe),
...@@ -168,6 +169,8 @@ static const char *eqe_type_str(u8 type) ...@@ -168,6 +169,8 @@ static const char *eqe_type_str(u8 type)
return "MLX5_EVENT_TYPE_FPGA_QP_ERROR"; return "MLX5_EVENT_TYPE_FPGA_QP_ERROR";
case MLX5_EVENT_TYPE_GENERAL_EVENT: case MLX5_EVENT_TYPE_GENERAL_EVENT:
return "MLX5_EVENT_TYPE_GENERAL_EVENT"; return "MLX5_EVENT_TYPE_GENERAL_EVENT";
case MLX5_EVENT_TYPE_DEVICE_TRACER:
return "MLX5_EVENT_TYPE_DEVICE_TRACER";
default: default:
return "Unrecognized event"; return "Unrecognized event";
} }
...@@ -576,6 +579,11 @@ static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr) ...@@ -576,6 +579,11 @@ static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr)
case MLX5_EVENT_TYPE_GENERAL_EVENT: case MLX5_EVENT_TYPE_GENERAL_EVENT:
general_event_handler(dev, eqe); general_event_handler(dev, eqe);
break; break;
case MLX5_EVENT_TYPE_DEVICE_TRACER:
mlx5_fw_tracer_event(dev, eqe);
break;
default: default:
mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n", mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
eqe->type, eq->eqn); eqe->type, eq->eqn);
...@@ -853,6 +861,9 @@ int mlx5_start_eqs(struct mlx5_core_dev *dev) ...@@ -853,6 +861,9 @@ int mlx5_start_eqs(struct mlx5_core_dev *dev)
if (MLX5_CAP_GEN(dev, temp_warn_event)) if (MLX5_CAP_GEN(dev, temp_warn_event))
async_event_mask |= (1ull << MLX5_EVENT_TYPE_TEMP_WARN_EVENT); async_event_mask |= (1ull << MLX5_EVENT_TYPE_TEMP_WARN_EVENT);
if (MLX5_CAP_MCAM_REG(dev, tracer_registers))
async_event_mask |= (1ull << MLX5_EVENT_TYPE_DEVICE_TRACER);
err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD, err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD, MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
"mlx5_cmd_eq", MLX5_EQ_TYPE_ASYNC); "mlx5_cmd_eq", MLX5_EQ_TYPE_ASYNC);
......
...@@ -332,6 +332,13 @@ enum mlx5_event { ...@@ -332,6 +332,13 @@ enum mlx5_event {
MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21,
MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26,
};
enum {
MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0,
MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1,
}; };
enum { enum {
......
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