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Merge tag 'qcom-arm64-for-5.16' of... 

Merge tag 'qcom-arm64-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm ARM64 dts updates for v5.16

MSM8916 gained some DT cleanup fixes. The Dragonboard 410c gains updated
firmware paths to the device specific firmware for modem and WiFi, to
allow these to be pushed to linux-next. The Longcheer L8150 gains extcon
support and the interrupt configuration for the accelerometer and
magnetometer are corrected.

MSM8998 gained descriptions for the multimedia clock controller and
iommu, as well as the GPU and its dedicated IOMMU. The QFPROM node is
updated to access the CRC corrected value space, the white LED (for
backlight) found in PMI8998 is described and GCC gains references to the
missing XO and sleep_clk reference clocks.
On top of this initial support for the Fxtec Pro1 QX1000 is added and
then the Sony Xperia XZ1, Xperia XZ1 Compact and the Xperia XZ Premium,
with USB, touchscreen, SDHCI, Bluetooth and vibrator supported.

The Xiaomi Mi 5 and Xiaomi Mi Note 2, based on the MSM8996 platform was
added, with support for frame buffer, GPU, audio, video encoder/decoder
and touchscreen.

The USB controller and PHY found in IPA6018 is described to provide USB
support. IPQ8074 gains a description of the SPMI controller.

The highlight on SC7180 is the introduction of the just released
"Homestar" device.  CPU power coefficients are corrected based on
measurements, IMEM is described to ensure that remoteproc relocation
information is carried to post mortem debug tools and a few smaller
fixes are introduced.

The SC7280 gains QSPI, low speed (i2c/spi/uart), GPU, thermal zones,
modem, CPU topology and updated memory map.

On SDM845 the "Limits hardware" is described and increases the
throttling temperature of the hardware from ~70C to 95C, with up to 30%
improvement in benchmarks as result.  Relying on hardware throttling and
thermal pressure, the CPU cooling devices are dropped.
The power for the second WiFi channel is properly described for the
Lenovo Yoga C630, to ensure they are both powered.

reboot-modes are defined for the PM660 PMIC, found in SDM630 and SDM660.

Initial support for the Snapdragon 690 (aka SM6350) is introduced, with
support for clocks, regulators, pinctrl, storage, thermal sensors, USB,
SMMU and CPUfreq. On top of this support for the Sony Xperia 10 III is
introduced.

* tag 'qcom-arm64-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (99 commits)
  arm64: dts: qcom: sdm630-nile: Correct regulator label name
  arm64: dts: qcom: sm6125: Improve indentation of multiline properties
  arm64: dts: qcom: msm8916-longcheer-l8150: Use &pm8916_usbin extcon
  arm64: dts: qcom: pm8916: Add pm8941-misc extcon for USB detection
  arm64: dts: qcom: pm8916: Remove wrong reg-names for rtc@6000
  arm64: dts: qcom: sc7280: Update Q6V5 MSS node
  arm64: dts: qcom: sc7280: Add Q6V5 MSS node
  arm64: dts: qcom: sc7280: Add nodes to boot modem
  arm64: dts: qcom: sc7280: Add/Delete/Update reserved memory nodes
  arm64: dts: qcom: sc7280: Update reserved memory map
  arm64: dts: qcom: msm8998-fxtec-pro1: Add tlmm keyboard keys
  arm64: dts: qcom: msm8998-fxtec-pro1: Add Goodix GT9286 touchscreen
  arm64: dts: qcom: msm8998-fxtec-pro1: Add physical keyboard leds
  arm64: dts: qcom: Add support for MSM8998 F(x)tec Pro1 QX1000
  arm64: dts: qcom: msm8916: Fix Secondary MI2S bit clock
  arm64: dts: qcom: msm8916-longcheer-l8150: Add missing sensor interrupts
  arm64: dts: qcom: sc7180: Add IMEM and pil info regions
  arm64: dts: qcom: pm6150l: Add missing include
  arm64: dts: qcom: sm6350: Add device tree for Sony Xperia 10 III
  arm64: dts: qcom: sm6350: Add apps_smmu and assign iommus prop to USB1
  ...

Link: https://lore.kernel.org/r/20211012231155.1036519-1-bjorn.andersson@linaro.orgSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 878e26d3 c22441a7
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Showing with 7534 additions and 1137 deletions
Documentation/devicetree/bindings/arm/cpus.yaml
View file @ c7613530
......@@ -171,6 +171,7 @@ properties:
- qcom,kryo385
- qcom,kryo468
- qcom,kryo485
- qcom,kryo560
- qcom,kryo685
- qcom,scorpion
......
arch/arm64/boot/dts/qcom/Makefile
View file @ c7613530
......@@ -33,12 +33,18 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8996-pmi8996-sony-xperia-tone-keyaki.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-dora.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-kagura.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-keyaki.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-gemini.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-scorpio.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-fxtec-pro1.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-oneplus-cheeseburger.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-oneplus-dumpling.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-lilac.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb
......@@ -48,6 +54,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb
......@@ -84,6 +92,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb
......
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
View file @ c7613530
......@@ -305,6 +305,12 @@ &mdss {
status = "okay";
};
&mpss {
status = "okay";
firmware-name = "qcom/msm8916/mba.mbn", "qcom/msm8916/modem.mbn";
};
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
......@@ -312,6 +318,8 @@ &pm8916_resin {
&pronto {
status = "okay";
firmware-name = "qcom/msm8916/wcnss.mbn";
};
&sdhc_1 {
......@@ -394,6 +402,10 @@ &wcd_codec {
qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
};
&wcnss_ctrl {
firmware-name = "qcom/msm8916/WCNSS_qcom_wlan_nv.bin";
};
/* Enable CoreSight */
&cti0 { status = "okay"; };
&cti1 { status = "okay"; };
......
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
View file @ c7613530
......@@ -148,9 +148,6 @@ &blsp1_spi1 {
&blsp1_uart2 {
label = "BT-UART";
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart2_default>;
pinctrl-1 = <&blsp1_uart2_sleep>;
bluetooth {
compatible = "qcom,qca6174-bt";
......@@ -437,32 +434,6 @@ config {
};
};
blsp1_uart2_default: blsp1_uart2_default {
mux {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "blsp_uart2";
};
config {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
drive-strength = <16>;
bias-disable;
};
};
blsp1_uart2_sleep: blsp1_uart2_sleep {
mux {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "gpio";
};
config {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
drive-strength = <2>;
bias-disable;
};
};
hdmi_hpd_active: hdmi_hpd_active {
mux {
pins = "gpio34";
......
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View file @ c7613530
......@@ -200,7 +200,7 @@ cryptobam: dma-controller@704000 {
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <1>;
qcom,controlled-remotely = <1>;
qcom,controlled-remotely;
qcom,config-pipe-trust-reg = <0>;
};
......@@ -671,6 +671,89 @@ dwc_1: usb@7000000 {
};
};
ssphy_0: ssphy@78000 {
compatible = "qcom,ipq6018-qmp-usb3-phy";
reg = <0x0 0x78000 0x0 0x1C4>;
#address-cells = <2>;
#size-cells = <2>;
#clock-cells = <1>;
ranges;
clocks = <&gcc GCC_USB0_AUX_CLK>,
<&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
clock-names = "aux", "cfg_ahb", "ref";
resets = <&gcc GCC_USB0_PHY_BCR>,
<&gcc GCC_USB3PHY_0_PHY_BCR>;
reset-names = "phy","common";
status = "disabled";
usb0_ssphy: lane@78200 {
reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
<0x0 0x00078400 0x0 0x200>, /* Rx */
<0x0 0x00078800 0x0 0x1F8>, /* PCS */
<0x0 0x00078600 0x0 0x044>; /* PCS misc */
#phy-cells = <0>;
clocks = <&gcc GCC_USB0_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "gcc_usb0_pipe_clk_src";
};
};
qusb_phy_0: qusb@79000 {
compatible = "qcom,ipq6018-qusb2-phy";
reg = <0x0 0x079000 0x0 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
<&xo>;
clock-names = "cfg_ahb", "ref";
resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
status = "disabled";
};
usb3: usb3@8A00000 {
compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
reg = <0x0 0x8AF8800 0x0 0x400>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
<&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_USB0_SLEEP_CLK>,
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
clock-names = "sys_noc_axi",
"master",
"sleep",
"mock_utmi";
assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
<&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
assigned-clock-rates = <133330000>,
<133330000>,
<20000000>;
resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
dwc_0: usb@8A00000 {
compatible = "snps,dwc3";
reg = <0x0 0x8A00000 0x0 0xcd00>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_0>, <&usb0_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
tx-fifo-resize;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
snps,ref-clock-period-ns = <0x32>;
dr_mode = "host";
};
};
};
wcss: wcss-smp2p {
......
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View file @ c7613530
......@@ -212,7 +212,7 @@ prng: rng@e3000 {
status = "disabled";
};
cryptobam: dma@704000 {
cryptobam: dma-controller@704000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x00704000 0x20000>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
......@@ -220,7 +220,7 @@ cryptobam: dma@704000 {
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <1>;
qcom,controlled-remotely = <1>;
qcom,controlled-remotely;
status = "disabled";
};
......@@ -293,6 +293,25 @@ gcc: gcc@1800000 {
#reset-cells = <0x1>;
};
spmi_bus: spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0200f000 0x001000>,
<0x02400000 0x800000>,
<0x02c00000 0x800000>,
<0x03800000 0x200000>,
<0x0200a000 0x000700>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
cell-index = <0>;
};
sdhc_1: sdhci@7824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x500>, <0x7824000 0x800>;
......
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts
View file @ c7613530
......@@ -30,14 +30,6 @@ wcnss_mem: wcnss@8b600000 {
};
};
// FIXME: Use extcon device provided by charger driver when available
usb_vbus: usb-vbus {
compatible = "linux,extcon-usb-gpio";
vbus-gpio = <&msmgpio 62 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_vbus_default>;
};
gpio-keys {
compatible = "gpio-keys";
......@@ -121,9 +113,21 @@ &blsp_i2c2 {
status = "okay";
accelerometer@10 {
compatible = "bosch,bmc150_accel";
compatible = "bosch,bmc156_accel";
reg = <0x10>;
/*
* For some reason the interrupt line is usually not connected
* to the BMC156. However, there are two pads next to the chip
* that can be shorted to make it work if needed.
*
* interrupt-parent = <&msmgpio>;
* interrupts = <116 IRQ_TYPE_EDGE_RISING>;
*/
pinctrl-names = "default";
pinctrl-0 = <&accel_int_default>;
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l6>;
......@@ -133,9 +137,15 @@ accelerometer@10 {
};
magnetometer@12 {
compatible = "bosch,bmc150_magn";
compatible = "bosch,bmc156_magn";
reg = <0x12>;
interrupt-parent = <&msmgpio>;
interrupts = <113 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&magn_int_default>;
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l6>;
};
......@@ -145,7 +155,8 @@ gyroscope@68 {
reg = <0x68>;
interrupt-parent = <&msmgpio>;
interrupts = <23 IRQ_TYPE_EDGE_RISING>;
interrupts = <23 IRQ_TYPE_EDGE_RISING>,
<22 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&gyro_int_default>;
......@@ -196,6 +207,10 @@ &pm8916_resin {
linux,code = <KEY_VOLUMEDOWN>;
};
&pm8916_usbin {
status = "okay";
};
&pm8916_vib {
status = "okay";
};
......@@ -225,11 +240,11 @@ &sdhc_2 {
&usb {
status = "okay";
dr_mode = "peripheral";
extcon = <&usb_vbus>;
extcon = <&pm8916_usbin>;
};
&usb_hs_phy {
extcon = <&usb_vbus>;
extcon = <&pm8916_usbin>;
};
&smd_rpm_regulators {
......@@ -336,6 +351,14 @@ l18 {
};
&msmgpio {
accel_int_default: accel-int-default {
pins = "gpio116";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
camera_flash_default: camera-flash-default {
pins = "gpio31", "gpio32";
function = "gpio";
......@@ -361,25 +384,26 @@ gpio_keys_default: gpio-keys-default {
};
gyro_int_default: gyro-int-default {
pins = "gpio23";
pins = "gpio22", "gpio23";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tp_int_default: tp-int-default {
pins = "gpio13";
magn_int_default: magn-int-default {
pins = "gpio113";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
usb_vbus_default: usb-vbus-default {
pins = "gpio62";
tp_int_default: tp-int-default {
pins = "gpio13";
function = "gpio";
bias-pull-up;
drive-strength = <2>;
bias-disable;
};
};
arch/arm64/boot/dts/qcom/msm8916.dtsi
View file @ c7613530
......@@ -414,7 +414,7 @@ wcnss_smsm: wcnss@6 {
};
};
soc: soc {
soc: soc@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
......@@ -1384,11 +1384,17 @@ sound: sound@7702000 {
lpass: audio-controller@7708000 {
status = "disabled";
compatible = "qcom,lpass-cpu-apq8016";
/*
* Note: Unlike the name would suggest, the SEC_I2S_CLK
* is actually only used by Tertiary MI2S while
* Primary/Secondary MI2S both use the PRI_I2S_CLK.
*/
clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
<&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
<&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
<&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
<&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
<&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
<&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
<&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
......@@ -1420,7 +1426,7 @@ lpass_codec: audio-codec@771c000 {
};
sdhc_1: sdhci@7824000 {
compatible = "qcom,sdhci-msm-v4";
compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
reg = <0x07824900 0x11c>, <0x07824000 0x800>;
reg-names = "hc_mem", "core_mem";
......@@ -1438,7 +1444,7 @@ sdhc_1: sdhci@7824000 {
};
sdhc_2: sdhci@7864000 {
compatible = "qcom,sdhci-msm-v4";
compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
reg = <0x07864900 0x11c>, <0x07864000 0x800>;
reg-names = "hc_mem", "core_mem";
......@@ -1765,7 +1771,7 @@ smd-edge {
label = "pronto";
wcnss {
wcnss_ctrl: wcnss {
compatible = "qcom,wcnss";
qcom,smd-channels = "WCNSS_CTRL";
......
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi 0 → 100644
View file @ c7613530
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Yassine Oudjana <y.oudjana@protonmail.com>
*/
/dts-v1/;
#include "msm8996.dtsi"
#include "pm8994.dtsi"
#include "pmi8994.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
clocks {
compatible = "simple-bus";
divclk1_cdc: divclk1 {
compatible = "gpio-gate-clock";
clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
#clock-cells = <0>;
enable-gpios = <&pm8994_gpios 15 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&divclk1_default>;
};
divclk4: divclk4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "divclk4";
pinctrl-names = "default";
pinctrl-0 = <&divclk4_pin_a>;
};
};
gpio_keys {
compatible = "gpio-keys";
vol_up {
label = "Volume Up";
gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
wakeup-source;
debounce-interval = <15>;
};
dome {
label = "Home";
gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
wakeup-source;
debounce-interval = <15>;
};
};
reserved-memory {
memory@88800000 {
reg = <0x0 0x88800000 0x0 0x1400000>;
no-map;
};
/* This platform has all PIL regions offset by 0x1400000 */
/delete-node/ mpss@88800000;
mpss_region: mpss@89c00000 {
reg = <0x0 0x89c00000 0x0 0x6200000>;
no-map;
};
/delete-node/ adsp@8ea00000;
adsp_region: adsp@8ea00000 {
reg = <0x0 0x8fe00000 0x0 0x1b00000>;
no-map;
};
/delete-node/ slpi@90b00000;
slpi_region: slpi@91900000 {
reg = <0x0 0x91900000 0x0 0xa00000>;
no-map;
};
/delete-node/ gpu@8f200000;
zap_shader_region: gpu@92300000 {
compatible = "shared-dma-pool";
reg = <0x0 0x92300000 0x0 0x2000>;
no-map;
};
/delete-node/ venus@91000000;
venus_region: venus@90400000 {
reg = <0x0 0x92400000 0x0 0x500000>;
no-map;
};
ramoops@92900000 {
compatible = "ramoops";
reg = <0x0 0x92900000 0x0 0x100000>;
no-map;
record-size = <0x8000>;
console-size = <0x80000>;
ftrace-size = <0x20000>;
pmsg-size = <0x40000>;
};
/delete-node/ rmtfs@86700000;
rmtfs@f6c00000 {
compatible = "qcom,rmtfs-mem";
reg = <0 0xf6c00000 0 0x200000>;
no-map;
qcom,client-id = <1>;
qcom,vmid = <15>;
};
/delete-node/ mba@91500000;
mba_region: mba@f6f00000 {
reg = <0x0 0xf6f00000 0x0 0x100000>;
no-map;
};
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3800000>;
regulator-max-microvolt = <3800000>;
regulator-always-on;
regulator-boot-on;
};
vdd_3v2_tp: vdd-3v2-tp {
compatible = "regulator-fixed";
regulator-name = "vdd_3v2_tp";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
startup-delay-us = <4000>;
vin-supply = <&vph_pwr>;
gpio = <&tlmm 73 0>;
enable-active-high;
};
vdd_3v3: rome-vreg {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <4000>;
vin-supply = <&vph_pwr_bbyp>;
gpio = <&pm8994_gpios 9 0>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&rome_enable_default>;
/* Required by QCA6174a - vddpe-3v3 */
regulator-always-on;
};
/* WL_EN pin defined as a fixed regulator */
wlan_en: wlan-en-1-8v {
compatible = "regulator-fixed";
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&pm8994_gpios 8 0>;
/* WLAN card specific delay */
startup-delay-us = <70000>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&wlan_en_default>;
};
};
&adsp_pil {
status = "okay";
};
&blsp2_i2c2 {
status = "okay";
label = "NFC_I2C";
nfc: pn548@28 {
compatible = "nxp,nxp-nci-i2c";
reg = <0x28>;
clock-frequency = <400000>;
interrupt-parent = <&tlmm>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
firmware-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&nfc_default>;
};
};
&blsp2_i2c3 {
status = "okay";
label = "TYPEC_I2C";
typec: tusb320@47 {
compatible = "ti,tusb320";
reg = <0x47>;
interrupt-parent = <&tlmm>;
interrupts = <63 IRQ_TYPE_EDGE_RISING>;
};
};
&blsp2_i2c6 {
status = "okay";
label = "MSM_TS_I2C";
};
&blsp1_uart2 {
status = "okay";
label = "QCA_UART";
bluetooth: qca6174a {
compatible = "qcom,qca6174-bt";
enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
clocks = <&divclk4>;
};
};
&dsi0 {
status = "okay";
vdd-supply = <&vreg_l2a_1p25>;
vddio-supply = <&vreg_l14a_1p8>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mdss_dsi_default &mdss_te_default>;
pinctrl-1 = <&mdss_dsi_sleep &mdss_te_sleep>;
};
&dsi0_out {
status = "okay";
data-lanes = <0 1 2 3>;
};
&dsi0_phy {
status = "okay";
vcca-supply = <&vreg_l28a_0p925>;
};
&gpu {
status = "okay";
};
&mdss {
status = "okay";
};
&mmcc {
vdd-gfx-supply = <&vdd_gfx>;
};
&pcie0 {
status = "okay";
/* Supplied by vdd_3v3, but choose wlan_en to drive enable pin high */
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&vreg_l28a_0p925>;
perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
};
&pcie_phy {
status = "okay";
vdda-phy-supply = <&vreg_l28a_0p925>;
vdda-pll-supply = <&vreg_l12a_1p8>;
};
&pm8994_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
};
&usb3 {
status = "okay";
extcon = <&typec>;
qcom,select-utmi-as-pipe-clk;
dwc3@6a00000 {
extcon = <&typec>;
/* usb3-phy is not used on this device */
phys = <&hsusb_phy1>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
snps,is-utmi-l1-suspend;
snps,usb2-gadget-lpm-disable;
snps,hird-threshold = /bits/ 8 <0>;
};
};
&hsusb_phy1 {
status = "okay";
extcon = <&typec>;
vdda-pll-supply = <&vreg_l12a_1p8>;
vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
};
&ufshc {
status = "okay";
vcc-supply = <&vreg_l20a_2p95>;
vccq-supply = <&vreg_l25a_1p2>;
vccq2-supply = <&vreg_s4a_1p8>;
vcc-max-microamp = <600000>;
vccq-max-microamp = <450000>;
vccq2-max-microamp = <450000>;
};
&ufsphy {
status = "okay";
vdda-phy-supply = <&vreg_l28a_0p925>;
vdda-pll-supply = <&vreg_l12a_1p8>;
vdda-phy-max-microamp = <18380>;
vdda-pll-max-microamp = <9440>;
vddp-ref-clk-supply = <&vreg_l25a_1p2>;
vddp-ref-clk-max-microamp = <100>;
vddp-ref-clk-always-on;
};
&venus {
status = "okay";
};
&wcd9335 {
clock-names = "mclk", "slimbus";
clocks = <&divclk1_cdc>,
<&rpmcc RPM_SMD_BB_CLK1>;
vdd-buck-supply = <&vreg_s4a_1p8>;
vdd-buck-sido-supply = <&vreg_s4a_1p8>;
vdd-rx-supply = <&vreg_s4a_1p8>;
vdd-tx-supply = <&vreg_s4a_1p8>;
vdd-vbat-supply = <&vph_pwr>;
vdd-micbias-supply = <&vph_pwr_bbyp>;
vdd-io-supply = <&vreg_s4a_1p8>;
};
&rpm_requests {
pm8994-regulators {
compatible = "qcom,rpm-pm8994-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_s2-supply = <&vph_pwr>;
vdd_s3-supply = <&vph_pwr>;
vdd_s4-supply = <&vph_pwr>;
vdd_s5-supply = <&vph_pwr>;
vdd_s6-supply = <&vph_pwr>;
vdd_s7-supply = <&vph_pwr>;
vdd_s8-supply = <&vph_pwr>;
vdd_s9-supply = <&vph_pwr>;
vdd_s10-supply = <&vph_pwr>;
vdd_s11-supply = <&vph_pwr>;
vdd_s12-supply = <&vph_pwr>;
vdd_l1-supply = <&vreg_s1b_1p025>;
vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>;
vdd_l3_l11-supply = <&vreg_s3a_1p3>;
vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>;
vdd_l5_l7-supply = <&vreg_s5a_2p15>;
vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>;
vdd_l8_l16_l30-supply = <&vph_pwr>;
vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>;
vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>;
vdd_l14_l15-supply = <&vreg_s5a_2p15>;
vdd_l17_l29-supply = <&vph_pwr_bbyp>;
vdd_l20_l21-supply = <&vph_pwr_bbyp>;
vdd_l25-supply = <&vreg_s3a_1p3>;
vdd_lvs1_2-supply = <&vreg_s4a_1p8>;
vreg_s3a_1p3: s3 {
regulator-name = "vreg_s3a_1p3";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
/* Required by QCA6174a - vdd-core */
regulator-always-on;
};
vreg_s4a_1p8: s4 {
regulator-name = "vreg_s4a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-allow-set-load;
/* Required by QCA6174a - vddio */
regulator-always-on;
};
vreg_s5a_2p15: s5 {
regulator-name = "vreg_s5a_2p15";
regulator-min-microvolt = <2150000>;
regulator-max-microvolt = <2150000>;
};
vreg_s7a_0p8: s7 {
regulator-name = "vreg_s7a_0p8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
};
vreg_l1a_1p0: l1 {
regulator-name = "vreg_l1a_1p0";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
vreg_l2a_1p25: l2 {
regulator-name = "vreg_l2a_1p25";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
};
vreg_l4a_1p225: l4 {
regulator-name = "vreg_l4a_1p225";
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
};
vreg_l6a_1p8: l6 {
regulator-name = "vreg_l6a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l8a_1p8: l8 {
regulator-name = "vreg_l8a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l9a_1p8: l9 {
regulator-name = "vreg_l9a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l10a_1p8: l10 {
regulator-name = "vreg_l10a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l12a_1p8: l12 {
regulator-name = "vreg_l12a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-allow-set-load;
};
vreg_l13a_2p95: l13 {
regulator-name = "vreg_l13a_2p95";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
vreg_l14a_1p8: l14 {
regulator-name = "vreg_l14a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l15a_1p8: l15 {
regulator-name = "vreg_l15a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l16a_2p7: l16 {
regulator-name = "vreg_l16a_2p7";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
};
vreg_l19a_3p3: l19 {
regulator-name = "vreg_l19a_3p3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
vreg_l20a_2p95: l20 {
regulator-name = "vreg_l20a_2p95";
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
};
vreg_l21a_2p95: l21 {
regulator-name = "vreg_l21a_2p95";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vreg_l23a_2p8: l23 {
regulator-name = "vreg_l23a_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
vreg_l24a_3p075: l24 {
regulator-name = "vreg_l24a_3p075";
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
};
vreg_l25a_1p2: l25 {
regulator-name = "vreg_l25a_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-allow-set-load;
};
vreg_l27a_1p2: l27 {
regulator-name = "vreg_l27a_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
vreg_l28a_0p925: l28 {
regulator-name = "vreg_l28a_0p925";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <925000>;
regulator-allow-set-load;
};
vreg_l30a_1p8: l30 {
regulator-name = "vreg_l30a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
/* Required by QCA6174a - vddio-xtal */
regulator-always-on;
};
vreg_l32a_1p8: l32 {
regulator-name = "vreg_l32a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_lvs1a_1p8: lvs1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_lvs2a_1p8: lvs2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
pmi8994-regulators {
compatible = "qcom,rpm-pmi8994-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_s2-supply = <&vph_pwr>;
vdd_s3-supply = <&vph_pwr>;
vdd_bst_byp-supply = <&vph_pwr>;
vreg_s1b_1p025: s1 {
regulator-name = "vreg_s1b_1p025";
regulator-min-microvolt = <1025000>;
regulator-max-microvolt = <1025000>;
};
vph_pwr_bbyp: boost-bypass {
regulator-name = "vph_pwr_bbyp";
regulator-min-microvolt = <3150000>;
regulator-max-microvolt = <3600000>;
};
};
};
&pm8994_spmi_regulators {
qcom,saw-reg = <&saw3>;
s8 {
qcom,saw-slave;
};
s9 {
qcom,saw-slave;
};
s10 {
qcom,saw-slave;
};
vreg_apc_0p8: s11 {
qcom,saw-leader;
regulator-name = "vreg_apc_0p8";
regulator-min-microvolt = <470000>;
regulator-max-microvolt = <1140000>;
regulator-max-step-microvolt = <150000>;
regulator-always-on;
};
};
&pmi8994_spmi_regulators {
vdd_gfx: s2 {
regulator-name = "vdd_gfx";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1015000>;
regulator-enable-ramp-delay = <500>;
};
};
&pm8994_gpios {
wlan_en_default: wlan-en-default {
pins = "gpio8";
function = PMIC_GPIO_FUNC_NORMAL;
output-low;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
power-source = <PM8994_GPIO_S4>;
bias-disable;
};
rome_enable_default: rome-enable-default {
pins = "gpio9";
function = PMIC_GPIO_FUNC_NORMAL;
output-high;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
power-source = <PM8994_GPIO_VPH>;
};
divclk1_default: divclk1_default {
pins = "gpio15";
function = PMIC_GPIO_FUNC_FUNC1;
bias-disable;
power-source = <PM8994_GPIO_S4>;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
};
divclk4_pin_a: divclk4 {
pins = "gpio18";
function = PMIC_GPIO_FUNC_FUNC2;
bias-disable;
power-source = <PM8994_GPIO_S4>;
};
};
&tlmm {
mdss_dsi_default: mdss_dsi_default {
pins = "gpio8";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
mdss_dsi_sleep: mdss_dsi_sleep {
pins = "gpio8";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
mdss_te_default: mdss_te_default {
pins = "gpio10";
function = "mdp_vsync";
drive-strength = <2>;
bias-pull-down;
};
mdss_te_sleep: mdss_te_sleep {
pins = "gpio10";
function = "mdp_vsync";
drive-strength = <2>;
bias-pull-down;
};
nfc_default: nfc_default {
pins = "gpio12", "gpio21";
function = "gpio";
drive-strength = <16>;
bias-pull-up;
};
};
arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts 0 → 100644
View file @ c7613530
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2021, Raffaele Tranquillini <raffaele.tranquillini@gmail.com>
*/
/dts-v1/;
#include "msm8996-xiaomi-common.dtsi"
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
#include <dt-bindings/input/ti-drv260x.h>
/ {
model = "Xiaomi Mi 5";
compatible = "xiaomi,gemini", "qcom,msm8996";
qcom,msm-id = <246 0x30001>;
qcom,pmic-id = <0x20009 0x2000a 0x00 0x00>;
qcom,board-id = <31 0>;
clocks {
divclk2_haptics: divclk2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "divclk2";
pinctrl-names = "default";
pinctrl-0 = <&divclk2_pin_a>;
};
};
};
&adsp_pil {
firmware-name = "qcom/msm8996/gemini/adsp.mbn";
};
&blsp2_i2c3 {
haptics: drv2604@5a {
compatible = "ti,drv2604";
reg = <0x5a>;
enable-gpio = <&tlmm 93 0x00>;
mode = <DRV260X_LRA_MODE>;
library-sel = <DRV260X_LIB_LRA>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&vibrator_default>;
pinctrl-1 = <&vibrator_sleep>;
};
lp5562@30 {
compatible = "ti,lp5562";
reg = <0x30>;
#address-cells = <1>;
#size-cells = <0>;
enable-gpio = <&pm8994_gpios 7 1>;
clock-mode = /bits/8 <2>;
label = "button-backlight";
led@0 {
reg = <0>;
chan-name = "button-backlight";
led-cur = /bits/ 8 <0x32>;
max-cur = /bits/ 8 <0xC8>;
};
led@1 {
reg = <0>;
chan-name = "button-backlight1";
led-cur = /bits/ 8 <0x32>;
max-cur = /bits/ 8 <0xC8>;
};
};
};
&blsp2_i2c6 {
synaptics@20 {
compatible = "syna,rmi4-i2c";
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&tlmm>;
interrupts = <125 IRQ_TYPE_LEVEL_LOW>;
vdda-supply = <&vreg_l6a_1p8>;
vdd-supply = <&vdd_3v2_tp>;
reset-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&touchscreen_default>;
pinctrl-1 = <&touchscreen_sleep>;
};
};
&gpu {
zap-shader {
firmware-name = "qcom/msm8996/gemini/a530_zap.mbn";
};
};
&q6asmdai {
dai@0 {
reg = <0>;
};
dai@1 {
reg = <1>;
};
dai@2 {
reg = <2>;
};
};
&sound {
compatible = "qcom,apq8096-sndcard";
model = "gemini";
audio-routing = "RX_BIAS", "MCLK",
"MM_DL1", "MultiMedia1 Playback",
"MM_DL2", "MultiMedia2 Playback",
"MultiMedia3 Capture", "MM_UL3";
mm1-dai-link {
link-name = "MultiMedia1";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
};
};
mm2-dai-link {
link-name = "MultiMedia2";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
};
};
mm3-dai-link {
link-name = "MultiMedia3";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
};
};
slim-dai-link {
link-name = "SLIM Playback";
cpu {
sound-dai = <&q6afedai SLIMBUS_6_RX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&wcd9335 6>;
};
};
slimcap-dai-link {
link-name = "SLIM Capture";
cpu {
sound-dai = <&q6afedai SLIMBUS_0_TX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&wcd9335 1>;
};
};
};
&venus {
firmware-name = "qcom/msm8996/gemini/venus.mbn";
};
&rpm_requests {
pm8994-regulators {
vreg_l17a_2p8: l17 {
regulator-name = "vreg_l17a_2p8";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
vreg_l29a_2p7: l29 {
regulator-name = "vreg_l29a_2p7";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
};
};
&pm8994_gpios {
gpio-line-names =
"NC", /* GPIO_1 */
"VOL_UP_N", /* GPIO_2 */
"SPKR_ID", /* GPIO_3 */
"PWM_HAPTICS", /* GPIO_4 */
"INFARED_DRV", /* GPIO_5 */
"NC", /* GPIO_6 */
"KEYPAD_LED_EN", /* GPIO_7 */
"WL_EN", /* GPIO_8 */
"3P3_ENABLE", /* GPIO_9 */
"FP_ID", /* GPIO_10 */
"NC", /* GPIO_11 */
"NC", /* GPIO_12 */
"NC", /* GPIO_13 */
"NC", /* GPIO_14 */
"DIVCLK1_CDC", /* GPIO_15 */
"DIVCLK2_HAPTICS", /* GPIO_16 */
"NC", /* GPIO_17 */
"32KHz_CLK_IN", /* GPIO_18 */
"BT_EN", /* GPIO_19 */
"PMIC_SLB", /* GPIO_20 */
"UIM_BATT_ALARM", /* GPIO_21 */
"NC"; /* GPIO_22 */
divclk2_pin_a: divclk2 {
pins = "gpio16";
function = PMIC_GPIO_FUNC_FUNC2;
bias-disable;
power-source = <PM8994_GPIO_S4>;
};
};
&pm8994_mpps {
gpio-line-names =
"NC", /* MPP_1 */
"CCI_TIMER1", /* MPP_2 */
"PMIC_SLB", /* MPP_3 */
"EXT_FET_WLED_PWR_EN_N",/* MPP_4 */
"NC", /* MPP_5 */
"NC", /* MPP_6 */
"NC", /* MPP_7 */
"NC"; /* MPP_8 */
};
&pmi8994_gpios {
gpio-line-names =
"NC", /* GPIO_1 */
"SPKR_PA_RST", /* GPIO_2 */
"NC", /* GPIO_3 */
"NC", /* GPIO_4 */
"NC", /* GPIO_5 */
"NC", /* GPIO_6 */
"NC", /* GPIO_7 */
"NC", /* GPIO_8 */
"NC", /* GPIO_9 */
"NC"; /* GPIO_10 */
};
&tlmm {
gpio-line-names =
"ESE_SPI_MOSI", /* GPIO_0 */
"ESE_SPI_MISO", /* GPIO_1 */
"ERR_INT_N", /* GPIO_2 */
"ESE_SPI_CLK", /* GPIO_3 */
"MSM_UART_TX", /* GPIO_4 */
"MSM_UART_RX", /* GPIO_5 */
"NFC_I2C_SDA", /* GPIO_6 */
"NFC_I2C_SCL", /* GPIO_7 */
"LCD0_RESET_N", /* GPIO_8 */
"NFC_IRQ", /* GPIO_9 */
"LCD_TE", /* GPIO_10 */
"LCD_ID_DET1", /* GPIO_11 */
"NFC_DISABLE", /* GPIO_12 */
"CAM_MCLK0", /* GPIO_13 */
"NC", /* GPIO_14 */
"CAM_MCLK2", /* GPIO_15 */
"ESE_PWR_REQ", /* GPIO_16 */
"CCI_I2C_SDA0", /* GPIO_17 */
"CCI_I2C_SCL0", /* GPIO_18 */
"CCI_I2C_SDA1", /* GPIO_19 */
"CCI_I2C_SCL1", /* GPIO_20 */
"NFC_DWL_REQ", /* GPIO_21 */
"CCI_TIMER1", /* GPIO_22 */
"WEBCAM1_RESET_N", /* GPIO_23 */
"ESE_IRQ", /* GPIO_24 */
"NC", /* GPIO_25 */
"WEBCAM1_STANDBY", /* GPIO_26 */
"NC", /* GPIO_27 */
"NC", /* GPIO_28 */
"NC", /* GPIO_29 */
"CAM1_RST_N", /* GPIO_30 */
"NC", /* GPIO_31 */
"NC", /* GPIO_32 */
"NC", /* GPIO_33 */
"FP_DOME_SW", /* GPIO_34 */
"PCI_E0_RST_N", /* GPIO_35 */
"PCI_E0_CLKREQ_N", /* GPIO_36 */
"PCI_E0_WAKE", /* GPIO_37 */
"FM_INT_N", /* GPIO_38 */
"FM_RESET_N", /* GPIO_39 */
"NC", /* GPIO_40 */
"QCA_UART_TXD", /* GPIO_41 */
"QCA_UART_RXD", /* GPIO_42 */
"QCA_UART_CTS", /* GPIO_43 */
"QCA_UART_RTS", /* GPIO_44 */
"MAWC_UART_TX", /* GPIO_45 */
"MAWC_UART_RX", /* GPIO_46 */
"NC", /* GPIO_47 */
"NC", /* GPIO_48 */
"AUDIO_SWITCH_EN", /* GPIO_49 */
"FP_SPI_RST", /* GPIO_50 */
"TYPEC_I2C_SDA", /* GPIO_51 */
"TYPEC_I2C_SCL", /* GPIO_52 */
"CODEC_INT2_N", /* GPIO_53 */
"CODEC_INT1_N", /* GPIO_54 */
"APPS_I2C7_SDA", /* GPIO_55 */
"APPS_I2C7_SCL", /* GPIO_56 */
"FORCE_USB_BOOT", /* GPIO_57 */
"SPKR_I2S_BCK", /* GPIO_58 */
"SPKR_I2S_WS", /* GPIO_59 */
"SPKR_I2S_DOUT", /* GPIO_60 */
"SPKR_I2S_DIN", /* GPIO_61 */
"ESE_RSTN", /* GPIO_62 */
"TYPEC_INT", /* GPIO_63 */
"CODEC_RESET_N", /* GPIO_64 */
"PCM_CLK", /* GPIO_65 */
"PCM_SYNC", /* GPIO_66 */
"PCM_DIN", /* GPIO_67 */
"PCM_DOUT", /* GPIO_68 */
"HIFI_CLK", /* GPIO_69 */
"SLIMBUS_CLK", /* GPIO_70 */
"SLIMBUS_DATA0", /* GPIO_71 */
"SLIMBUS_DATA1", /* GPIO_72 */
"LDO_5V_IN_EN", /* GPIO_73 */
"NC", /* GPIO_74 */
"FM_I2S_CLK", /* GPIO_75 */
"FM_I2S_SYNC", /* GPIO_76 */
"FM_I2S_DATA", /* GPIO_77 */
"FM_STATUS", /* GPIO_78 */
"NC", /* GPIO_79 */
"SENSOR_RESET_N", /* GPIO_80 */
"FP_SPI_MOSI", /* GPIO_81 */
"FP_SPI_MISO", /* GPIO_82 */
"FP_SPI_CS_N", /* GPIO_83 */
"FP_SPI_CLK", /* GPIO_84 */
"NC", /* GPIO_85 */
"CAM_VDD_1P05_EN", /* GPIO_86 */
"MSM_TS_I2C_SDA", /* GPIO_87 */
"MSM_TS_I2C_SCL", /* GPIO_88 */
"TS_RESOUT_N", /* GPIO_89 */
"ESE_SPI_CS_N", /* GPIO_90 */
"NC", /* GPIO_91 */
"NC", /* GPIO_92 */
"HAPTICS_EN", /* GPIO_93 */
"NC", /* GPIO_94 */
"NC", /* GPIO_95 */
"NC", /* GPIO_96 */
"NC", /* GPIO_97 */
"GRFC_1", /* GPIO_98 */
"NC", /* GPIO_99 */
"GRFC_3", /* GPIO_100 */
"GRFC_4", /* GPIO_101 */
"NC", /* GPIO_102 */
"NC", /* GPIO_103 */
"GRFC_7", /* GPIO_104 */
"UIM2_DATA", /* GPIO_105 */
"UIM2_CLK", /* GPIO_106 */
"UIM2_RESET", /* GPIO_107 */
"UIM2_PRESENT", /* GPIO_108 */
"UIM1_DATA", /* GPIO_109 */
"UIM1_CLK", /* GPIO_110 */
"UIM1_RESET", /* GPIO_111 */
"UIM1_PRESENT", /* GPIO_112 */
"UIM_BATT_ALARM", /* GPIO_113 */
"GRFC_8", /* GPIO_114 */
"GRFC_9", /* GPIO_115 */
"TX_GTR_THRES", /* GPIO_116 */
"ACCEL_INT", /* GPIO_117 */
"GYRO_INT", /* GPIO_118 */
"COMPASS_INT", /* GPIO_119 */
"PROXIMITY_INT_N", /* GPIO_120 */
"FP_IRQ", /* GPIO_121 */
"NC", /* GPIO_122 */
"HALL_INTR2", /* GPIO_123 */
"HALL_INTR1", /* GPIO_124 */
"TS_INT_N", /* GPIO_125 */
"NC", /* GPIO_126 */
"GRFC_11", /* GPIO_127 */
"NC", /* GPIO_128 */
"EXT_GPS_LNA_EN", /* GPIO_129 */
"NC", /* GPIO_130 */
"NC", /* GPIO_131 */
"NC", /* GPIO_132 */
"GRFC_14", /* GPIO_133 */
"GSM_TX2_PHASE_D", /* GPIO_134 */
"NC", /* GPIO_135 */
"NC", /* GPIO_136 */
"RFFE3_DATA", /* GPIO_137 */
"RFFE3_CLK", /* GPIO_138 */
"NC", /* GPIO_139 */
"NC", /* GPIO_140 */
"RFFE5_DATA", /* GPIO_141 */
"RFFE5_CLK", /* GPIO_142 */
"NC", /* GPIO_143 */
"COEX_UART_TX", /* GPIO_144 */
"COEX_UART_RX", /* GPIO_145 */
"RFFE2_DATA", /* GPIO_146 */
"RFFE2_CLK", /* GPIO_147 */
"RFFE1_DATA", /* GPIO_148 */
"RFFE1_CLK"; /* GPIO_149 */
touchscreen_default: touchscreen_default {
pins = "gpio89", "gpio125";
function = "gpio";
drive-strength = <10>;
bias-pull-up;
};
touchscreen_sleep: touchscreen_sleep {
pins = "gpio89", "gpio125";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
vibrator_default: vibrator_default {
pins = "gpio93";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
vibrator_sleep: vibrator_sleep {
pins = "gpio93";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts 0 → 100644
View file @ c7613530
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Yassine Oudjana <y.oudjana@protonmail.com>
*/
/dts-v1/;
#include "msm8996-xiaomi-common.dtsi"
#include "pmi8996.dtsi"
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
/ {
model = "Xiaomi Mi Note 2";
compatible = "xiaomi,scorpio", "qcom,msm8996";
qcom,msm-id = <305 0x10000>;
qcom,board-id = <34 0>;
chosen {
#address-cells = <2>;
#size-cells = <2>;
ranges;
framebuffer0: framebuffer@83401000 {
compatible = "simple-framebuffer";
reg = <0x00 0x83401000 0x00 (1080 * 1920 * 3)>;
width = <1080>;
height = <1920>;
stride = <(1080 * 3)>;
format = "r8g8b8";
/* DSI0 and MDP SMMU clocks */
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MMSS_MMAGIC_AHB_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
<&mmcc MMSS_MISC_AHB_CLK>,
<&mmcc MDSS_BYTE0_CLK>,
<&mmcc MDSS_PCLK0_CLK>,
<&mmcc MDSS_ESC0_CLK>,
<&mmcc SMMU_MDP_AHB_CLK>,
<&mmcc SMMU_MDP_AXI_CLK>;
/* MDSS power domain */
power-domains = <&mmcc MDSS_GDSC>;
};
};
reserved-memory {
cont_splash_mem: memory@83401000 {
reg = <0x0 0x83401000 0x0 (1080 * 1920 * 3)>;
no-map;
};
};
};
&adsp_pil {
firmware-name = "qcom/msm8996/scorpio/adsp.mbn";
};
&blsp2_i2c6 {
touchscreen: atmel-mxt-ts@4a {
compatible = "atmel,maxtouch";
reg = <0x4a>;
interrupt-parent = <&tlmm>;
interrupts = <125 IRQ_TYPE_LEVEL_LOW>;
vdda-supply = <&vreg_l6a_1p8>;
vdd-supply = <&vdd_3v2_tp>;
reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&touchscreen_default>;
pinctrl-1 = <&touchscreen_sleep>;
};
};
&gpu {
zap-shader {
firmware-name = "qcom/msm8996/scorpio/a530_zap.mbn";
};
};
&mdp_smmu {
/*
* Probing this SMMU causes a crash due to writing to some secure
* registers. Disable it for now.
*/
status = "disabled";
};
&mdss {
/*
* MDSS depends on the MDP SMMU, and probing it alters the bootloader
* configured framebuffer used by simplefb. Disable it for now.
*/
status = "disabled";
};
&q6asmdai {
dai@0 {
reg = <0>;
};
dai@1 {
reg = <1>;
};
dai@2 {
reg = <2>;
};
};
&sound {
compatible = "qcom,apq8096-sndcard";
model = "scorpio";
audio-routing = "RX_BIAS", "MCLK";
mm1-dai-link {
link-name = "MultiMedia1";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
};
};
mm2-dai-link {
link-name = "MultiMedia2";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
};
};
mm3-dai-link {
link-name = "MultiMedia3";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
};
};
slim-dai-link {
link-name = "SLIM Playback";
cpu {
sound-dai = <&q6afedai SLIMBUS_6_RX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&wcd9335 6>;
};
};
slimcap-dai-link {
link-name = "SLIM Capture";
cpu {
sound-dai = <&q6afedai SLIMBUS_0_TX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&wcd9335 1>;
};
};
};
&venus {
firmware-name = "qcom/msm8996/scorpio/venus.mbn";
};
&rpm_requests {
pm8994-regulators {
vreg_l3a_0p875: l3 {
regulator-name = "vreg_l3a_0p875";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1300000>;
};
vreg_l11a_1p1: l11 {
regulator-name = "vreg_l11a_1p1";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
vreg_l17a_2p8: l17 {
regulator-name = "vreg_l17a_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
vreg_l18a_2p8: l18 {
regulator-name = "vreg_l18a_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
vreg_l22a_3p0: l22 {
regulator-name = "vreg_l22a_3p0";
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <3500000>;
};
vreg_l29a_2p7: l29 {
regulator-name = "vreg_l29a_2p7";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
};
};
};
&vdd_gfx {
regulator-max-microvolt = <1065000>;
};
&pm8994_gpios {
gpio-line-names =
"NC", /* GPIO_1 */
"VOL_UP_N", /* GPIO_2 */
"SPKR_ID", /* GPIO_3 */
"PWM_HAPTICS", /* GPIO_4 */
"INFARED_DRV", /* GPIO_5 */
"NC", /* GPIO_6 */
"KEYPAD_LED_EN_A", /* GPIO_7 */
"WL_EN", /* GPIO_8 */
"3P3_ENABLE", /* GPIO_9 */
"KEYPAD_LED_EN_B", /* GPIO_10 */
"FP_ID", /* GPIO_11 */
"NC", /* GPIO_12 */
"NC", /* GPIO_13 */
"NC", /* GPIO_14 */
"DIVCLK1_CDC", /* GPIO_15 */
"DIVCLK2_HAPTICS", /* GPIO_16 */
"NC", /* GPIO_17 */
"32KHz_CLK_IN", /* GPIO_18 */
"BT_EN", /* GPIO_19 */
"PMIC_SLB", /* GPIO_20 */
"UIM_BATT_ALARM", /* GPIO_21 */
"NC"; /* GPIO_22 */
};
&pm8994_mpps {
gpio-line-names =
"VREF_SDC_UIM_APC", /* MPP_1 */
"NC", /* MPP_2 */
"VREF_DACX", /* MPP_3 */
"NC", /* MPP_4 */
"NC", /* MPP_5 */
"STAT_SMB1351", /* MPP_6 */
"NC", /* MPP_7 */
"NC"; /* MPP_8 */
};
&pmi8994_gpios {
gpio-line-names =
"NC", /* GPIO_1 */
"SPKR_PA_RST", /* GPIO_2 */
"NC", /* GPIO_3 */
"NC", /* GPIO_4 */
"NC", /* GPIO_5 */
"NC", /* GPIO_6 */
"NC", /* GPIO_7 */
"NC", /* GPIO_8 */
"NC", /* GPIO_9 */
"NC"; /* GPIO_10 */
};
&tlmm {
gpio-line-names =
"ESE_SPI_MOSI", /* GPIO_0 */
"ESE_SPI_MISO", /* GPIO_1 */
"NC", /* GPIO_2 */
"ESE_SPI_CLK", /* GPIO_3 */
"MSM_UART_TX", /* GPIO_4 */
"MSM_UART_RX", /* GPIO_5 */
"NFC_I2C_SDA", /* GPIO_6 */
"NFC_I2C_SCL", /* GPIO_7 */
"OLED_RESET_N", /* GPIO_8 */
"NFC_IRQ", /* GPIO_9 */
"OLED_TE", /* GPIO_10 */
"OLED_ID_DET1", /* GPIO_11 */
"NFC_DISABLE", /* GPIO_12 */
"CAM_MCLK0", /* GPIO_13 */
"OLED_ID_DET2", /* GPIO_14 */
"CAM_MCLK2", /* GPIO_15 */
"ESE_PWR_REQ", /* GPIO_16 */
"CCI_I2C_SDA0", /* GPIO_17 */
"CCI_I2C_SCL0", /* GPIO_18 */
"CCI_I2C_SDA1", /* GPIO_19 */
"CCI_I2C_SCL1", /* GPIO_20 */
"NFC_DWL_REQ", /* GPIO_21 */
"CCI_TIMER1", /* GPIO_22 */
"WEBCAM1_RESET_N", /* GPIO_23 */
"ESE_IRQ", /* GPIO_24 */
"NC", /* GPIO_25 */
"WEBCAM1_STANDBY", /* GPIO_26 */
"NC", /* GPIO_27 */
"NC", /* GPIO_28 */
"OLED_ERR_FG", /* GPIO_29 */
"CAM1_RST_N", /* GPIO_30 */
"HIFI_SW_MUTE", /* GPIO_31 */
"NC", /* GPIO_32 */
"NC", /* GPIO_33 */
"FP_DOME_SW", /* GPIO_34 */
"PCI_E0_RST_N", /* GPIO_35 */
"PCI_E0_CLKREQ_N", /* GPIO_36 */
"PCI_E0_WAKE", /* GPIO_37 */
"OV_PWDN", /* GPIO_38 */
"NC", /* GPIO_39 */
"VDDR_1P6_EN", /* GPIO_40 */
"QCA_UART_TXD", /* GPIO_41 */
"QCA_UART_RXD", /* GPIO_42 */
"QCA_UART_CTS", /* GPIO_43 */
"QCA_UART_RTS", /* GPIO_44 */
"MAWC_UART_TX", /* GPIO_45 */
"MAWC_UART_RX", /* GPIO_46 */
"NC", /* GPIO_47 */
"NC", /* GPIO_48 */
"AUDIO_SWITCH_EN", /* GPIO_49 */
"FP_SPI_RST", /* GPIO_50 */
"TYPEC_I2C_SDA", /* GPIO_51 */
"TYPEC_I2C_SCL", /* GPIO_52 */
"CODEC_INT2_N", /* GPIO_53 */
"CODEC_INT1_N", /* GPIO_54 */
"APPS_I2C7_SDA", /* GPIO_55 */
"APPS_I2C7_SCL", /* GPIO_56 */
"FORCE_USB_BOOT", /* GPIO_57 */
"SPKR_I2S_BCK", /* GPIO_58 */
"SPKR_I2S_WS", /* GPIO_59 */
"SPKR_I2S_DOUT", /* GPIO_60 */
"SPKR_I2S_DIN", /* GPIO_61 */
"ESE_RSTN", /* GPIO_62 */
"TYPEC_INT", /* GPIO_63 */
"CODEC_RESET_N", /* GPIO_64 */
"PCM_CLK", /* GPIO_65 */
"PCM_SYNC", /* GPIO_66 */
"PCM_DIN", /* GPIO_67 */
"PCM_DOUT", /* GPIO_68 */
"CDC_44K1_CLK", /* GPIO_69 */
"SLIMBUS_CLK", /* GPIO_70 */
"SLIMBUS_DATA0", /* GPIO_71 */
"SLIMBUS_DATA1", /* GPIO_72 */
"LDO_5V_IN_EN", /* GPIO_73 */
"NC", /* GPIO_74 */
"TSP_RST_N", /* GPIO_75 */
"NC", /* GPIO_76 */
"TOUCHKEY_INT", /* GPIO_77 */
"SPKR_I2S_MCLK", /* GPIO_78 */
"SPKR_PA_INT", /* GPIO_79 */
"SENSOR_RESET_N", /* GPIO_80 */
"FP_SPI_MOSI", /* GPIO_81 */
"FP_SPI_MISO", /* GPIO_82 */
"FP_SPI_CS_N", /* GPIO_83 */
"FP_SPI_CLK", /* GPIO_84 */
"HIFI_SD", /* GPIO_85 */
"CAM_VDD_1P05_EN", /* GPIO_86 */
"MSM_TS_I2C_SDA", /* GPIO_87 */
"MSM_TS_I2C_SCL", /* GPIO_88 */
"NC", /* GPIO_89 */
"ESE_SPI_CS_N", /* GPIO_90 */
"NC", /* GPIO_91 */
"NC", /* GPIO_92 */
"NC", /* GPIO_93 */
"NC", /* GPIO_94 */
"NC", /* GPIO_95 */
"NC", /* GPIO_96 */
"GRFC_0", /* GPIO_97 */
"GRFC_1", /* GPIO_98 */
"NC", /* GPIO_99 */
"GRFC_3", /* GPIO_100 */
"GRFC_4", /* GPIO_101 */
"NC", /* GPIO_102 */
"NC", /* GPIO_103 */
"GRFC_7", /* GPIO_104 */
"UIM2_DATA", /* GPIO_105 */
"UIM2_CLK", /* GPIO_106 */
"UIM2_RESET", /* GPIO_107 */
"UIM2_PRESENT", /* GPIO_108 */
"UIM1_DATA", /* GPIO_109 */
"UIM1_CLK", /* GPIO_110 */
"UIM1_RESET", /* GPIO_111 */
"UIM1_PRESENT", /* GPIO_112 */
"UIM_BATT_ALARM", /* GPIO_113 */
"GRFC_8", /* GPIO_114 */
"GRFC_9", /* GPIO_115 */
"TX_GTR_THRES", /* GPIO_116 */
"ACC_INT", /* GPIO_117 */
"GYRO_INT", /* GPIO_118 */
"COMPASS_INT", /* GPIO_119 */
"PROXIMITY_INT_N", /* GPIO_120 */
"FP_IRQ", /* GPIO_121 */
"TSP_TA", /* GPIO_122 */
"HALL_INTR2", /* GPIO_123 */
"HALL_INTR1", /* GPIO_124 */
"TS_INT_N", /* GPIO_125 */
"NC", /* GPIO_126 */
"GRFC_11", /* GPIO_127 */
"HIFI_PWR_EN", /* GPIO_128 */
"EXT_GPS_LNA_EN", /* GPIO_129 */
"NC", /* GPIO_130 */
"NC", /* GPIO_131 */
"NC", /* GPIO_132 */
"GRFC_14", /* GPIO_133 */
"GSM_TX2_PHASE_D", /* GPIO_134 */
"HIFI_SW_SEL", /* GPIO_135 */
"GRFC_15", /* GPIO_136 */
"RFFE3_DATA", /* GPIO_137 */
"RFFE3_CLK", /* GPIO_138 */
"NC", /* GPIO_139 */
"NC", /* GPIO_140 */
"RFFE5_DATA", /* GPIO_141 */
"RFFE5_CLK", /* GPIO_142 */
"NC", /* GPIO_143 */
"COEX_UART_TX", /* GPIO_144 */
"COEX_UART_RX", /* GPIO_145 */
"RFFE2_DATA", /* GPIO_146 */
"RFFE2_CLK", /* GPIO_147 */
"RFFE1_DATA", /* GPIO_148 */
"RFFE1_CLK"; /* GPIO_149 */
touchscreen_default: touchscreen_default {
pins = "gpio75", "gpio125";
function = "gpio";
drive-strength = <10>;
bias-pull-up;
};
touchscreen_sleep: touchscreen_sleep {
pins = "gpio75", "gpio125";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
arch/arm64/boot/dts/qcom/msm8996.dtsi
View file @ c7613530
......@@ -1211,6 +1211,20 @@ wake {
};
};
blsp1_uart2_default: blsp1-uart2-default {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "blsp_uart2";
drive-strength = <16>;
bias-disable;
};
blsp1_uart2_sleep: blsp1-uart2-sleep {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
blsp1_i2c3_default: blsp1-i2c2-default {
pins = "gpio47", "gpio48";
function = "blsp_i2c3";
......@@ -1239,6 +1253,20 @@ blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
bias-disable;
};
blsp2_i2c3_default: blsp2-i2c3 {
pins = "gpio51", "gpio52";
function = "blsp_i2c9";
drive-strength = <16>;
bias-disable;
};
blsp2_i2c3_sleep: blsp2-i2c3-sleep {
pins = "gpio51", "gpio52";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wcd_intr_default: wcd-intr-default{
pins = "gpio54";
function = "gpio";
......@@ -2686,7 +2714,7 @@ sdhc2: sdhci@74a4900 {
status = "disabled";
};
blsp1_dma: dma@7544000 {
blsp1_dma: dma-controller@7544000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07544000 0x2b000>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
......@@ -2704,6 +2732,9 @@ blsp1_uart2: serial@7570000 {
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart2_default>;
pinctrl-1 = <&blsp1_uart2_sleep>;
dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
dma-names = "tx", "rx";
status = "disabled";
......@@ -2743,7 +2774,7 @@ blsp1_i2c3: i2c@7577000 {
status = "disabled";
};
blsp2_dma: dma@7584000 {
blsp2_dma: dma-controller@7584000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07584000 0x2b000>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
......@@ -2808,6 +2839,24 @@ blsp2_i2c2: i2c@75b6000 {
status = "disabled";
};
blsp2_i2c3: i2c@75b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b7000 0x1000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c3_default>;
pinctrl-1 = <&blsp2_i2c3_sleep>;
dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_i2c5: i2c@75b9000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x75b9000 0x1000>;
......
arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts 0 → 100644
View file @ c7613530
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2021, AngeloGioacchino Del Regno
* <angelogioacchino.delregno@somainline.org>
*/
/dts-v1/;
#include "msm8998-mtp.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
model = "F(x)tec Pro1 (QX1000)";
compatible = "fxtec,pro1", "qcom,msm8998";
qcom,board-id = <0x02000b 0x10>;
/*
* Until we hook up type-c detection, we
* have to stick with this. But it works.
*/
extcon_usb: extcon-usb {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&tlmm 38 GPIO_ACTIVE_HIGH>;
};
gpio-hall-sensors {
compatible = "gpio-keys";
input-name = "hall-sensors";
label = "Hall sensors";
pinctrl-names = "default";
pinctrl-0 = <&hall_sensor1_default>;
hall-sensor1 {
label = "Keyboard Hall Sensor";
gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>;
debounce-interval = <15>;
gpio-key,wakeup;
linux,input-type = <EV_SW>;
linux,code = <SW_KEYPAD_SLIDE>;
};
};
gpio-kb-extra-keys {
compatible = "gpio-keys";
input-name = "extra-kb-keys";
label = "Keyboard extra keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_kb_pins_extra>;
home {
label = "Home";
gpios = <&tlmm 21 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOMEPAGE>;
debounce-interval = <15>;
linux,can-disable;
};
super-l {
label = "Super Left";
gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
linux,code = <KEY_FN>;
debounce-interval = <15>;
linux,can-disable;
};
super-r {
label = "Super Right";
gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
linux,code = <KEY_FN>;
debounce-interval = <15>;
linux,can-disable;
};
shift {
label = "Shift";
gpios = <&tlmm 114 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RIGHTSHIFT>;
debounce-interval = <15>;
linux,can-disable;
};
ctrl {
label = "Ctrl";
gpios = <&tlmm 128 GPIO_ACTIVE_LOW>;
linux,code = <KEY_LEFTCTRL>;
debounce-interval = <15>;
linux,can-disable;
};
alt {
label = "Alt";
gpios = <&tlmm 129 GPIO_ACTIVE_LOW>;
linux,code = <KEY_LEFTALT>;
debounce-interval = <15>;
linux,can-disable;
};
};
gpio-keys {
compatible = "gpio-keys";
input-name = "side-buttons";
label = "Side buttons";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&vol_up_pin_a>, <&cam_focus_pin_a>,
<&cam_snapshot_pin_a>;
vol-up {
label = "Volume Up";
gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_VOLUMEUP>;
gpio-key,wakeup;
debounce-interval = <15>;
};
camera-snapshot {
label = "Camera Snapshot";
gpios = <&pm8998_gpio 7 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_CAMERA>;
debounce-interval = <15>;
};
camera-focus {
label = "Camera Focus";
gpios = <&pm8998_gpio 8 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_CAMERA_FOCUS>;
debounce-interval = <15>;
};
};
keyboard-leds {
compatible = "gpio-leds";
backlight {
color = <LED_COLOR_ID_WHITE>;
default-state = "off";
function = LED_FUNCTION_KBD_BACKLIGHT;
gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
label = "white:kbd_backlight";
retain-state-suspended;
};
caps-lock {
color = <LED_COLOR_ID_YELLOW>;
default-state = "off";
function = LED_FUNCTION_CAPSLOCK;
gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
label = "yellow:capslock";
linux,default-trigger = "kbd-capslock";
};
};
reserved-memory {
cont_splash_mem: memory@9d400000 {
reg = <0x0 0x9d400000 0x0 0x2000000>;
no-map;
};
zap_shader_region: memory@f6400000 {
compatible = "shared-dma-pool";
reg = <0x0 0xf6400000 0x0 0x2000>;
no-map;
};
ramoops@ffc00000 {
compatible = "ramoops";
reg = <0x0 0xffc00000 0x0 0x100000>;
console-size = <0x60000>;
ecc-size = <16>;
ftrace-size = <0x10000>;
pmsg-size = <0x20000>;
record-size = <0x10000>;
};
};
ts_vio_vreg: ts-vio-vreg {
compatible = "regulator-fixed";
regulator-name = "ts_vio_reg";
startup-delay-us = <2>;
enable-active-high;
gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&ts_vio_default>;
regulator-always-on;
};
};
&blsp2_i2c1 {
status = "ok";
touchscreen@14 {
compatible = "goodix,gt9286";
reg = <0x14>;
interrupt-parent = <&tlmm>;
interrupts = <125 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
AVDD28-supply = <&vreg_l28_3p0>;
VDDIO-supply = <&ts_vio_vreg>;
pinctrl-names = "active";
pinctrl-0 = <&ts_rst_n>, <&ts_int_n>;
};
};
&mmcc {
status = "ok";
};
&mmss_smmu {
status = "ok";
};
&pm8998_gpio {
vol_up_pin_a: vol-up-active {
pins = "gpio6";
function = "normal";
bias-pull-up;
input-enable;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
};
cam_focus_pin_a: cam-focus-btn-active {
pins = "gpio7";
function = "normal";
bias-pull-up;
input-enable;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
};
cam_snapshot_pin_a: cam-snapshot-btn-active {
pins = "gpio8";
function = "normal";
bias-pull-up;
input-enable;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
};
};
&pm8998_pon {
resin {
compatible = "qcom,pm8941-resin";
interrupts = <GIC_SPI 0x8 1 IRQ_TYPE_EDGE_BOTH>;
bias-pull-up;
debounce = <15625>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
&tlmm {
gpio-reserved-ranges = <0 4>;
mdp_vsync_n: mdp-vsync-n {
pins = "gpio10";
function = "mdp_vsync_a";
bias-pull-down;
drive-strength = <2>;
};
gpio_kb_pins_extra: gpio-kb-pins-extra {
pins = "gpio21", "gpio32", "gpio33", "gpio114",
"gpio128", "gpio129";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
ts_vio_default: ts-vio-def {
pins = "gpio81";
function = "gpio";
bias-disable;
drive-strength = <2>;
};
ts_rst_n: ts-rst-n {
pins = "gpio89";
function = "gpio";
bias-pull-up;
drive-strength = <8>;
};
hall_sensor1_default: hall-sensor1-def {
pins = "gpio124";
function = "gpio";
bias-disable;
drive-strength = <2>;
input-enable;
};
ts_int_n: ts-int-n {
pins = "gpio125";
function = "gpio";
bias-disable;
drive-strength = <8>;
};
};
&ufshc {
status = "ok";
};
&ufsphy {
status = "ok";
};
&usb3_dwc3 {
dr_mode = "peripheral";
extcon = <&extcon_usb>;
};
/* GT9286 analog supply */
&vreg_l28_3p0 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts 0 → 100644
View file @ c7613530
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2021, AngeloGioacchino Del Regno
* <angelogioacchino.delregno@somainline.org>
*/
/dts-v1/;
#include "msm8998-sony-xperia-yoshino.dtsi"
/ {
model = "Sony Xperia XZ1 Compact";
compatible = "sony,xperia-lilac", "qcom,msm8998";
};
&ibb {
regulator-min-microvolt = <5500000>;
regulator-max-microvolt = <5500000>;
};
&lab {
regulator-min-microvolt = <5500000>;
regulator-max-microvolt = <5500000>;
qcom,soft-start-us = <800>;
};
&vreg_l22a_2p85 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts 0 → 100644
View file @ c7613530
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2021, AngeloGioacchino Del Regno
* <angelogioacchino.delregno@somainline.org>
*/
/dts-v1/;
#include "msm8998-sony-xperia-yoshino.dtsi"
/ {
model = "Sony Xperia XZ Premium";
compatible = "sony,xperia-maple", "qcom,msm8998";
disp_dvdd_vreg: disp-dvdd-vreg {
compatible = "regulator-fixed";
regulator-name = "disp_dvdd_en";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
startup-delay-us = <0>;
enable-active-high;
gpio = <&pmi8998_gpio 10 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&disp_dvdd_en>;
};
};
&ibb {
regulator-min-microvolt = <5600000>;
regulator-max-microvolt = <5600000>;
};
&lab {
regulator-min-microvolt = <5800000>;
regulator-max-microvolt = <5800000>;
qcom,soft-start-us = <200>;
};
&pmi8998_gpio {
disp_dvdd_en: disp-dvdd-en-active {
pins = "gpio10";
function = "normal";
bias-disable;
drive-push-pull;
output-high;
power-source = <0>;
qcom,drive-strength = <1>;
};
};
&vreg_l22a_2p85 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2704000>;
};
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts 0 → 100644
View file @ c7613530
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2021, AngeloGioacchino Del Regno
* <angelogioacchino.delregno@somainline.org>
*/
/dts-v1/;
#include "msm8998-sony-xperia-yoshino.dtsi"
/ {
model = "Sony Xperia XZ1";
compatible = "sony,xperia-poplar", "qcom,msm8998";
};
&ibb {
regulator-min-microvolt = <5600000>;
regulator-max-microvolt = <5600000>;
};
&lab {
regulator-min-microvolt = <5600000>;
regulator-max-microvolt = <5600000>;
qcom,soft-start-us = <800>;
};
&vreg_l18a_2p85 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
&vreg_l22a_2p85 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
};
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi 0 → 100644
View file @ c7613530
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2021, AngeloGioacchino Del Regno
* <angelogioacchino.delregno@somainline.org>
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
*/
#include "msm8998.dtsi"
#include "pm8005.dtsi"
#include "pm8998.dtsi"
#include "pmi8998.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
/ {
/* required for bootloader to select correct board */
qcom,msm-id = <0x124 0x20000>, <0x124 0x20001>; /* 8998v2, v2.1 */
qcom,board-id = <8 0>;
clocks {
compatible = "simple-bus";
div1_mclk: divclk1 {
compatible = "gpio-gate-clock";
pinctrl-0 = <&audio_mclk_pin>;
pinctrl-names = "default";
clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
#clock-cells = <0>;
enable-gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>;
};
};
board_vbat: vbat-regulator {
compatible = "regulator-fixed";
regulator-name = "VBAT";
regulator-min-microvolt = <4000000>;
regulator-max-microvolt = <4000000>;
regulator-always-on;
regulator-boot-on;
};
cam0_vdig_vreg: cam0-vdig {
compatible = "regulator-fixed";
regulator-name = "cam0_vdig";
startup-delay-us = <0>;
enable-active-high;
gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam0_vdig_default>;
};
cam1_vdig_vreg: cam1-vdig {
compatible = "regulator-fixed";
regulator-name = "cam1_vdig";
startup-delay-us = <0>;
enable-active-high;
gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam1_vdig_default>;
vin-supply = <&vreg_s3a_1p35>;
};
cam_vio_vreg: cam-vio-vreg {
compatible = "regulator-fixed";
regulator-name = "cam_vio_vreg";
startup-delay-us = <0>;
enable-active-high;
gpio = <&pmi8998_gpio 1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam_vio_default>;
vin-supply = <&vreg_lvs1a_1p8>;
};
touch_vddio_vreg: touch-vddio-vreg {
compatible = "regulator-fixed";
regulator-name = "touch_vddio_vreg";
startup-delay-us = <10000>;
gpio = <&tlmm 133 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&ts_vddio_en>;
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-always-on;
regulator-boot-on;
};
gpio-keys {
compatible = "gpio-keys";
input-name = "gpio-keys";
label = "Side buttons";
pinctrl-names = "default";
pinctrl-0 = <&vol_down_pin_a>, <&cam_focus_pin_a>,
<&cam_snapshot_pin_a>;
vol-down {
label = "Volume Down";
gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_VOLUMEDOWN>;
gpio-key,wakeup;
debounce-interval = <15>;
};
camera-snapshot {
label = "Camera Snapshot";
gpios = <&pm8998_gpio 7 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_CAMERA>;
debounce-interval = <15>;
};
camera-focus {
label = "Camera Focus";
gpios = <&pm8998_gpio 8 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_CAMERA_FOCUS>;
debounce-interval = <15>;
};
};
gpio-hall-sensor {
compatible = "gpio-keys";
input-name = "hall-sensors";
label = "Hall sensors";
pinctrl-names = "default";
pinctrl-0 = <&hall_sensor0_default>;
hall-sensor0 {
label = "Cover Hall Sensor";
gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
gpio-key,wakeup;
debounce-interval = <30>;
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_mem: memory@85800000 {
reg = <0x0 0x85800000 0x0 0x3700000>;
no-map;
};
cont_splash_mem: memory@9d400000 {
reg = <0x0 0x9d400000 0x0 0x2400000>;
no-map;
};
zap_shader_region: memory@f6400000 {
compatible = "shared-dma-pool";
reg = <0x0 0xf6400000 0x0 0x2000>;
no-map;
};
adsp_region: memory@fe000000 {
reg = <0x0 0xfe000000 0x0 0x800000>;
no-map;
};
qseecom_region: memory@fe800000 {
reg = <0x0 0xfe800000 0x0 0x1400000>;
no-map;
};
ramoops@ffc00000 {
compatible = "ramoops";
reg = <0x0 0xffc00000 0x0 0x100000>;
record-size = <0x10000>;
console-size = <0x60000>;
ftrace-size = <0x10000>;
pmsg-size = <0x20000>;
ecc-size = <16>;
};
};
vibrator {
compatible = "gpio-vibrator";
enable-gpios = <&pmi8998_gpio 5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vib_default>;
};
};
&blsp1_i2c5 {
status = "okay";
clock-frequency = <355000>;
touchscreen@2c {
compatible = "syna,rmi4-i2c";
reg = <0x2c>;
#address-cells = <1>;
#size-cells = <0>;
interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&ts_int_n>;
vdd-supply = <&vreg_l28_3p0>;
vio-supply = <&touch_vddio_vreg>;
syna,reset-delay-ms = <220>;
syna,startup-delay-ms = <1000>;
rmi4-f01@1 {
reg = <0x01>;
syna,nosleep-mode = <1>;
};
rmi4-f11@11 {
reg = <0x11>;
syna,sensor-type = <1>;
};
};
};
&blsp1_i2c5_sleep {
bias-disable;
};
&blsp1_uart3 {
status = "okay";
bluetooth {
compatible = "qcom,wcn3990-bt";
vddio-supply = <&vreg_s4a_1p8>;
vddxo-supply = <&vreg_l7a_1p8>;
vddrf-supply = <&vreg_l17a_1p3>;
vddch0-supply = <&vreg_l25a_3p3>;
max-speed = <3200000>;
clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
};
};
&blsp2_uart1 {
status = "okay";
};
&ibb {
regulator-min-microamp = <800000>;
regulator-max-microamp = <800000>;
regulator-enable-ramp-delay = <200>;
regulator-over-current-protection;
regulator-pull-down;
regulator-ramp-delay = <1>;
regulator-settling-time-up-us = <600>;
regulator-settling-time-down-us = <1000>;
regulator-soft-start;
qcom,discharge-resistor-kohms = <300>;
};
&lab {
regulator-min-microamp = <200000>;
regulator-max-microamp = <200000>;
regulator-enable-ramp-delay = <500>;
regulator-over-current-protection;
regulator-pull-down;
regulator-ramp-delay = <1>;
regulator-settling-time-up-us = <50000>;
regulator-settling-time-down-us = <3000>;
regulator-soft-start;
};
&mmcc {
status = "ok";
};
&mmss_smmu {
status = "ok";
};
&pm8005_lsid1 {
pm8005-regulators {
compatible = "qcom,pm8005-regulators";
vdd_s1-supply = <&vph_pwr>;
/* VDD_GFX supply */
pm8005_s1: s1 {
regulator-min-microvolt = <524000>;
regulator-max-microvolt = <1088000>;
regulator-enable-ramp-delay = <500>;
regulator-always-on;
};
};
};
&pm8998_gpio {
vol_down_pin_a: vol-down-active {
pins = "gpio5";
function = PMIC_GPIO_FUNC_NORMAL;
bias-pull-up;
input-enable;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
};
cam_focus_pin_a: cam-focus-btn-active {
pins = "gpio7";
function = PMIC_GPIO_FUNC_NORMAL;
bias-pull-up;
input-enable;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
};
cam_snapshot_pin_a: cam-snapshot-btn-active {
pins = "gpio8";
function = PMIC_GPIO_FUNC_NORMAL;
bias-pull-up;
input-enable;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
};
audio_mclk_pin: audio-mclk-pin-active {
pins = "gpio13";
function = "func2";
power-source = <0>;
};
};
&pmi8998_gpio {
cam_vio_default: cam-vio-active {
pins = "gpio1";
function = PMIC_GPIO_FUNC_NORMAL;
bias-disable;
drive-push-pull;
output-low;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
power-source = <1>;
};
vib_default: vib-en {
pins = "gpio5";
function = PMIC_GPIO_FUNC_NORMAL;
bias-disable;
drive-push-pull;
output-low;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
power-source = <0>;
};
};
&pm8998_pon {
resin {
compatible = "qcom,pm8941-resin";
interrupts = <GIC_SPI 0x8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_VOLUMEUP>;
};
};
&qusb2phy {
status = "okay";
vdda-pll-supply = <&vreg_l12a_1p8>;
vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
};
&rpm_requests {
pm8998-regulators {
compatible = "qcom,rpm-pm8998-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_s2-supply = <&vph_pwr>;
vdd_s3-supply = <&vph_pwr>;
vdd_s4-supply = <&vph_pwr>;
vdd_s5-supply = <&vph_pwr>;
vdd_s6-supply = <&vph_pwr>;
vdd_s7-supply = <&vph_pwr>;
vdd_s8-supply = <&vph_pwr>;
vdd_s9-supply = <&vph_pwr>;
vdd_s10-supply = <&vph_pwr>;
vdd_s11-supply = <&vph_pwr>;
vdd_s12-supply = <&vph_pwr>;
vdd_s13-supply = <&vph_pwr>;
vdd_l1_l27-supply = <&vreg_s7a_1p025>;
vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>;
vdd_l3_l11-supply = <&vreg_s7a_1p025>;
vdd_l4_l5-supply = <&vreg_s7a_1p025>;
vdd_l6-supply = <&vreg_s5a_2p04>;
vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>;
vdd_l9-supply = <&vreg_bob>;
vdd_l10_l23_l25-supply = <&vreg_bob>;
vdd_l13_l19_l21-supply = <&vreg_bob>;
vdd_l16_l28-supply = <&vreg_bob>;
vdd_l18_l22-supply = <&vreg_bob>;
vdd_l20_l24-supply = <&vreg_bob>;
vdd_l26-supply = <&vreg_s3a_1p35>;
vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>;
vreg_s3a_1p35: s3 {
regulator-min-microvolt = <1352000>;
regulator-max-microvolt = <1352000>;
};
vreg_s4a_1p8: s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-system-load = <100000>;
regulator-allow-set-load;
};
vreg_s5a_2p04: s5 {
regulator-min-microvolt = <1904000>;
regulator-max-microvolt = <2032000>;
};
vreg_s7a_1p025: s7 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1028000>;
};
vreg_l1a_0p875: l1 {
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
regulator-system-load = <73400>;
regulator-allow-set-load;
};
vreg_l2a_1p2: l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-system-load = <12560>;
regulator-allow-set-load;
};
vreg_l3a_1p0: l3 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
vreg_l5a_0p8: l5 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
};
vreg_l6a_1p8: l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l7a_1p8: l7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l8a_1p2: l8 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
vreg_l9a_1p8: l9 {
regulator-min-microvolt = <1808000>;
regulator-max-microvolt = <2960000>;
};
vreg_l10a_1p8: l10 {
regulator-min-microvolt = <1808000>;
regulator-max-microvolt = <2960000>;
};
vreg_l11a_1p0: l11 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
vreg_l12a_1p8: l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l13a_2p95: l13 {
regulator-min-microvolt = <1808000>;
regulator-max-microvolt = <2960000>;
regulator-allow-set-load;
};
vreg_l14a_1p85: l14 {
regulator-min-microvolt = <1848000>;
regulator-max-microvolt = <1856000>;
regulator-system-load = <32000>;
regulator-allow-set-load;
};
vreg_l15a_1p8: l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l16a_2p7: l16 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2704000>;
};
vreg_l17a_1p3: l17 {
regulator-min-microvolt = <1304000>;
regulator-max-microvolt = <1304000>;
};
vreg_l18a_2p85: l18 {};
vreg_l19a_2p7: l19 {
regulator-min-microvolt = <2696000>;
regulator-max-microvolt = <2704000>;
};
vreg_l20a_2p95: l20 {
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <2960000>;
regulator-system-load = <10000>;
regulator-allow-set-load;
};
vreg_l21a_2p95: l21 {
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <2960000>;
regulator-system-load = <800000>;
regulator-allow-set-load;
};
vreg_l22a_2p85: l22 { };
vreg_l23a_3p3: l23 {
regulator-min-microvolt = <3312000>;
regulator-max-microvolt = <3312000>;
};
vreg_l24a_3p075: l24 {
regulator-min-microvolt = <3088000>;
regulator-max-microvolt = <3088000>;
};
vreg_l25a_3p3: l25 {
regulator-min-microvolt = <3104000>;
regulator-max-microvolt = <3312000>;
};
vreg_l26a_1p2: l26 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-allow-set-load;
};
vreg_l28_3p0: l28 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
vreg_lvs1a_1p8: lvs1 { };
vreg_lvs2a_1p8: lvs2 { };
};
pmi8998-regulators {
compatible = "qcom,rpm-pmi8998-regulators";
vdd_bob-supply = <&vph_pwr>;
vreg_bob: bob {
regulator-min-microvolt = <3312000>;
regulator-max-microvolt = <3600000>;
};
};
};
&sdhc2 {
status = "okay";
cd-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&vreg_l21a_2p95>;
vqmmc-supply = <&vreg_l13a_2p95>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
};
&tlmm {
gpio-reserved-ranges = <0 4>, <81 4>;
mdp_vsync_n: mdp-vsync-n {
pins = "gpio10";
function = "mdp_vsync_a";
drive-strength = <2>;
bias-pull-down;
};
nfc_ven: nfc-ven {
pins = "gpio12";
function = "gpio";
bias-disable;
drive-strength = <2>;
output-low;
};
msm_mclk0_default: msm-mclk0-active {
pins = "gpio13";
function = "cam_mclk";
drive-strength = <2>;
bias-disable;
};
msm_mclk1_default: msm-mclk1-active {
pins = "gpio14";
function = "cam_mclk";
drive-strength = <2>;
bias-disable;
};
cci0_default: cci0-default {
pins = "gpio18", "gpio19";
function = "cci_i2c";
bias-disable;
drive-strength = <2>;
};
cci1_default: cci1-default {
pins = "gpio19", "gpio20";
function = "cci_i2c";
bias-disable;
drive-strength = <2>;
};
cam0_vdig_default: cam0-vdig-default {
pins = "gpio21";
function = "gpio";
bias-disable;
drive-strength = <2>;
};
cam1_vdig_default: cam1-vdig-default {
pins = "gpio25";
function = "gpio";
bias-disable;
drive-strength = <2>;
};
hall_sensor0_default: acc-cover-open {
pins = "gpio124";
function = "gpio";
bias-disable;
drive-strength = <2>;
input-enable;
};
ts_int_n: ts-int-n {
pins = "gpio125";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
ts_vddio_en: ts-vddio-en-default {
pins = "gpio133";
function = "gpio";
bias-disable;
drive-strength = <2>;
output-low;
};
};
/*
* WARNING:
* Disable UFS until card quirks are in to avoid unrecoverable hard-brick
* that would happen as soon as the UFS card gets probed as, without the
* required quirks, the bootloader will be erased right after card probe.
*/
&ufshc {
status = "disabled";
};
&ufsphy {
status = "disabled";
};
&usb3 {
status = "okay";
};
&usb3_dwc3 {
/* Force to peripheral until we have Type-C hooked up */
dr_mode = "peripheral";
};
&usb3phy {
status = "okay";
vdda-phy-supply = <&vreg_l1a_0p875>;
vdda-pll-supply = <&vreg_l2a_1p2>;
};
arch/arm64/boot/dts/qcom/msm8998.dtsi
View file @ c7613530
......@@ -4,6 +4,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
#include <dt-bindings/clock/qcom,gpucc-msm8998.h>
#include <dt-bindings/clock/qcom,mmcc-msm8998.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/gpio/gpio.h>
......@@ -117,7 +118,7 @@ xo: xo-board {
clock-output-names = "xo_board";
};
sleep_clk {
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32764>;
......@@ -308,38 +309,42 @@ idle-states {
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "little-retention";
/* CPU Retention (C2D), L2 Active */
arm,psci-suspend-param = <0x00000002>;
entry-latency-us = <81>;
exit-latency-us = <86>;
min-residency-us = <200>;
min-residency-us = <504>;
};
LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "little-power-collapse";
/* CPU + L2 Power Collapse (C3, D4) */
arm,psci-suspend-param = <0x40000003>;
entry-latency-us = <273>;
exit-latency-us = <612>;
min-residency-us = <1000>;
entry-latency-us = <814>;
exit-latency-us = <4562>;
min-residency-us = <9183>;
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "big-retention";
/* CPU Retention (C2D), L2 Active */
arm,psci-suspend-param = <0x00000002>;
entry-latency-us = <79>;
exit-latency-us = <82>;
min-residency-us = <200>;
min-residency-us = <1302>;
};
BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "big-power-collapse";
/* CPU + L2 Power Collapse (C3, D4) */
arm,psci-suspend-param = <0x40000003>;
entry-latency-us = <336>;
exit-latency-us = <525>;
min-residency-us = <1000>;
entry-latency-us = <724>;
exit-latency-us = <2027>;
min-residency-us = <9419>;
local-timer-stop;
};
};
......@@ -855,6 +860,9 @@ gcc: clock-controller@100000 {
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x00100000 0xb0000>;
clock-names = "xo", "sleep_clk";
clocks = <&xo>, <&sleep_clk>;
};
rpm_msg_ram: memory@778000 {
......@@ -862,14 +870,14 @@ rpm_msg_ram: memory@778000 {
reg = <0x00778000 0x7000>;
};
qfprom: qfprom@780000 {
qfprom: qfprom@784000 {
compatible = "qcom,qfprom";
reg = <0x00780000 0x621c>;
reg = <0x00784000 0x621c>;
#address-cells = <1>;
#size-cells = <1>;
qusb2_hstx_trim: hstx-trim@423a {
reg = <0x423a 0x1>;
qusb2_hstx_trim: hstx-trim@23a {
reg = <0x23a 0x1>;
bits = <0 4>;
};
};
......@@ -1416,6 +1424,103 @@ glink-edge {
};
};
adreno_gpu: gpu@5000000 {
compatible = "qcom,adreno-540.1", "qcom,adreno";
reg = <0x05000000 0x40000>;
reg-names = "kgsl_3d0_reg_memory";
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
<&gpucc RBBMTIMER_CLK>,
<&gcc GCC_BIMC_GFX_CLK>,
<&gcc GCC_GPU_BIMC_GFX_CLK>,
<&gpucc RBCPR_CLK>,
<&gpucc GFX3D_CLK>;
clock-names = "iface",
"rbbmtimer",
"mem",
"mem_iface",
"rbcpr",
"core";
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&adreno_smmu 0>;
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&rpmpd MSM8998_VDDMX>;
#stream-id-cells = <16>;
status = "disabled";
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-710000097 {
opp-hz = /bits/ 64 <710000097>;
opp-level = <RPM_SMD_LEVEL_TURBO>;
opp-supported-hw = <0xFF>;
};
opp-670000048 {
opp-hz = /bits/ 64 <670000048>;
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
opp-supported-hw = <0xFF>;
};
opp-596000097 {
opp-hz = /bits/ 64 <596000097>;
opp-level = <RPM_SMD_LEVEL_NOM>;
opp-supported-hw = <0xFF>;
};
opp-515000097 {
opp-hz = /bits/ 64 <515000097>;
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
opp-supported-hw = <0xFF>;
};
opp-414000000 {
opp-hz = /bits/ 64 <414000000>;
opp-level = <RPM_SMD_LEVEL_SVS>;
opp-supported-hw = <0xFF>;
};
opp-342000000 {
opp-hz = /bits/ 64 <342000000>;
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
opp-supported-hw = <0xFF>;
};
opp-257000000 {
opp-hz = /bits/ 64 <257000000>;
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
opp-supported-hw = <0xFF>;
};
};
};
adreno_smmu: iommu@5040000 {
compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
reg = <0x05040000 0x10000>;
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
<&gcc GCC_BIMC_GFX_CLK>,
<&gcc GCC_GPU_BIMC_GFX_CLK>;
clock-names = "iface", "mem", "mem_iface";
#global-interrupts = <0>;
#iommu-cells = <1>;
interrupts =
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
/*
* GPU-GX GDSC's parent is GPU-CX. We need to bring up the
* GPU-CX for SMMU but we need both of them up for Adreno.
* Contemporarily, we also need to manage the VDDMX rpmpd
* domain in the Adreno driver.
* Enable GPU CX/GX GDSCs here so that we can manage the
* SoC VDDMX RPM Power Domain in the Adreno driver.
*/
power-domains = <&gpucc GPU_GX_GDSC>;
status = "disabled";
};
gpucc: clock-controller@5065000 {
compatible = "qcom,msm8998-gpucc";
#clock-cells = <1>;
......@@ -2187,7 +2292,7 @@ blsp1_i2c6: i2c@c17a000 {
#size-cells = <0>;
};
blsp2_dma: dma@c184000 {
blsp2_dma: dma-controller@c184000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0c184000 0x25000>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
......@@ -2330,6 +2435,73 @@ blsp2_i2c6: i2c@c1ba000 {
#size-cells = <0>;
};
mmcc: clock-controller@c8c0000 {
compatible = "qcom,mmcc-msm8998";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0xc8c0000 0x40000>;
status = "disabled";
clock-names = "xo",
"gpll0",
"dsi0dsi",
"dsi0byte",
"dsi1dsi",
"dsi1byte",
"hdmipll",
"dplink",
"dpvco",
"core_bi_pll_test_se";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_MMSS_GPLL0_CLK>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>;
};
mmss_smmu: iommu@cd00000 {
compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
reg = <0x0cd00000 0x40000>;
#iommu-cells = <1>;
clocks = <&mmcc MNOC_AHB_CLK>,
<&mmcc BIMC_SMMU_AHB_CLK>,
<&rpmcc RPM_SMD_MMAXI_CLK>,
<&mmcc BIMC_SMMU_AXI_CLK>;
clock-names = "iface-mm", "iface-smmu",
"bus-mm", "bus-smmu";
status = "disabled";
#global-interrupts = <0>;
interrupts =
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
};
remoteproc_adsp: remoteproc@17300000 {
compatible = "qcom,msm8998-adsp-pas";
reg = <0x17300000 0x4040>;
......
arch/arm64/boot/dts/qcom/pm6150l.dtsi
View file @ c7613530
// SPDX-License-Identifier: BSD-3-Clause
// Copyright (c) 2019, The Linux Foundation. All rights reserved.
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
......
arch/arm64/boot/dts/qcom/pm660.dtsi
View file @ c7613530
......@@ -49,9 +49,10 @@ rtc@6000 {
};
pon: pon@800 {
compatible = "qcom,pm8916-pon";
compatible = "qcom,pm8998-pon";
reg = <0x800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
......
arch/arm64/boot/dts/qcom/pm8150.dtsi
View file @ c7613530
......@@ -48,8 +48,10 @@ pm8150_0: pmic@0 {
#size-cells = <0>;
pon: power-on@800 {
compatible = "qcom,pm8916-pon";
compatible = "qcom,pm8998-pon";
reg = <0x0800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pon_pwrkey: pwrkey {
compatible = "qcom,pm8941-pwrkey";
......
arch/arm64/boot/dts/qcom/pm8916.dtsi
View file @ c7613530
......@@ -41,6 +41,14 @@ watchdog {
};
};
pm8916_usbin: extcon@1300 {
compatible = "qcom,pm8941-misc";
reg = <0x1300>;
interrupts = <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "usb_vbus";
status = "disabled";
};
pm8916_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
......@@ -86,7 +94,6 @@ adc-chan@f {
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
......
arch/arm64/boot/dts/qcom/pmi8998.dtsi
View file @ c7613530
......@@ -41,5 +41,17 @@ lab: lab {
interrupt-names = "sc-err", "ocp";
};
};
pmi8998_wled: leds@d800 {
compatible = "qcom,pmi8998-wled";
reg = <0xd800 0xd900>;
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
<0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp", "short";
label = "backlight";
status = "disabled";
};
};
};
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
View file @ c7613530
......@@ -804,6 +804,16 @@ lt9611_rst_pin: lt9611-rst-pin {
};
};
&pon_pwrkey {
status = "okay";
};
&pon_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
};
&qupv3_id_0 {
status = "okay";
};
......
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts
View file @ c7613530
......@@ -23,6 +23,20 @@ &charger_thermal {
status = "disabled";
};
&pm6150_adc {
status = "disabled";
/delete-node/ skin-temp-thermistor@4e;
/delete-node/ charger-thermistor@4f;
};
&pm6150_adc_tm {
status = "disabled";
/delete-node/ charger-thermistor@0;
/delete-node/ skin-temp-thermistor@1;
};
/*
* CoachZ rev1 is stuffed with a 47k NTC as thermistor for skin temperature,
* which currently is not supported by the PM6150 ADC driver. Disable the
......
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
View file @ c7613530
......@@ -33,7 +33,7 @@ skin_temp_thermal: skin-temp-thermal {
polling-delay = <0>;
thermal-sensors = <&pm6150_adc_tm 1>;
sustainable-power = <814>;
sustainable-power = <965>;
trips {
skin_temp_alert0: trip-point0 {
......
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts 0 → 100644
View file @ c7613530
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Homestar board device tree source
*
* Copyright 2021 Google LLC.
*/
/dts-v1/;
#include "sc7180-trogdor-homestar.dtsi"
/ {
model = "Google Homestar (rev2)";
compatible = "google,homestar-rev2","google,homestar-rev23", "qcom,sc7180";
};
&panel {
/delete-property/hpd-gpios;
no-hpd;
};
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts 0 → 100644
View file @ c7613530
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Homestar board device tree source
*
* Copyright 2021 Google LLC.
*/
/dts-v1/;
#include "sc7180-trogdor-homestar.dtsi"
/ {
model = "Google Homestar (rev3+)";
compatible = "google,homestar", "qcom,sc7180";
};
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi 0 → 100644
View file @ c7613530
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Homestar board device tree source
*
* Copyright 2021 Google LLC.
*/
#include "sc7180.dtsi"
ap_ec_spi: &spi6 {};
ap_h1_spi: &spi0 {};
#include "sc7180-trogdor.dtsi"
/ {
/* BOARD-SPECIFIC TOP LEVEL NODES */
max98360a_1: max98360a_1 {
compatible = "maxim,max98360a";
#sound-dai-cells = <0>;
};
max98360a_2: max98360a_2 {
compatible = "maxim,max98360a";
#sound-dai-cells = <0>;
};
max98360a_3: max98360a_3 {
compatible = "maxim,max98360a";
#sound-dai-cells = <0>;
};
pp3300_touch: pp3300-touch {
compatible = "regulator-fixed";
regulator-name = "pp3300_touch";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&en_pp3300_touch>;
vin-supply = <&pp3300_a>;
};
thermal-zones {
skin_temp_thermal: skin-temp-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&pm6150_adc_tm 1>;
sustainable-power = <965>;
trips {
skin_temp_alert0: trip-point0 {
temperature = <55000>;
hysteresis = <1000>;
type = "passive";
};
skin_temp_alert1: trip-point1 {
temperature = <58000>;
hysteresis = <1000>;
type = "passive";
};
skin-temp-crit {
temperature = <73000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&skin_temp_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&skin_temp_alert1>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
};
&ap_tp_i2c {
status = "disabled";
};
ap_ts_pen_1v8: &i2c4 {
status = "okay";
clock-frequency = <400000>;
ap_ts: touchscreen@14 {
compatible = "goodix,gt7375p";
reg = <0x14>;
pinctrl-names = "default";
pinctrl-0 = <&ts_int_l>, <&ts_reset_l>;
interrupt-parent = <&tlmm>;
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
vdd-supply = <&pp3300_touch>;
};
};
/* Panel controls backlight over aux channel */
&backlight {
status = "disabled";
};
&camcc {
status = "okay";
};
&panel {
compatible = "samsung,atna33xc20";
enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
/delete-property/ backlight;
};
&pm6150_adc {
skin-temp-thermistor@4d {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
};
&pm6150_adc_tm {
status = "okay";
skin-temp-thermistor@1 {
reg = <1>;
io-channels = <&pm6150_adc ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
};
&pp3300_dx_edp {
gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>;
};
&secondary_mi2s {
qcom,playback-sd-lines = <0 1>;
};
&sound_multimedia1_codec {
sound-dai = <&max98360a>, <&max98360a_1>, <&max98360a_2>, <&max98360a_3> ;
};
&wifi {
qcom,ath10k-calibration-variant = "GO_HOMESTAR";
};
/* PINCTRL - modifications to sc7180-trogdor.dtsi */
&en_pp3300_dx_edp {
pinmux {
pins = "gpio67";
};
pinconf {
pins = "gpio67";
};
};
&sec_mi2s_active{
pinmux {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
function = "mi2s_1";
};
};
&ts_reset_l {
pinconf {
/*
* We want reset state by default and it will be up to the
* driver to disable this when it's ready.
*/
output-low;
};
};
/* PINCTRL - board-specific pinctrl */
&tlmm {
gpio-line-names = "HUB_RST_L",
"AP_RAM_ID0",
"AP_SKU_ID2",
"AP_RAM_ID1",
"",
"AP_RAM_ID2",
"UF_CAM_EN",
"WF_CAM_EN",
"TS_RESET_L",
"TS_INT_L",
"",
"EDP_BRIJ_IRQ",
"AP_EDP_BKLTEN",
"UF_CAM_MCLK",
"WF_CAM_CLK",
"EDP_BRIJ_I2C_SDA",
"EDP_BRIJ_I2C_SCL",
"UF_CAM_SDA",
"UF_CAM_SCL",
"WF_CAM_SDA",
"WF_CAM_SCL",
"AVEE_LCD_EN",
"",
"AMP_EN",
"AMP_EN2",
"AP_SAR_SENSOR_SDA",
"AP_SAR_SENSOR_SCL",
"SEL_LCM",
"HP_IRQ",
"WF_CAM_RST_L",
"UF_CAM_RST_L",
"AP_BRD_ID2",
"BRIJ_SUSPEND",
"AP_BRD_ID0",
"AP_H1_SPI_MISO",
"AP_H1_SPI_MOSI",
"AP_H1_SPI_CLK",
"AP_H1_SPI_CS_L",
"BT_UART_CTS",
"BT_UART_RTS",
"BT_UART_TXD",
"BT_UART_RXD",
"H1_AP_INT_ODL",
"",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"HP_I2C_SDA",
"HP_I2C_SCL",
"FORCED_USB_BOOT",
"AMP_BCLK",
"AMP_LRCLK",
"AMP_DIN",
"AMP_DIN_2",
"HP_BCLK",
"HP_LRCLK",
"HP_DOUT",
"HP_DIN",
"HP_MCLK",
"AP_SKU_ID0",
"AP_EC_SPI_MISO",
"AP_EC_SPI_MOSI",
"AP_EC_SPI_CLK",
"AP_EC_SPI_CS_L",
"AP_SPI_CLK",
"AP_SPI_MOSI",
"AP_SPI_MISO",
/*
* AP_FLASH_WP_L is crossystem ABI. Schematics
* call it BIOS_FLASH_WP_L.
*/
"AP_FLASH_WP_L",
"EN_PP3300_DX_EDP",
"AP_SPI_CS0_L",
"SD_CD_ODL",
"",
"",
"",
"WLAN_SW_CTRL",
"",
"REPORT_E",
"VDD_RESET_1.8V",
"ID0",
"",
"ID1",
"AVDD_LCD_EN",
"MIPI_1.8V_EN",
"",
"CODEC_PWR_EN",
"HUB_EN",
"",
"PP1800_MIPI_SW_EN",
"EN_PP3300_TOUCH",
"",
"",
"AP_SKU_ID1",
"AP_RST_REQ",
"",
"AP_BRD_ID1",
"AP_EC_INT_L",
"SDM_GRFC_3",
"",
"",
"BOOT_CONFIG_4",
"BOOT_CONFIG_2",
"",
"",
"",
"",
"EDP_BRIJ_EN",
"",
"",
"BOOT_CONFIG_3",
"WCI2_LTE_COEX_TXD",
"WCI2_LTE_COEX_RXD",
"",
"",
"",
"",
"FORCED_USB_BOOT_POL",
"AP_TS_PEN_I2C_SDA",
"AP_TS_PEN_I2C_SCL",
"DP_HOT_PLUG_DET",
"EC_IN_RW_ODL";
en_pp3300_touch: en-pp3300-touch {
pinmux {
pins = "gpio87";
function = "gpio";
};
pinconf {
pins = "gpio87";
drive-strength = <2>;
bias-disable;
};
};
};
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
View file @ c7613530
......@@ -54,6 +54,18 @@ &panel {
compatible = "boe,nv133fhm-n62";
};
&pm6150_adc {
status = "disabled";
/delete-node/ charger-thermistor@4f;
};
&pm6150_adc_tm {
status = "disabled";
/delete-node/ charger-thermistor@0;
};
&trackpad {
interrupts = <58 IRQ_TYPE_EDGE_FALLING>;
};
......
arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi
View file @ c7613530
......@@ -17,3 +17,14 @@ &remoteproc_mpss {
firmware-name = "qcom/sc7180-trogdor/modem/mba.mbn",
"qcom/sc7180-trogdor/modem/qdsp6sw.mbn";
};
&ipa {
status = "okay";
/*
* Trogdor doesn't have QHEE (Qualcomm's EL2 blob), so the
* modem needs to cover certain init steps (GSI init), and
* the AP needs to wait for it.
*/
modem-init;
};
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts
View file @ c7613530
......@@ -26,6 +26,14 @@ &charger_thermal {
status = "disabled";
};
&pm6150_adc {
/delete-node/ charger-thermistor@4f;
};
&pm6150_adc_tm {
/delete-node/ charger-thermistor@0;
};
&pp3300_hub {
/* pp3300_l7c is used to power the USB hub */
/delete-property/regulator-always-on;
......
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts
View file @ c7613530
......@@ -22,3 +22,11 @@ / {
&charger_thermal {
status = "disabled";
};
&pm6150_adc {
/delete-node/ charger-thermistor@4f;
};
&pm6150_adc_tm {
/delete-node/ charger-thermistor@0;
};
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi
View file @ c7613530
......@@ -44,7 +44,7 @@ &cpu6_alert1 {
};
&cpu6_thermal {
sustainable-power = <948>;
sustainable-power = <1124>;
};
&cpu7_alert0 {
......@@ -56,7 +56,7 @@ &cpu7_alert1 {
};
&cpu7_thermal {
sustainable-power = <948>;
sustainable-power = <1124>;
};
&cpu8_alert0 {
......@@ -68,7 +68,7 @@ &cpu8_alert1 {
};
&cpu8_thermal {
sustainable-power = <948>;
sustainable-power = <1124>;
};
&cpu9_alert0 {
......@@ -80,7 +80,7 @@ &cpu9_alert1 {
};
&cpu9_thermal {
sustainable-power = <948>;
sustainable-power = <1124>;
};
&gpio_keys {
......
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
View file @ c7613530
......@@ -751,17 +751,6 @@ alc5682: codec@1a {
};
};
&ipa {
status = "okay";
/*
* Trogdor doesn't have QHEE (Qualcomm's EL2 blob), so the
* modem needs to cover certain init steps (GSI init), and
* the AP needs to wait for it.
*/
modem-init;
};
&lpass_cpu {
status = "okay";
......@@ -1524,13 +1513,13 @@ pinconf-clk {
pinconf-cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
drive-strength = <16>;
};
pinconf-data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
drive-strength = <16>;
};
pinconf-rclk {
......
arch/arm64/boot/dts/qcom/sc7180.dtsi
View file @ c7613530
......@@ -15,7 +15,6 @@
#include <dt-bindings/interconnect/qcom,sc7180.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
......@@ -137,8 +136,8 @@ CPU0: cpu@0 {
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
......@@ -162,8 +161,8 @@ CPU1: cpu@100 {
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_100>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
......@@ -184,8 +183,8 @@ CPU2: cpu@200 {
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_200>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
......@@ -206,8 +205,8 @@ CPU3: cpu@300 {
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_300>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
......@@ -228,8 +227,8 @@ CPU4: cpu@400 {
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_400>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
......@@ -250,8 +249,8 @@ CPU5: cpu@500 {
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_500>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
......@@ -272,8 +271,8 @@ CPU6: cpu@600 {
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <405>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <480>;
next-level-cache = <&L2_600>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
......@@ -294,8 +293,8 @@ CPU7: cpu@700 {
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <405>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <480>;
next-level-cache = <&L2_700>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
......@@ -1922,14 +1921,15 @@ remoteproc_mpss: remoteproc@4080000 {
clock-names = "iface", "bus", "nav", "snoc_axi",
"mnoc_axi", "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
<&rpmhpd SC7180_CX>,
power-domains = <&rpmhpd SC7180_CX>,
<&rpmhpd SC7180_MX>,
<&rpmhpd SC7180_MSS>;
power-domain-names = "load_state", "cx", "mx", "mss";
power-domain-names = "cx", "mx", "mss";
memory-region = <&mpss_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
......@@ -3224,7 +3224,6 @@ aoss_qmp: power-controller@c300000 {
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
#power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
......@@ -3246,6 +3245,21 @@ spmi_bus: spmi@c440000 {
cell-index = <0>;
};
imem@146aa000 {
compatible = "simple-mfd";
reg = <0 0x146aa000 0 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x146aa000 0x2000>;
pil-reloc@94c {
compatible = "qcom,pil-reloc-info";
reg = <0x94c 0xc8>;
};
};
apps_smmu: iommu@15000000 {
compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
......@@ -3616,7 +3630,7 @@ cpu0_thermal: cpu0-thermal {
polling-delay = <0>;
thermal-sensors = <&tsens0 1>;
sustainable-power = <768>;
sustainable-power = <1052>;
trips {
cpu0_alert0: trip-point0 {
......@@ -3665,7 +3679,7 @@ cpu1_thermal: cpu1-thermal {
polling-delay = <0>;
thermal-sensors = <&tsens0 2>;
sustainable-power = <768>;
sustainable-power = <1052>;
trips {
cpu1_alert0: trip-point0 {
......@@ -3714,7 +3728,7 @@ cpu2_thermal: cpu2-thermal {
polling-delay = <0>;
thermal-sensors = <&tsens0 3>;
sustainable-power = <768>;
sustainable-power = <1052>;
trips {
cpu2_alert0: trip-point0 {
......@@ -3763,7 +3777,7 @@ cpu3_thermal: cpu3-thermal {
polling-delay = <0>;
thermal-sensors = <&tsens0 4>;
sustainable-power = <768>;
sustainable-power = <1052>;
trips {
cpu3_alert0: trip-point0 {
......@@ -3812,7 +3826,7 @@ cpu4_thermal: cpu4-thermal {
polling-delay = <0>;
thermal-sensors = <&tsens0 5>;
sustainable-power = <768>;
sustainable-power = <1052>;
trips {
cpu4_alert0: trip-point0 {
......@@ -3861,7 +3875,7 @@ cpu5_thermal: cpu5-thermal {
polling-delay = <0>;
thermal-sensors = <&tsens0 6>;
sustainable-power = <768>;
sustainable-power = <1052>;
trips {
cpu5_alert0: trip-point0 {
......@@ -3910,7 +3924,7 @@ cpu6_thermal: cpu6-thermal {
polling-delay = <0>;
thermal-sensors = <&tsens0 9>;
sustainable-power = <1202>;
sustainable-power = <1425>;
trips {
cpu6_alert0: trip-point0 {
......@@ -3951,7 +3965,7 @@ cpu7_thermal: cpu7-thermal {
polling-delay = <0>;
thermal-sensors = <&tsens0 10>;
sustainable-power = <1202>;
sustainable-power = <1425>;
trips {
cpu7_alert0: trip-point0 {
......@@ -3992,7 +4006,7 @@ cpu8_thermal: cpu8-thermal {
polling-delay = <0>;
thermal-sensors = <&tsens0 11>;
sustainable-power = <1202>;
sustainable-power = <1425>;
trips {
cpu8_alert0: trip-point0 {
......@@ -4033,7 +4047,7 @@ cpu9_thermal: cpu9-thermal {
polling-delay = <0>;
thermal-sensors = <&tsens0 12>;
sustainable-power = <1202>;
sustainable-power = <1425>;
trips {
cpu9_alert0: trip-point0 {
......
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
View file @ c7613530
......@@ -7,11 +7,84 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
#include <dt-bindings/input/linux-event-codes.h>
#include "sc7280.dtsi"
#include "pm7325.dtsi"
#include "pm8350c.dtsi"
#include "pmk8350.dtsi"
/ {
gpio-keys {
compatible = "gpio-keys";
label = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_vol_up_default>;
volume-up {
label = "volume_up";
gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEUP>;
gpio-key,wakeup;
debounce-interval = <15>;
linux,can-disable;
};
};
};
/*
* Reserved memory changes
*
* Delete all unused memory nodes and define the peripheral memory regions
* required by the board dts.
*
*/
/delete-node/ &hyp_mem;
/delete-node/ &xbl_mem;
/delete-node/ &reserved_xbl_uefi_log;
/delete-node/ &sec_apps_mem;
/* Increase the size from 2.5MB to 8MB */
&rmtfs_mem {
reg = <0x0 0x9c900000 0x0 0x800000>;
};
/ {
reserved-memory {
adsp_mem: memory@86700000 {
reg = <0x0 0x86700000 0x0 0x2800000>;
no-map;
};
camera_mem: memory@8ad00000 {
reg = <0x0 0x8ad00000 0x0 0x500000>;
no-map;
};
venus_mem: memory@8b200000 {
reg = <0x0 0x8b200000 0x0 0x500000>;
no-map;
};
mpss_mem: memory@8b800000 {
reg = <0x0 0x8b800000 0x0 0xf600000>;
no-map;
};
wpss_mem: memory@9ae00000 {
reg = <0x0 0x9ae00000 0x0 0x1900000>;
no-map;
};
mba_mem: memory@9c700000 {
reg = <0x0 0x9c700000 0x0 0x200000>;
no-map;
};
};
};
&apps_rsc {
pm7325-regulators {
compatible = "qcom,pm7325-rpmh-regulators";
......@@ -207,10 +280,39 @@ pmk8350_die_temp {
};
};
&qfprom {
vcc-supply = <&vreg_l1c_1p8>;
};
&qspi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <37500000>;
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};
};
&qupv3_id_0 {
status = "okay";
};
&qupv3_id_1 {
status = "okay";
};
&remoteproc_mpss {
status = "okay";
compatible = "qcom,sc7280-mss-pil";
iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
memory-region = <&mba_mem &mpss_mem>;
};
&sdhc_1 {
status = "okay";
......@@ -240,6 +342,7 @@ &sdhc_2 {
};
&uart5 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};
......@@ -282,18 +385,123 @@ &usb_2_hsphy {
vdda18-supply = <&vreg_l1c_1p8>;
};
&uart7 {
status = "okay";
/delete-property/interrupts;
interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default", "sleep";
pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
};
/* PINCTRL - additions to nodes defined in sc7280.dtsi */
&qup_uart5_default {
tx {
pins = "gpio46";
&pm7325_gpios {
key_vol_up_default: key-vol-up-default {
pins = "gpio6";
function = "normal";
input-enable;
bias-pull-up;
power-source = <0>;
qcom,drive-strength = <3>;
};
};
&qspi_cs0 {
bias-disable;
};
&qspi_clk {
bias-disable;
};
&qspi_data01 {
/* High-Z when no transfers; nice to park the lines */
bias-pull-up;
};
&qup_uart5_tx {
drive-strength = <2>;
bias-disable;
};
};
&qup_uart5_rx {
drive-strength = <2>;
bias-pull-up;
};
&qup_uart7_cts {
/*
* Configure a pull-down on CTS to match the pull of
* the Bluetooth module.
*/
bias-pull-down;
};
&qup_uart7_rts {
/* We'll drive RTS, so no pull */
drive-strength = <2>;
bias-disable;
};
rx {
pins = "gpio47";
&qup_uart7_tx {
/* We'll drive TX, so no pull */
drive-strength = <2>;
bias-disable;
};
&qup_uart7_rx {
/*
* Configure a pull-up on RX. This is needed to avoid
* garbage data when the TX pin of the Bluetooth module is
* in tri-state (module powered off or not driving the
* signal yet).
*/
bias-pull-up;
};
&tlmm {
qup_uart7_sleep_cts: qup-uart7-sleep-cts {
pins = "gpio28";
function = "gpio";
/*
* Configure a pull-down on CTS to match the pull of
* the Bluetooth module.
*/
bias-pull-down;
};
qup_uart7_sleep_rts: qup-uart7-sleep-rts {
pins = "gpio29";
function = "gpio";
/*
* Configure pull-down on RTS. As RTS is active low
* signal, pull it low to indicate the BT SoC that it
* can wakeup the system anytime from suspend state by
* pulling RX low (by sending wakeup bytes).
*/
bias-pull-down;
};
qup_uart7_sleep_tx: qup-uart7-sleep-tx {
pins = "gpio30";
function = "gpio";
/*
* Configure pull-up on TX when it isn't actively driven
* to prevent BT SoC from receiving garbage during sleep.
*/
bias-pull-up;
};
qup_uart7_sleep_rx: qup-uart7-sleep-rx {
pins = "gpio31";
function = "gpio";
/*
* Configure a pull-up on RX. This is needed to avoid
* garbage data when the TX pin of the Bluetooth module
* is floating which may cause spurious wakeups.
*/
bias-pull-up;
};
};
......@@ -336,6 +544,7 @@ data {
};
sd-cd {
pins = "gpio91";
bias-pull-up;
};
};
arch/arm64/boot/dts/qcom/sc7280.dtsi
View file @ c7613530
......@@ -5,12 +5,14 @@
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,gpucc-sc7280.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sc7280.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
......@@ -26,8 +28,40 @@ / {
chosen { };
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
i2c8 = &i2c8;
i2c9 = &i2c9;
i2c10 = &i2c10;
i2c11 = &i2c11;
i2c12 = &i2c12;
i2c13 = &i2c13;
i2c14 = &i2c14;
i2c15 = &i2c15;
mmc1 = &sdhc_1;
mmc2 = &sdhc_2;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
spi3 = &spi3;
spi4 = &spi4;
spi5 = &spi5;
spi6 = &spi6;
spi7 = &spi7;
spi8 = &spi8;
spi9 = &spi9;
spi10 = &spi10;
spi11 = &spi11;
spi12 = &spi12;
spi13 = &spi13;
spi14 = &spi14;
spi15 = &spi15;
};
clocks {
......@@ -49,6 +83,16 @@ reserved-memory {
#size-cells = <2>;
ranges;
hyp_mem: memory@80000000 {
reg = <0x0 0x80000000 0x0 0x600000>;
no-map;
};
xbl_mem: memory@80600000 {
reg = <0x0 0x80600000 0x0 0x200000>;
no-map;
};
aop_mem: memory@80800000 {
reg = <0x0 0x80800000 0x0 0x60000>;
no-map;
......@@ -60,6 +104,16 @@ aop_cmd_db_mem: memory@80860000 {
no-map;
};
reserved_xbl_uefi_log: memory@80880000 {
reg = <0x0 0x80884000 0x0 0x10000>;
no-map;
};
sec_apps_mem: memory@808ff000 {
reg = <0x0 0x808ff000 0x0 0x1000>;
no-map;
};
smem_mem: memory@80900000 {
reg = <0x0 0x80900000 0x0 0x200000>;
no-map;
......@@ -70,10 +124,24 @@ cpucp_mem: memory@80b00000 {
reg = <0x0 0x80b00000 0x0 0x100000>;
};
wlan_fw_mem: memory@80c00000 {
reg = <0x0 0x80c00000 0x0 0xc00000>;
no-map;
};
ipa_fw_mem: memory@8b700000 {
reg = <0 0x8b700000 0 0x10000>;
no-map;
};
rmtfs_mem: memory@9c900000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0 0x9c900000 0x0 0x280000>;
no-map;
qcom,client-id = <1>;
qcom,vmid = <15>;
};
};
cpus {
......@@ -219,6 +287,42 @@ L2_700: l2-cache {
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
core4 {
cpu = <&CPU4>;
};
core5 {
cpu = <&CPU5>;
};
core6 {
cpu = <&CPU6>;
};
core7 {
cpu = <&CPU7>;
};
};
};
idle-states {
entry-method = "psci";
......@@ -415,6 +519,44 @@ psci {
method = "smc";
};
qspi_opp_table: qspi-opp-table {
compatible = "operating-points-v2";
opp-75000000 {
opp-hz = /bits/ 64 <75000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-150000000 {
opp-hz = /bits/ 64 <150000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
qup_opp_table: qup-opp-table {
compatible = "operating-points-v2";
opp-75000000 {
opp-hz = /bits/ 64 <75000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-128000000 {
opp-hz = /bits/ 64 <128000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
......@@ -517,312 +659,1188 @@ opp-384000000 {
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x009c0000 0 0x2000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
clock-names = "m-ahb", "s-ahb";
#address-cells = <2>;
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x123 0x0>;
status = "disabled";
uart5: serial@994000 {
compatible = "qcom,geni-debug-uart";
reg = <0 0x00994000 0 0x4000>;
i2c0: i2c@980000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00980000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&qup_i2c0_data_clk>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
};
cnoc2: interconnect@1500000 {
reg = <0 0x01500000 0 0x1000>;
compatible = "qcom,sc7280-cnoc2";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
spi0: spi@980000 {
compatible = "qcom,geni-spi";
reg = <0 0x00980000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
cnoc3: interconnect@1502000 {
reg = <0 0x01502000 0 0x1000>;
compatible = "qcom,sc7280-cnoc3";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
uart0: serial@980000 {
compatible = "qcom,geni-uart";
reg = <0 0x00980000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
mc_virt: interconnect@1580000 {
reg = <0 0x01580000 0 0x4>;
compatible = "qcom,sc7280-mc-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
i2c1: i2c@984000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00984000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c1_data_clk>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
system_noc: interconnect@1680000 {
reg = <0 0x01680000 0 0x15480>;
compatible = "qcom,sc7280-system-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
spi1: spi@984000 {
compatible = "qcom,geni-spi";
reg = <0 0x00984000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,sc7280-aggre1-noc";
reg = <0 0x016e0000 0 0x1c080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
uart1: serial@984000 {
compatible = "qcom,geni-uart";
reg = <0 0x00984000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
aggre2_noc: interconnect@1700000 {
reg = <0 0x01700000 0 0x2b080>;
compatible = "qcom,sc7280-aggre2-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
i2c2: i2c@988000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00988000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c2_data_clk>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
mmss_noc: interconnect@1740000 {
reg = <0 0x01740000 0 0x1e080>;
compatible = "qcom,sc7280-mmss-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
spi2: spi@988000 {
compatible = "qcom,geni-spi";
reg = <0 0x00988000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
ipa: ipa@1e40000 {
compatible = "qcom,sc7280-ipa";
iommus = <&apps_smmu 0x480 0x0>,
<&apps_smmu 0x482 0x0>;
reg = <0 0x1e40000 0 0x8000>,
<0 0x1e50000 0 0x4ad0>,
<0 0x1e04000 0 0x23000>;
reg-names = "ipa-reg",
"ipa-shared",
"gsi";
interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>,
<&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
<&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ipa",
"gsi",
"ipa-clock-query",
"ipa-setup-ready";
clocks = <&rpmhcc RPMH_IPA_CLK>;
clock-names = "core";
uart2: serial@988000 {
compatible = "qcom,geni-uart";
reg = <0 0x00988000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
interconnect-names = "memory",
"config";
i2c3: i2c@98c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0098c000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c3_data_clk>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
qcom,smem-states = <&ipa_smp2p_out 0>,
<&ipa_smp2p_out 1>;
qcom,smem-state-names = "ipa-clock-enabled-valid",
"ipa-clock-enabled";
spi3: spi@98c000 {
compatible = "qcom,geni-spi";
reg = <0 0x0098c000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
uart3: serial@98c000 {
compatible = "qcom,geni-uart";
reg = <0 0x0098c000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex", "syscon";
reg = <0 0x01f40000 0 0x40000>;
#hwlock-cells = <1>;
i2c4: i2c@990000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00990000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c4_data_clk>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
lpasscc: lpasscc@3000000 {
compatible = "qcom,sc7280-lpasscc";
reg = <0 0x03000000 0 0x40>,
<0 0x03c04000 0 0x4>,
<0 0x03389000 0 0x24>;
reg-names = "qdsp6ss", "top_cc", "cc";
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
#clock-cells = <1>;
spi4: spi@990000 {
compatible = "qcom,geni-spi";
reg = <0 0x00990000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
lpass_ag_noc: interconnect@3c40000 {
reg = <0 0x03c40000 0 0xf080>;
compatible = "qcom,sc7280-lpass-ag-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
uart4: serial@990000 {
compatible = "qcom,geni-uart";
reg = <0 0x00990000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
gpucc: clock-controller@3d90000 {
compatible = "qcom,sc7280-gpucc";
reg = <0 0x03d90000 0 0x9000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
clock-names = "bi_tcxo",
"gcc_gpu_gpll0_clk_src",
"gcc_gpu_gpll0_div_clk_src";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
i2c5: i2c@994000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00994000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c5_data_clk>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x06002000 0 0x1000>,
<0 0x16280000 0 0x180000>;
reg-names = "stm-base", "stm-stimulus-base";
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
stm_out: endpoint {
remote-endpoint = <&funnel0_in7>;
spi5: spi@994000 {
compatible = "qcom,geni-spi";
reg = <0 0x00994000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
uart5: serial@994000 {
compatible = "qcom,geni-uart";
reg = <0 0x00994000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
i2c6: i2c@998000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00998000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c6_data_clk>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
spi6: spi@998000 {
compatible = "qcom,geni-spi";
reg = <0 0x00998000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
funnel@6041000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x06041000 0 0x1000>;
uart6: serial@998000 {
compatible = "qcom,geni-uart";
reg = <0 0x00998000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
i2c7: i2c@99c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0099c000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c7_data_clk>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
out-ports {
port {
funnel0_out: endpoint {
remote-endpoint = <&merge_funnel_in0>;
spi7: spi@99c000 {
compatible = "qcom,geni-spi";
reg = <0 0x0099c000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
uart7: serial@99c000 {
compatible = "qcom,geni-uart";
reg = <0 0x0099c000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
};
in-ports {
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x00ac0000 0 0x2000>;
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
clock-names = "m-ahb", "s-ahb";
#address-cells = <2>;
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x43 0x0>;
status = "disabled";
i2c8: i2c@a80000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a80000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c8_data_clk>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
port@7 {
reg = <7>;
funnel0_in7: endpoint {
remote-endpoint = <&stm_out>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
spi8: spi@a80000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a80000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
uart8: serial@a80000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a80000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
i2c9: i2c@a84000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a84000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c9_data_clk>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
funnel@6042000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x06042000 0 0x1000>;
spi9: spi@a84000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a84000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
uart9: serial@a84000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a84000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
out-ports {
port {
funnel1_out: endpoint {
remote-endpoint = <&merge_funnel_in1>;
i2c10: i2c@a88000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a88000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c10_data_clk>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
spi10: spi@a88000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a88000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
uart10: serial@a88000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a88000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
in-ports {
i2c11: i2c@a8c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a8c000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c11_data_clk>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
port@4 {
reg = <4>;
funnel1_in4: endpoint {
remote-endpoint = <&apss_merge_funnel_out>;
spi11: spi@a8c000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a8c000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
uart11: serial@a8c000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a8c000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
i2c12: i2c@a90000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a90000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c12_data_clk>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
spi12: spi@a90000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a90000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
funnel@6045000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x06045000 0 0x1000>;
uart12: serial@a90000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a90000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
i2c13: i2c@a94000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a94000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c13_data_clk>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
out-ports {
port {
merge_funnel_out: endpoint {
remote-endpoint = <&swao_funnel_in>;
spi13: spi@a94000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a94000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
uart13: serial@a94000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a94000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
i2c14: i2c@a98000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a98000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c14_data_clk>;
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
in-ports {
spi14: spi@a98000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a98000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
port@0 {
reg = <0>;
merge_funnel_in0: endpoint {
remote-endpoint = <&funnel0_out>;
uart14: serial@a98000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a98000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
i2c15: i2c@a9c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a9c000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c15_data_clk>;
interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
port@1 {
reg = <1>;
merge_funnel_in1: endpoint {
remote-endpoint = <&funnel1_out>;
spi15: spi@a9c000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a9c000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
uart15: serial@a9c000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a9c000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
};
cnoc2: interconnect@1500000 {
reg = <0 0x01500000 0 0x1000>;
compatible = "qcom,sc7280-cnoc2";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
replicator@6046000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0 0x06046000 0 0x1000>;
cnoc3: interconnect@1502000 {
reg = <0 0x01502000 0 0x1000>;
compatible = "qcom,sc7280-cnoc3";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
mc_virt: interconnect@1580000 {
reg = <0 0x01580000 0 0x4>;
compatible = "qcom,sc7280-mc-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
out-ports {
port {
replicator_out: endpoint {
remote-endpoint = <&etr_in>;
system_noc: interconnect@1680000 {
reg = <0 0x01680000 0 0x15480>;
compatible = "qcom,sc7280-system-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,sc7280-aggre1-noc";
reg = <0 0x016e0000 0 0x1c080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre2_noc: interconnect@1700000 {
reg = <0 0x01700000 0 0x2b080>;
compatible = "qcom,sc7280-aggre2-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mmss_noc: interconnect@1740000 {
reg = <0 0x01740000 0 0x1e080>;
compatible = "qcom,sc7280-mmss-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
in-ports {
port {
replicator_in: endpoint {
remote-endpoint = <&swao_replicator_out>;
ipa: ipa@1e40000 {
compatible = "qcom,sc7280-ipa";
iommus = <&apps_smmu 0x480 0x0>,
<&apps_smmu 0x482 0x0>;
reg = <0 0x1e40000 0 0x8000>,
<0 0x1e50000 0 0x4ad0>,
<0 0x1e04000 0 0x23000>;
reg-names = "ipa-reg",
"ipa-shared",
"gsi";
interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
<&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
<&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ipa",
"gsi",
"ipa-clock-query",
"ipa-setup-ready";
clocks = <&rpmhcc RPMH_IPA_CLK>;
clock-names = "core";
interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
interconnect-names = "memory",
"config";
qcom,smem-states = <&ipa_smp2p_out 0>,
<&ipa_smp2p_out 1>;
qcom,smem-state-names = "ipa-clock-enabled-valid",
"ipa-clock-enabled";
status = "disabled";
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex", "syscon";
reg = <0 0x01f40000 0 0x40000>;
#hwlock-cells = <1>;
};
tcsr: syscon@1fc0000 {
compatible = "qcom,sc7280-tcsr", "syscon";
reg = <0 0x01fc0000 0 0x30000>;
};
lpasscc: lpasscc@3000000 {
compatible = "qcom,sc7280-lpasscc";
reg = <0 0x03000000 0 0x40>,
<0 0x03c04000 0 0x4>,
<0 0x03389000 0 0x24>;
reg-names = "qdsp6ss", "top_cc", "cc";
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
#clock-cells = <1>;
};
lpass_ag_noc: interconnect@3c40000 {
reg = <0 0x03c40000 0 0xf080>;
compatible = "qcom,sc7280-lpass-ag-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
gpu: gpu@3d00000 {
compatible = "qcom,adreno-635.0", "qcom,adreno";
#stream-id-cells = <16>;
reg = <0 0x03d00000 0 0x40000>,
<0 0x03d9e000 0 0x1000>,
<0 0x03d61000 0 0x800>;
reg-names = "kgsl_3d0_reg_memory",
"cx_mem",
"cx_dbgc";
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&adreno_smmu 0 0x401>;
operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "gfx-mem";
#cooling-cells = <2>;
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-315000000 {
opp-hz = /bits/ 64 <315000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-peak-kBps = <1804000>;
};
opp-450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <4068000>;
};
opp-550000000 {
opp-hz = /bits/ 64 <550000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <6832000>;
};
};
};
gmu: gmu@3d69000 {
compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
reg = <0 0x03d6a000 0 0x34000>,
<0 0x3de0000 0 0x10000>,
<0 0x0b290000 0 0x10000>;
reg-names = "gmu", "rscc", "gmu_pdc";
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hfi", "gmu";
clocks = <&gpucc 5>,
<&gpucc 8>,
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gpucc 2>,
<&gpucc 15>,
<&gpucc 11>;
clock-names = "gmu",
"cxo",
"axi",
"memnoc",
"ahb",
"hub",
"smmu_vote";
power-domains = <&gpucc 0>,
<&gpucc 1>;
power-domain-names = "cx",
"gx";
iommus = <&adreno_smmu 5 0x400>;
operating-points-v2 = <&gmu_opp_table>;
gmu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
};
};
};
etr@6048000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x06048000 0 0x1000>;
iommus = <&apps_smmu 0x04c0 0>;
gpucc: clock-controller@3d90000 {
compatible = "qcom,sc7280-gpucc";
reg = <0 0x03d90000 0 0x9000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
clock-names = "bi_tcxo",
"gcc_gpu_gpll0_clk_src",
"gcc_gpu_gpll0_div_clk_src";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
adreno_smmu: iommu@3da0000 {
compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
reg = <0 0x03da0000 0 0x20000>;
#iommu-cells = <2>;
#global-interrupts = <2>;
interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
<&gpucc 2>,
<&gpucc 11>,
<&gpucc 5>,
<&gpucc 15>,
<&gpucc 13>;
clock-names = "gcc_gpu_memnoc_gfx_clk",
"gcc_gpu_snoc_dvm_gfx_clk",
"gpu_cc_ahb_clk",
"gpu_cc_hlos1_vote_gpu_smmu_clk",
"gpu_cc_cx_gmu_clk",
"gpu_cc_hub_cx_int_clk",
"gpu_cc_hub_aon_clk";
power-domains = <&gpucc 0>;
};
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sc7280-mpss-pas";
reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
reg-names = "qdsp6", "rmb";
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
<&gcc GCC_MSS_OFFLINE_AXI_CLK>,
<&gcc GCC_MSS_SNOC_AXI_CLK>,
<&rpmhcc RPMH_PKA_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "offline", "snoc_axi", "pka", "xo";
power-domains = <&rpmhpd SC7280_CX>,
<&rpmhpd SC7280_MSS>;
power-domain-names = "cx", "mss";
memory-region = <&mpss_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
<&pdc_reset PDC_MODEM_SYNC_RESET>;
reset-names = "mss_restart", "pdc_reset";
qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>;
qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>;
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "modem";
qcom,remote-pid = <1>;
};
};
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x06002000 0 0x1000>,
<0 0x16280000 0 0x180000>;
reg-names = "stm-base", "stm-stimulus-base";
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,scatter-gather;
in-ports {
out-ports {
port {
etr_in: endpoint {
remote-endpoint = <&replicator_out>;
stm_out: endpoint {
remote-endpoint = <&funnel0_in7>;
};
};
};
};
funnel@6b04000 {
funnel@6041000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x06b04000 0 0x1000>;
reg = <0 0x06041000 0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
swao_funnel_out: endpoint {
remote-endpoint = <&etf_in>;
funnel0_out: endpoint {
remote-endpoint = <&merge_funnel_in0>;
};
};
};
......@@ -833,85 +1851,218 @@ in-ports {
port@7 {
reg = <7>;
swao_funnel_in: endpoint {
remote-endpoint = <&merge_funnel_out>;
funnel0_in7: endpoint {
remote-endpoint = <&stm_out>;
};
};
};
};
etf@6b05000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x06b05000 0 0x1000>;
funnel@6042000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x06042000 0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
etf_out: endpoint {
remote-endpoint = <&swao_replicator_in>;
funnel1_out: endpoint {
remote-endpoint = <&merge_funnel_in1>;
};
};
};
in-ports {
port {
etf_in: endpoint {
remote-endpoint = <&swao_funnel_out>;
#address-cells = <1>;
#size-cells = <0>;
port@4 {
reg = <4>;
funnel1_in4: endpoint {
remote-endpoint = <&apss_merge_funnel_out>;
};
};
};
};
replicator@6b06000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0 0x06b06000 0 0x1000>;
funnel@6045000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x06045000 0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,replicator-loses-context;
out-ports {
port {
swao_replicator_out: endpoint {
remote-endpoint = <&replicator_in>;
merge_funnel_out: endpoint {
remote-endpoint = <&swao_funnel_in>;
};
};
};
in-ports {
port {
swao_replicator_in: endpoint {
remote-endpoint = <&etf_out>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
merge_funnel_in0: endpoint {
remote-endpoint = <&funnel0_out>;
};
};
port@1 {
reg = <1>;
merge_funnel_in1: endpoint {
remote-endpoint = <&funnel1_out>;
};
};
};
};
etm@7040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07040000 0 0x1000>;
cpu = <&CPU0>;
replicator@6046000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0 0x06046000 0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
qcom,skip-power-up;
out-ports {
port {
etm0_out: endpoint {
remote-endpoint = <&apss_funnel_in0>;
};
replicator_out: endpoint {
remote-endpoint = <&etr_in>;
};
};
};
etm@7140000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07140000 0 0x1000>;
in-ports {
port {
replicator_in: endpoint {
remote-endpoint = <&swao_replicator_out>;
};
};
};
};
etr@6048000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x06048000 0 0x1000>;
iommus = <&apps_smmu 0x04c0 0>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,scatter-gather;
in-ports {
port {
etr_in: endpoint {
remote-endpoint = <&replicator_out>;
};
};
};
};
funnel@6b04000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x06b04000 0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
swao_funnel_out: endpoint {
remote-endpoint = <&etf_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@7 {
reg = <7>;
swao_funnel_in: endpoint {
remote-endpoint = <&merge_funnel_out>;
};
};
};
};
etf@6b05000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x06b05000 0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
etf_out: endpoint {
remote-endpoint = <&swao_replicator_in>;
};
};
};
in-ports {
port {
etf_in: endpoint {
remote-endpoint = <&swao_funnel_out>;
};
};
};
};
replicator@6b06000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0 0x06b06000 0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,replicator-loses-context;
out-ports {
port {
swao_replicator_out: endpoint {
remote-endpoint = <&replicator_in>;
};
};
};
in-ports {
port {
swao_replicator_in: endpoint {
remote-endpoint = <&etf_out>;
};
};
};
};
etm@7040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07040000 0 0x1000>;
cpu = <&CPU0>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
qcom,skip-power-up;
out-ports {
port {
etm0_out: endpoint {
remote-endpoint = <&apss_funnel_in0>;
};
};
};
};
etm@7140000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07140000 0 0x1000>;
cpu = <&CPU1>;
......@@ -1033,489 +2184,1001 @@ etm@7740000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07740000 0 0x1000>;
cpu = <&CPU7>;
cpu = <&CPU7>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
qcom,skip-power-up;
out-ports {
port {
etm7_out: endpoint {
remote-endpoint = <&apss_funnel_in7>;
};
};
};
};
funnel@7800000 { /* APSS Funnel */
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x07800000 0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
apss_funnel_out: endpoint {
remote-endpoint = <&apss_merge_funnel_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
apss_funnel_in0: endpoint {
remote-endpoint = <&etm0_out>;
};
};
port@1 {
reg = <1>;
apss_funnel_in1: endpoint {
remote-endpoint = <&etm1_out>;
};
};
port@2 {
reg = <2>;
apss_funnel_in2: endpoint {
remote-endpoint = <&etm2_out>;
};
};
port@3 {
reg = <3>;
apss_funnel_in3: endpoint {
remote-endpoint = <&etm3_out>;
};
};
port@4 {
reg = <4>;
apss_funnel_in4: endpoint {
remote-endpoint = <&etm4_out>;
};
};
port@5 {
reg = <5>;
apss_funnel_in5: endpoint {
remote-endpoint = <&etm5_out>;
};
};
port@6 {
reg = <6>;
apss_funnel_in6: endpoint {
remote-endpoint = <&etm6_out>;
};
};
port@7 {
reg = <7>;
apss_funnel_in7: endpoint {
remote-endpoint = <&etm7_out>;
};
};
};
};
funnel@7810000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x07810000 0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
apss_merge_funnel_out: endpoint {
remote-endpoint = <&funnel1_in4>;
};
};
};
in-ports {
port {
apss_merge_funnel_in: endpoint {
remote-endpoint = <&apss_funnel_out>;
};
};
};
};
sdhc_2: sdhci@8804000 {
compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
status = "disabled";
reg = <0 0x08804000 0 0x1000>;
iommus = <&apps_smmu 0x100 0x0>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
<&gcc GCC_SDCC2_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "core", "iface", "xo";
interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&sdhc2_opp_table>;
bus-width = <4>;
qcom,dll-config = <0x0007642c>;
sdhc2_opp_table: opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1800000 400000>;
opp-avg-kBps = <100000 0>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <5400000 1600000>;
opp-avg-kBps = <200000 0>;
};
};
};
usb_1_hsphy: phy@88e3000 {
compatible = "qcom,sc7280-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
reg = <0 0x088e3000 0 0x400>;
status = "disabled";
#phy-cells = <0>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
};
usb_2_hsphy: phy@88e4000 {
compatible = "qcom,sc7280-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
reg = <0 0x088e4000 0 0x400>;
status = "disabled";
#phy-cells = <0>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
};
usb_1_qmpphy: phy-wrapper@88e9000 {
compatible = "qcom,sc7280-qmp-usb3-dp-phy",
"qcom,sm8250-qmp-usb3-dp-phy";
reg = <0 0x088e9000 0 0x200>,
<0 0x088e8000 0 0x40>,
<0 0x088ea000 0 0x200>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux", "ref_clk_src", "com_aux";
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "phy", "common";
usb_1_ssphy: usb3-phy@88e9200 {
reg = <0 0x088e9200 0 0x200>,
<0 0x088e9400 0 0x200>,
<0 0x088e9c00 0 0x400>,
<0 0x088e9600 0 0x200>,
<0 0x088e9800 0 0x200>,
<0 0x088e9a00 0 0x100>;
#clock-cells = <0>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
dp_phy: dp-phy@88ea200 {
reg = <0 0x088ea200 0 0x200>,
<0 0x088ea400 0 0x200>,
<0 0x088eaa00 0 0x200>,
<0 0x088ea600 0 0x200>,
<0 0x088ea800 0 0x200>;
#phy-cells = <0>;
#clock-cells = <1>;
};
};
usb_2: usb@8cf8800 {
compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
reg = <0 0x08cf8800 0 0x400>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-ranges;
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SEC_SLEEP_CLK>;
clock-names = "cfg_noc", "core", "iface","mock_utmi",
"sleep";
assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 13 IRQ_TYPE_EDGE_RISING>,
<&pdc 12 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "hs_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
power-domains = <&gcc GCC_USB30_SEC_GDSC>;
resets = <&gcc GCC_USB30_SEC_BCR>;
interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
interconnect-names = "usb-ddr", "apps-usb";
usb_2_dwc3: usb@8c00000 {
compatible = "snps,dwc3";
reg = <0 0x08c00000 0 0xe000>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0xa0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
phys = <&usb_2_hsphy>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
};
};
qspi: spi@88dc000 {
compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
reg = <0 0x088dc000 0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<&gcc GCC_QSPI_CORE_CLK>;
clock-names = "iface", "core";
interconnects = <&gem_noc MASTER_APPSS_PROC 0
&cnoc2 SLAVE_QSPI_0 0>;
interconnect-names = "qspi-config";
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qspi_opp_table>;
status = "disabled";
};
dc_noc: interconnect@90e0000 {
reg = <0 0x090e0000 0 0x5080>;
compatible = "qcom,sc7280-dc-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
gem_noc: interconnect@9100000 {
reg = <0 0x9100000 0 0xe2200>;
compatible = "qcom,sc7280-gem-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system-cache-controller@9200000 {
compatible = "qcom,sc7280-llcc";
reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
nsp_noc: interconnect@a0c0000 {
reg = <0 0x0a0c0000 0 0x10000>;
compatible = "qcom,sc7280-nsp-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
usb_1: usb@a6f8800 {
compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-ranges;
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
clock-names = "cfg_noc", "core", "iface", "mock_utmi",
"sleep";
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
"dm_hs_phy_irq", "ss_phy_irq";
power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
resets = <&gcc GCC_USB30_PRIM_BCR>;
interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
interconnect-names = "usb-ddr", "apps-usb";
usb_1_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xe000>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0xe0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
maximum-speed = "super-speed";
};
};
videocc: clock-controller@aaf0000 {
compatible = "qcom,sc7280-videocc";
reg = <0 0xaaf0000 0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>;
clock-names = "bi_tcxo", "bi_tcxo_ao";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
dispcc: clock-controller@af00000 {
compatible = "qcom,sc7280-dispcc";
reg = <0 0xaf00000 0 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<0>, <0>, <0>, <0>, <0>, <0>;
clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
"dp_phy_pll_link_clk",
"dp_phy_pll_vco_div_clk",
"edp_phy_pll_link_clk",
"edp_phy_pll_vco_div_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7280-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>;
qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
<55 306 4>, <59 312 3>, <62 374 2>,
<64 434 2>, <66 438 3>, <69 86 1>,
<70 520 54>, <124 609 31>, <155 63 1>,
<156 716 12>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
pdc_reset: reset-controller@b5e0000 {
compatible = "qcom,sc7280-pdc-global";
reg = <0 0x0b5e0000 0 0x20000>;
#reset-cells = <1>;
};
tsens0: thermal-sensor@c263000 {
compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
reg = <0 0x0c263000 0 0x1ff>, /* TM */
<0 0x0c222000 0 0x1ff>; /* SROT */
#qcom,sensors = <15>;
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow","critical";
#thermal-sensor-cells = <1>;
};
tsens1: thermal-sensor@c265000 {
compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
reg = <0 0x0c265000 0 0x1ff>, /* TM */
<0 0x0c223000 0 0x1ff>; /* SROT */
#qcom,sensors = <12>;
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow","critical";
#thermal-sensor-cells = <1>;
};
aoss_reset: reset-controller@c2a0000 {
compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
reg = <0 0x0c2a0000 0 0x31000>;
#reset-cells = <1>;
};
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sc7280-aoss-qmp";
reg = <0 0x0c300000 0 0x100000>;
interrupts-extended = <&ipcc IPCC_CLIENT_AOP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_AOP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
};
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0 0x0c440000 0 0x1100>,
<0 0x0c600000 0 0x2000000>,
<0 0x0e600000 0 0x100000>,
<0 0x0e700000 0 0xa0000>,
<0 0x0c40a000 0 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <4>;
};
tlmm: pinctrl@f100000 {
compatible = "qcom,sc7280-pinctrl";
reg = <0 0x0f100000 0 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
qspi_clk: qspi-clk {
pins = "gpio14";
function = "qspi_clk";
};
qspi_cs0: qspi-cs0 {
pins = "gpio15";
function = "qspi_cs";
};
qspi_cs1: qspi-cs1 {
pins = "gpio19";
function = "qspi_cs";
};
qspi_data01: qspi-data01 {
pins = "gpio12", "gpio13";
function = "qspi_data";
};
qspi_data12: qspi-data12 {
pins = "gpio16", "gpio17";
function = "qspi_data";
};
qup_i2c0_data_clk: qup-i2c0-data-clk {
pins = "gpio0", "gpio1";
function = "qup00";
};
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
qcom,skip-power-up;
qup_i2c1_data_clk: qup-i2c1-data-clk {
pins = "gpio4", "gpio5";
function = "qup01";
};
out-ports {
port {
etm7_out: endpoint {
remote-endpoint = <&apss_funnel_in7>;
qup_i2c2_data_clk: qup-i2c2-data-clk {
pins = "gpio8", "gpio9";
function = "qup02";
};
qup_i2c3_data_clk: qup-i2c3-data-clk {
pins = "gpio12", "gpio13";
function = "qup03";
};
qup_i2c4_data_clk: qup-i2c4-data-clk {
pins = "gpio16", "gpio17";
function = "qup04";
};
qup_i2c5_data_clk: qup-i2c5-data-clk {
pins = "gpio20", "gpio21";
function = "qup05";
};
funnel@7800000 { /* APSS Funnel */
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x07800000 0 0x1000>;
qup_i2c6_data_clk: qup-i2c6-data-clk {
pins = "gpio24", "gpio25";
function = "qup06";
};
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qup_i2c7_data_clk: qup-i2c7-data-clk {
pins = "gpio28", "gpio29";
function = "qup07";
};
out-ports {
port {
apss_funnel_out: endpoint {
remote-endpoint = <&apss_merge_funnel_in>;
qup_i2c8_data_clk: qup-i2c8-data-clk {
pins = "gpio32", "gpio33";
function = "qup10";
};
qup_i2c9_data_clk: qup-i2c9-data-clk {
pins = "gpio36", "gpio37";
function = "qup11";
};
qup_i2c10_data_clk: qup-i2c10-data-clk {
pins = "gpio40", "gpio41";
function = "qup12";
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
qup_i2c11_data_clk: qup-i2c11-data-clk {
pins = "gpio44", "gpio45";
function = "qup13";
};
port@0 {
reg = <0>;
apss_funnel_in0: endpoint {
remote-endpoint = <&etm0_out>;
qup_i2c12_data_clk: qup-i2c12-data-clk {
pins = "gpio48", "gpio49";
function = "qup14";
};
qup_i2c13_data_clk: qup-i2c13-data-clk {
pins = "gpio52", "gpio53";
function = "qup15";
};
port@1 {
reg = <1>;
apss_funnel_in1: endpoint {
remote-endpoint = <&etm1_out>;
qup_i2c14_data_clk: qup-i2c14-data-clk {
pins = "gpio56", "gpio57";
function = "qup16";
};
qup_i2c15_data_clk: qup-i2c15-data-clk {
pins = "gpio60", "gpio61";
function = "qup17";
};
port@2 {
reg = <2>;
apss_funnel_in2: endpoint {
remote-endpoint = <&etm2_out>;
qup_spi0_data_clk: qup-spi0-data-clk {
pins = "gpio0", "gpio1", "gpio2";
function = "qup00";
};
qup_spi0_cs: qup-spi0-cs {
pins = "gpio3";
function = "qup00";
};
port@3 {
reg = <3>;
apss_funnel_in3: endpoint {
remote-endpoint = <&etm3_out>;
qup_spi0_cs_gpio: qup-spi0-cs-gpio {
pins = "gpio3";
function = "gpio";
};
qup_spi1_data_clk: qup-spi1-data-clk {
pins = "gpio4", "gpio5", "gpio6";
function = "qup01";
};
port@4 {
reg = <4>;
apss_funnel_in4: endpoint {
remote-endpoint = <&etm4_out>;
qup_spi1_cs: qup-spi1-cs {
pins = "gpio7";
function = "qup01";
};
qup_spi1_cs_gpio: qup-spi1-cs-gpio {
pins = "gpio7";
function = "gpio";
};
port@5 {
reg = <5>;
apss_funnel_in5: endpoint {
remote-endpoint = <&etm5_out>;
qup_spi2_data_clk: qup-spi2-data-clk {
pins = "gpio8", "gpio9", "gpio10";
function = "qup02";
};
qup_spi2_cs: qup-spi2-cs {
pins = "gpio11";
function = "qup02";
};
port@6 {
reg = <6>;
apss_funnel_in6: endpoint {
remote-endpoint = <&etm6_out>;
qup_spi2_cs_gpio: qup-spi2-cs-gpio {
pins = "gpio11";
function = "gpio";
};
qup_spi3_data_clk: qup-spi3-data-clk {
pins = "gpio12", "gpio13", "gpio14";
function = "qup03";
};
port@7 {
reg = <7>;
apss_funnel_in7: endpoint {
remote-endpoint = <&etm7_out>;
qup_spi3_cs: qup-spi3-cs {
pins = "gpio15";
function = "qup03";
};
qup_spi3_cs_gpio: qup-spi3-cs-gpio {
pins = "gpio15";
function = "gpio";
};
qup_spi4_data_clk: qup-spi4-data-clk {
pins = "gpio16", "gpio17", "gpio18";
function = "qup04";
};
qup_spi4_cs: qup-spi4-cs {
pins = "gpio19";
function = "qup04";
};
funnel@7810000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x07810000 0 0x1000>;
qup_spi4_cs_gpio: qup-spi4-cs-gpio {
pins = "gpio19";
function = "gpio";
};
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qup_spi5_data_clk: qup-spi5-data-clk {
pins = "gpio20", "gpio21", "gpio22";
function = "qup05";
};
out-ports {
port {
apss_merge_funnel_out: endpoint {
remote-endpoint = <&funnel1_in4>;
qup_spi5_cs: qup-spi5-cs {
pins = "gpio23";
function = "qup05";
};
qup_spi5_cs_gpio: qup-spi5-cs-gpio {
pins = "gpio23";
function = "gpio";
};
qup_spi6_data_clk: qup-spi6-data-clk {
pins = "gpio24", "gpio25", "gpio26";
function = "qup06";
};
in-ports {
port {
apss_merge_funnel_in: endpoint {
remote-endpoint = <&apss_funnel_out>;
qup_spi6_cs: qup-spi6-cs {
pins = "gpio27";
function = "qup06";
};
qup_spi6_cs_gpio: qup-spi6-cs-gpio {
pins = "gpio27";
function = "gpio";
};
qup_spi7_data_clk: qup-spi7-data-clk {
pins = "gpio28", "gpio29", "gpio30";
function = "qup07";
};
qup_spi7_cs: qup-spi7-cs {
pins = "gpio31";
function = "qup07";
};
sdhc_2: sdhci@8804000 {
compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
status = "disabled";
qup_spi7_cs_gpio: qup-spi7-cs-gpio {
pins = "gpio31";
function = "gpio";
};
reg = <0 0x08804000 0 0x1000>;
qup_spi8_data_clk: qup-spi8-data-clk {
pins = "gpio32", "gpio33", "gpio34";
function = "qup10";
};
iommus = <&apps_smmu 0x100 0x0>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
qup_spi8_cs: qup-spi8-cs {
pins = "gpio35";
function = "qup10";
};
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
<&gcc GCC_SDCC2_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "core", "iface", "xo";
interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&sdhc2_opp_table>;
qup_spi8_cs_gpio: qup-spi8-cs-gpio {
pins = "gpio35";
function = "gpio";
};
bus-width = <4>;
qup_spi9_data_clk: qup-spi9-data-clk {
pins = "gpio36", "gpio37", "gpio38";
function = "qup11";
};
qcom,dll-config = <0x0007642c>;
qup_spi9_cs: qup-spi9-cs {
pins = "gpio39";
function = "qup11";
};
sdhc2_opp_table: opp-table {
compatible = "operating-points-v2";
qup_spi9_cs_gpio: qup-spi9-cs-gpio {
pins = "gpio39";
function = "gpio";
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1800000 400000>;
opp-avg-kBps = <100000 0>;
qup_spi10_data_clk: qup-spi10-data-clk {
pins = "gpio40", "gpio41", "gpio42";
function = "qup12";
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <5400000 1600000>;
opp-avg-kBps = <200000 0>;
qup_spi10_cs: qup-spi10-cs {
pins = "gpio43";
function = "qup12";
};
qup_spi10_cs_gpio: qup-spi10-cs-gpio {
pins = "gpio43";
function = "gpio";
};
qup_spi11_data_clk: qup-spi11-data-clk {
pins = "gpio44", "gpio45", "gpio46";
function = "qup13";
};
usb_1_hsphy: phy@88e3000 {
compatible = "qcom,sc7280-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
reg = <0 0x088e3000 0 0x400>;
status = "disabled";
#phy-cells = <0>;
qup_spi11_cs: qup-spi11-cs {
pins = "gpio47";
function = "qup13";
};
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "ref";
qup_spi11_cs_gpio: qup-spi11-cs-gpio {
pins = "gpio47";
function = "gpio";
};
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
qup_spi12_data_clk: qup-spi12-data-clk {
pins = "gpio48", "gpio49", "gpio50";
function = "qup14";
};
usb_2_hsphy: phy@88e4000 {
compatible = "qcom,sc7280-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
reg = <0 0x088e4000 0 0x400>;
status = "disabled";
#phy-cells = <0>;
qup_spi12_cs: qup-spi12-cs {
pins = "gpio51";
function = "qup14";
};
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "ref";
qup_spi12_cs_gpio: qup-spi12-cs-gpio {
pins = "gpio51";
function = "gpio";
};
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
qup_spi13_data_clk: qup-spi13-data-clk {
pins = "gpio52", "gpio53", "gpio54";
function = "qup15";
};
usb_1_qmpphy: phy-wrapper@88e9000 {
compatible = "qcom,sc7280-qmp-usb3-dp-phy",
"qcom,sm8250-qmp-usb3-dp-phy";
reg = <0 0x088e9000 0 0x200>,
<0 0x088e8000 0 0x40>,
<0 0x088ea000 0 0x200>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
qup_spi13_cs: qup-spi13-cs {
pins = "gpio55";
function = "qup15";
};
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux", "ref_clk_src", "com_aux";
qup_spi13_cs_gpio: qup-spi13-cs-gpio {
pins = "gpio55";
function = "gpio";
};
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "phy", "common";
qup_spi14_data_clk: qup-spi14-data-clk {
pins = "gpio56", "gpio57", "gpio58";
function = "qup16";
};
usb_1_ssphy: usb3-phy@88e9200 {
reg = <0 0x088e9200 0 0x200>,
<0 0x088e9400 0 0x200>,
<0 0x088e9c00 0 0x400>,
<0 0x088e9600 0 0x200>,
<0 0x088e9800 0 0x200>,
<0 0x088e9a00 0 0x100>;
#clock-cells = <0>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
qup_spi14_cs: qup-spi14-cs {
pins = "gpio59";
function = "qup16";
};
dp_phy: dp-phy@88ea200 {
reg = <0 0x088ea200 0 0x200>,
<0 0x088ea400 0 0x200>,
<0 0x088eac00 0 0x400>,
<0 0x088ea600 0 0x200>,
<0 0x088ea800 0 0x200>,
<0 0x088eaa00 0 0x100>;
#phy-cells = <0>;
#clock-cells = <1>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
qup_spi14_cs_gpio: qup-spi14-cs-gpio {
pins = "gpio59";
function = "gpio";
};
qup_spi15_data_clk: qup-spi15-data-clk {
pins = "gpio60", "gpio61", "gpio62";
function = "qup17";
};
usb_2: usb@8cf8800 {
compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
reg = <0 0x08cf8800 0 0x400>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-ranges;
qup_spi15_cs: qup-spi15-cs {
pins = "gpio63";
function = "qup17";
};
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SEC_SLEEP_CLK>;
clock-names = "cfg_noc", "core", "iface","mock_utmi",
"sleep";
qup_spi15_cs_gpio: qup-spi15-cs-gpio {
pins = "gpio63";
function = "gpio";
};
assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
qup_uart0_cts: qup-uart0-cts {
pins = "gpio0";
function = "qup00";
};
interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 13 IRQ_TYPE_EDGE_RISING>,
<&pdc 12 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "hs_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
qup_uart0_rts: qup-uart0-rts {
pins = "gpio1";
function = "qup00";
};
power-domains = <&gcc GCC_USB30_SEC_GDSC>;
qup_uart0_tx: qup-uart0-tx {
pins = "gpio2";
function = "qup00";
};
resets = <&gcc GCC_USB30_SEC_BCR>;
qup_uart0_rx: qup-uart0-rx {
pins = "gpio3";
function = "qup00";
};
interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
interconnect-names = "usb-ddr", "apps-usb";
qup_uart1_cts: qup-uart1-cts {
pins = "gpio4";
function = "qup01";
};
usb_2_dwc3: usb@8c00000 {
compatible = "snps,dwc3";
reg = <0 0x08c00000 0 0xe000>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0xa0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
phys = <&usb_2_hsphy>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
qup_uart1_rts: qup-uart1-rts {
pins = "gpio5";
function = "qup01";
};
qup_uart1_tx: qup-uart1-tx {
pins = "gpio6";
function = "qup01";
};
dc_noc: interconnect@90e0000 {
reg = <0 0x090e0000 0 0x5080>;
compatible = "qcom,sc7280-dc-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
qup_uart1_rx: qup-uart1-rx {
pins = "gpio7";
function = "qup01";
};
gem_noc: interconnect@9100000 {
reg = <0 0x9100000 0 0xe2200>;
compatible = "qcom,sc7280-gem-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
qup_uart2_cts: qup-uart2-cts {
pins = "gpio8";
function = "qup02";
};
system-cache-controller@9200000 {
compatible = "qcom,sc7280-llcc";
reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
qup_uart2_rts: qup-uart2-rts {
pins = "gpio9";
function = "qup02";
};
nsp_noc: interconnect@a0c0000 {
reg = <0 0x0a0c0000 0 0x10000>;
compatible = "qcom,sc7280-nsp-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
qup_uart2_tx: qup-uart2-tx {
pins = "gpio10";
function = "qup02";
};
usb_1: usb@a6f8800 {
compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-ranges;
qup_uart2_rx: qup-uart2-rx {
pins = "gpio11";
function = "qup02";
};
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
clock-names = "cfg_noc", "core", "iface", "mock_utmi",
"sleep";
qup_uart3_cts: qup-uart3-cts {
pins = "gpio12";
function = "qup03";
};
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
qup_uart3_rts: qup-uart3-rts {
pins = "gpio13";
function = "qup03";
};
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
"dm_hs_phy_irq", "ss_phy_irq";
qup_uart3_tx: qup-uart3-tx {
pins = "gpio14";
function = "qup03";
};
power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
qup_uart3_rx: qup-uart3-rx {
pins = "gpio15";
function = "qup03";
};
resets = <&gcc GCC_USB30_PRIM_BCR>;
qup_uart4_cts: qup-uart4-cts {
pins = "gpio16";
function = "qup04";
};
interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
interconnect-names = "usb-ddr", "apps-usb";
qup_uart4_rts: qup-uart4-rts {
pins = "gpio17";
function = "qup04";
};
usb_1_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xe000>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0xe0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
maximum-speed = "super-speed";
qup_uart4_tx: qup-uart4-tx {
pins = "gpio18";
function = "qup04";
};
qup_uart4_rx: qup-uart4-rx {
pins = "gpio19";
function = "qup04";
};
videocc: clock-controller@aaf0000 {
compatible = "qcom,sc7280-videocc";
reg = <0 0xaaf0000 0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>;
clock-names = "bi_tcxo", "bi_tcxo_ao";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
qup_uart5_cts: qup-uart5-cts {
pins = "gpio20";
function = "qup05";
};
dispcc: clock-controller@af00000 {
compatible = "qcom,sc7280-dispcc";
reg = <0 0xaf00000 0 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<0>, <0>, <0>, <0>, <0>, <0>;
clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
"dp_phy_pll_link_clk",
"dp_phy_pll_vco_div_clk",
"edp_phy_pll_link_clk",
"edp_phy_pll_vco_div_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
qup_uart5_rts: qup-uart5-rts {
pins = "gpio21";
function = "qup05";
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7280-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>;
qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
<55 306 4>, <59 312 3>, <62 374 2>,
<64 434 2>, <66 438 3>, <69 86 1>,
<70 520 54>, <124 609 31>, <155 63 1>,
<156 716 12>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
qup_uart5_tx: qup-uart5-tx {
pins = "gpio22";
function = "qup05";
};
pdc_reset: reset-controller@b5e0000 {
compatible = "qcom,sc7280-pdc-global";
reg = <0 0x0b5e0000 0 0x20000>;
#reset-cells = <1>;
qup_uart5_rx: qup-uart5-rx {
pins = "gpio23";
function = "qup05";
};
tsens0: thermal-sensor@c263000 {
compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
reg = <0 0x0c263000 0 0x1ff>, /* TM */
<0 0x0c222000 0 0x1ff>; /* SROT */
#qcom,sensors = <15>;
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow","critical";
#thermal-sensor-cells = <1>;
qup_uart6_cts: qup-uart6-cts {
pins = "gpio24";
function = "qup06";
};
tsens1: thermal-sensor@c265000 {
compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
reg = <0 0x0c265000 0 0x1ff>, /* TM */
<0 0x0c223000 0 0x1ff>; /* SROT */
#qcom,sensors = <12>;
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow","critical";
#thermal-sensor-cells = <1>;
qup_uart6_rts: qup-uart6-rts {
pins = "gpio25";
function = "qup06";
};
aoss_reset: reset-controller@c2a0000 {
compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
reg = <0 0x0c2a0000 0 0x31000>;
#reset-cells = <1>;
qup_uart6_tx: qup-uart6-tx {
pins = "gpio26";
function = "qup06";
};
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sc7280-aoss-qmp";
reg = <0 0x0c300000 0 0x100000>;
interrupts-extended = <&ipcc IPCC_CLIENT_AOP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_AOP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
qup_uart6_rx: qup-uart6-rx {
pins = "gpio27";
function = "qup06";
};
#clock-cells = <0>;
#power-domain-cells = <1>;
qup_uart7_cts: qup-uart7-cts {
pins = "gpio28";
function = "qup07";
};
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0 0x0c440000 0 0x1100>,
<0 0x0c600000 0 0x2000000>,
<0 0x0e600000 0 0x100000>,
<0 0x0e700000 0 0xa0000>,
<0 0x0c40a000 0 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <4>;
qup_uart7_rts: qup-uart7-rts {
pins = "gpio29";
function = "qup07";
};
tlmm: pinctrl@f100000 {
compatible = "qcom,sc7280-pinctrl";
reg = <0 0x0f100000 0 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
qup_uart7_tx: qup-uart7-tx {
pins = "gpio30";
function = "qup07";
};
qup_uart5_default: qup-uart5-default {
pins = "gpio46", "gpio47";
function = "qup13";
qup_uart7_rx: qup-uart7-rx {
pins = "gpio31";
function = "qup07";
};
sdc1_on: sdc1-on {
......@@ -1573,10 +3236,6 @@ cmd {
data {
pins = "sdc2_data";
};
sd-cd {
pins = "gpio91";
};
};
sdc2_off: sdc2-off {
......@@ -1598,6 +3257,181 @@ data {
bias-bus-hold;
};
};
qup_uart8_cts: qup-uart8-cts {
pins = "gpio32";
function = "qup10";
};
qup_uart8_rts: qup-uart8-rts {
pins = "gpio33";
function = "qup10";
};
qup_uart8_tx: qup-uart8-tx {
pins = "gpio34";
function = "qup10";
};
qup_uart8_rx: qup-uart8-rx {
pins = "gpio35";
function = "qup10";
};
qup_uart9_cts: qup-uart9-cts {
pins = "gpio36";
function = "qup11";
};
qup_uart9_rts: qup-uart9-rts {
pins = "gpio37";
function = "qup11";
};
qup_uart9_tx: qup-uart9-tx {
pins = "gpio38";
function = "qup11";
};
qup_uart9_rx: qup-uart9-rx {
pins = "gpio39";
function = "qup11";
};
qup_uart10_cts: qup-uart10-cts {
pins = "gpio40";
function = "qup12";
};
qup_uart10_rts: qup-uart10-rts {
pins = "gpio41";
function = "qup12";
};
qup_uart10_tx: qup-uart10-tx {
pins = "gpio42";
function = "qup12";
};
qup_uart10_rx: qup-uart10-rx {
pins = "gpio43";
function = "qup12";
};
qup_uart11_cts: qup-uart11-cts {
pins = "gpio44";
function = "qup13";
};
qup_uart11_rts: qup-uart11-rts {
pins = "gpio45";
function = "qup13";
};
qup_uart11_tx: qup-uart11-tx {
pins = "gpio46";
function = "qup13";
};
qup_uart11_rx: qup-uart11-rx {
pins = "gpio47";
function = "qup13";
};
qup_uart12_cts: qup-uart12-cts {
pins = "gpio48";
function = "qup14";
};
qup_uart12_rts: qup-uart12-rts {
pins = "gpio49";
function = "qup14";
};
qup_uart12_tx: qup-uart12-tx {
pins = "gpio50";
function = "qup14";
};
qup_uart12_rx: qup-uart12-rx {
pins = "gpio51";
function = "qup14";
};
qup_uart13_cts: qup-uart13-cts {
pins = "gpio52";
function = "qup15";
};
qup_uart13_rts: qup-uart13-rts {
pins = "gpio53";
function = "qup15";
};
qup_uart13_tx: qup-uart13-tx {
pins = "gpio54";
function = "qup15";
};
qup_uart13_rx: qup-uart13-rx {
pins = "gpio55";
function = "qup15";
};
qup_uart14_cts: qup-uart14-cts {
pins = "gpio56";
function = "qup16";
};
qup_uart14_rts: qup-uart14-rts {
pins = "gpio57";
function = "qup16";
};
qup_uart14_tx: qup-uart14-tx {
pins = "gpio58";
function = "qup16";
};
qup_uart14_rx: qup-uart14-rx {
pins = "gpio59";
function = "qup16";
};
qup_uart15_cts: qup-uart15-cts {
pins = "gpio60";
function = "qup17";
};
qup_uart15_rts: qup-uart15-rts {
pins = "gpio61";
function = "qup17";
};
qup_uart15_tx: qup-uart15-tx {
pins = "gpio62";
function = "qup17";
};
qup_uart15_rx: qup-uart15-rx {
pins = "gpio63";
function = "qup17";
};
};
imem@146a5000 {
compatible = "qcom,sc7280-imem", "syscon";
reg = <0 0x146a5000 0 0x6000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x146a5000 0x6000>;
pil-reloc@594c {
compatible = "qcom,pil-reloc-info";
reg = <0x594c 0xc8>;
};
};
apps_smmu: iommu@15000000 {
......@@ -2471,16 +4305,16 @@ cpuss1_crit: cluster0-crit {
};
gpuss0-thermal {
polling-delay-passive = <0>;
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&tsens1 1>;
trips {
gpuss0_alert0: trip-point0 {
temperature = <90000>;
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
type = "passive";
};
gpuss0_crit: gpuss0-crit {
......@@ -2489,19 +4323,26 @@ gpuss0_crit: gpuss0-crit {
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&gpuss0_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpuss1-thermal {
polling-delay-passive = <0>;
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&tsens1 2>;
trips {
gpuss1_alert0: trip-point0 {
temperature = <90000>;
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
type = "passive";
};
gpuss1_crit: gpuss1-crit {
......@@ -2510,6 +4351,13 @@ gpuss1_crit: gpuss1-crit {
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&gpuss1_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
nspss0-thermal {
......
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi
View file @ c7613530
......@@ -308,7 +308,7 @@ vreg_l3b_3p0: l3 {
regulator-allow-set-load;
};
vreg_l4b_29p5: l4 {
vreg_l4b_2p95: l4 {
regulator-min-microvolt = <2944000>;
regulator-max-microvolt = <2952000>;
regulator-enable-ramp-delay = <250>;
......@@ -327,7 +327,7 @@ vreg_l4b_29p5: l4 {
* Tighten the range to 1.8-3.328 (closest to 3.3) to
* make the mmc driver happy.
*/
vreg_l5b_29p5: l5 {
vreg_l5b_2p95: l5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3328000>;
regulator-enable-ramp-delay = <250>;
......@@ -559,14 +559,14 @@ &sdhc_1 {
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
vmmc-supply = <&vreg_l4b_29p5>;
vmmc-supply = <&vreg_l4b_2p95>;
vqmmc-supply = <&vreg_l8a_1p8>;
};
&sdhc_2 {
status = "okay";
vmmc-supply = <&vreg_l5b_29p5>;
vmmc-supply = <&vreg_l5b_2p95>;
vqmmc-supply = <&vreg_l2b_2p95>;
};
......
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file @ c7613530
......@@ -763,6 +763,8 @@ adsp_pas: remoteproc-adsp {
memory-region = <&adsp_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
......@@ -862,6 +864,8 @@ cdsp_pas: remoteproc-cdsp {
memory-region = <&cdsp_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&cdsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
......@@ -2307,15 +2311,15 @@ ufs_mem_phy_lanes: lanes@1d87400 {
};
};
cryptobam: dma@1dc4000 {
cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v1.7.0";
reg = <0 0x01dc4000 0 0x24000>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rpmhcc 15>;
clocks = <&rpmhcc RPMH_CE_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
qcom,controlled-remotely = <1>;
qcom,controlled-remotely;
iommus = <&apps_smmu 0x704 0x1>,
<&apps_smmu 0x706 0x1>,
<&apps_smmu 0x714 0x1>,
......@@ -2327,7 +2331,7 @@ crypto: crypto@1dfa000 {
reg = <0 0x01dfa000 0 0x6000>;
clocks = <&gcc GCC_CE1_AHB_CLK>,
<&gcc GCC_CE1_AHB_CLK>,
<&rpmhcc 15>;
<&rpmhcc RPMH_CE_CLK>;
clock-names = "iface", "bus", "core";
dmas = <&cryptobam 6>, <&cryptobam 7>;
dma-names = "rx", "tx";
......@@ -2979,6 +2983,8 @@ mss_pil: remoteproc@4080000 {
clock-names = "iface", "bus", "mem", "gpll0_mss",
"snoc_axi", "mnoc_axi", "prng", "xo";
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
......@@ -2988,11 +2994,10 @@ mss_pil: remoteproc@4080000 {
qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
power-domains = <&aoss_qmp 2>,
<&rpmhpd SDM845_CX>,
power-domains = <&rpmhpd SDM845_CX>,
<&rpmhpd SDM845_MX>,
<&rpmhpd SDM845_MSS>;
power-domain-names = "load_state", "cx", "mx", "mss";
power-domain-names = "cx", "mx", "mss";
mba {
memory-region = <&mba_region>;
......@@ -3641,6 +3646,30 @@ swm: swm@c85 {
};
};
lmh_cluster1: lmh@17d70800 {
compatible = "qcom,sdm845-lmh";
reg = <0 0x17d70800 0 0x400>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
cpus = <&CPU4>;
qcom,lmh-temp-arm-millicelsius = <65000>;
qcom,lmh-temp-low-millicelsius = <94500>;
qcom,lmh-temp-high-millicelsius = <95000>;
interrupt-controller;
#interrupt-cells = <1>;
};
lmh_cluster0: lmh@17d78800 {
compatible = "qcom,sdm845-lmh";
reg = <0 0x17d78800 0 0x400>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
cpus = <&CPU0>;
qcom,lmh-temp-arm-millicelsius = <65000>;
qcom,lmh-temp-low-millicelsius = <94500>;
qcom,lmh-temp-high-millicelsius = <95000>;
interrupt-controller;
#interrupt-cells = <1>;
};
sound: sound {
};
......@@ -4583,7 +4612,6 @@ aoss_qmp: power-controller@c300000 {
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
#power-domain-cells = <1>;
cx_cdev: cx {
#cooling-cells = <2>;
......@@ -4912,6 +4940,8 @@ cpufreq_hw: cpufreq@17d43000 {
reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
reg-names = "freq-domain0", "freq-domain1";
interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
......@@ -4969,23 +4999,6 @@ cpu0_crit: cpu_crit {
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu0_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu0_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu1-thermal {
......@@ -5013,23 +5026,6 @@ cpu1_crit: cpu_crit {
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu1_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu1_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu2-thermal {
......@@ -5057,23 +5053,6 @@ cpu2_crit: cpu_crit {
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu2_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu2_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu3-thermal {
......@@ -5101,23 +5080,6 @@ cpu3_crit: cpu_crit {
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu3_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu3_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu4-thermal {
......@@ -5145,23 +5107,6 @@ cpu4_crit: cpu_crit {
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu4_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu4_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu5-thermal {
......@@ -5189,23 +5134,6 @@ cpu5_crit: cpu_crit {
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu5_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu5_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu6-thermal {
......@@ -5233,23 +5161,6 @@ cpu6_crit: cpu_crit {
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu6_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu6_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu7-thermal {
......@@ -5277,23 +5188,6 @@ cpu7_crit: cpu_crit {
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu7_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu7_alert1>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
aoss0-thermal {
......
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
View file @ c7613530
......@@ -230,6 +230,9 @@ vreg_l22a_2p85: ldo22 {
};
vreg_l23a_3p3: ldo23 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdda_qusb_hs0_3p1:
......@@ -615,6 +618,7 @@ bluetooth {
vddxo-supply = <&vreg_l7a_1p8>;
vddrf-supply = <&vreg_l17a_1p3>;
vddch0-supply = <&vreg_l25a_3p3>;
vddch1-supply = <&vreg_l23a_3p3>;
max-speed = <3200000>;
};
};
......@@ -729,6 +733,7 @@ &wifi {
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
vdd-3.3-ch1-supply = <&vreg_l23a_3p3>;
qcom,snoc-host-cap-8bit-quirk;
};
arch/arm64/boot/dts/qcom/sm6125.dtsi
View file @ c7613530
......@@ -494,7 +494,7 @@ timer@f120000 {
reg = <0x0f120000 0x1000>;
clock-frequency = <19200000>;
frame@0f121000 {
frame@f121000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
......@@ -502,14 +502,14 @@ frame@0f121000 {
<0x0f122000 0x1000>;
};
frame@0f123000 {
frame@f123000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0f123000 0x1000>;
status = "disabled";
};
frame@0f124000 {
frame@f124000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0f124000 0x1000>;
......
arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts 0 → 100644
View file @ c7613530
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
*/
/dts-v1/;
#include "sm6350.dtsi"
/ {
model = "Sony Xperia 10 III";
compatible = "sony,pdx213", "qcom,sm6350";
qcom,msm-id = <434 0x10000>, <459 0x10000>;
qcom,board-id = <0x1000B 0>;
chosen {
#address-cells = <2>;
#size-cells = <2>;
ranges;
framebuffer: framebuffer@a0000000 {
compatible = "simple-framebuffer";
reg = <0 0xa0000000 0 0x2300000>;
width = <1080>;
height = <2520>;
stride = <(1080 * 4)>;
format = "a8r8g8b8";
clocks = <&gcc GCC_DISP_AXI_CLK>;
};
};
};
&sdhc_2 {
status = "okay";
cd-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>;
};
&tlmm {
gpio-reserved-ranges = <13 4>, <45 2>, <56 2>;
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
maximum-speed = "super-speed";
dr_mode = "peripheral";
};
&usb_1_hsphy {
status = "okay";
};
&usb_1_qmpphy {
status = "okay";
};
arch/arm64/boot/dts/qcom/sm6350.dtsi 0 → 100644
View file @ c7613530
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
*/
#include <dt-bindings/clock/qcom,gcc-sm6350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <76800000>;
clock-output-names = "xo_board";
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32764>;
#clock-cells = <0>;
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
};
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x200>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x300>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x400>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_400>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x500>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_500>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x600>;
enable-method = "psci";
capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <703>;
next-level-cache = <&L2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x700>;
enable-method = "psci";
capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <703>;
next-level-cache = <&L2_700>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
core4 {
cpu = <&CPU4>;
};
core5 {
cpu = <&CPU5>;
};
core6 {
cpu = <&CPU6>;
};
core7 {
cpu = <&CPU7>;
};
};
};
};
firmware {
scm: scm {
compatible = "qcom,scm-sm6350", "qcom,scm";
#reset-cells = <1>;
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0x0 0x80000000 0x0 0x0>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_mem: memory@80000000 {
reg = <0 0x80000000 0 0x600000>;
no-map;
};
xbl_aop_mem: memory@80700000 {
reg = <0 0x80700000 0 0x160000>;
no-map;
};
cmd_db: memory@80860000 {
compatible = "qcom,cmd-db";
reg = <0 0x80860000 0 0x20000>;
no-map;
};
sec_apps_mem: memory@808ff000 {
reg = <0 0x808ff000 0 0x1000>;
no-map;
};
smem_mem: memory@80900000 {
reg = <0 0x80900000 0 0x200000>;
no-map;
};
cdsp_sec_mem: memory@80b00000 {
reg = <0 0x80b00000 0 0x1e00000>;
no-map;
};
pil_camera_mem: memory@86000000 {
reg = <0 0x86000000 0 0x500000>;
no-map;
};
pil_npu_mem: memory@86500000 {
reg = <0 0x86500000 0 0x500000>;
no-map;
};
pil_video_mem: memory@86a00000 {
reg = <0 0x86a00000 0 0x500000>;
no-map;
};
pil_cdsp_mem: memory@86f00000 {
reg = <0 0x86f00000 0 0x1e00000>;
no-map;
};
pil_adsp_mem: memory@88d00000 {
reg = <0 0x88d00000 0 0x2800000>;
no-map;
};
wlan_fw_mem: memory@8b500000 {
reg = <0 0x8b500000 0 0x200000>;
no-map;
};
pil_ipa_fw_mem: memory@8b700000 {
reg = <0 0x8b700000 0 0x10000>;
no-map;
};
pil_ipa_gsi_mem: memory@8b710000 {
reg = <0 0x8b710000 0 0x5400>;
no-map;
};
pil_gpu_mem: memory@8b715400 {
reg = <0 0x8b715400 0 0x2000>;
no-map;
};
pil_modem_mem: memory@8b800000 {
reg = <0 0x8b800000 0 0xf800000>;
no-map;
};
cont_splash_memory: memory@a0000000 {
reg = <0 0xa0000000 0 0x2300000>;
no-map;
};
dfps_data_memory: memory@a2300000 {
reg = <0 0xa2300000 0 0x100000>;
no-map;
};
removed_region: memory@c0000000 {
reg = <0 0xc0000000 0 0x3900000>;
no-map;
};
debug_region: memory@ffb00000 {
reg = <0 0xffb00000 0 0xc0000>;
no-map;
};
last_log_region: memory@ffbc0000 {
reg = <0 0xffbc0000 0 0x40000>;
no-map;
};
ramoops: ramoops@ffc00000 {
compatible = "removed-dma-pool", "ramoops";
reg = <0 0xffc00000 0 0x00100000>;
record-size = <0x1000>;
console-size = <0x40000>;
ftrace-size = <0x0>;
msg-size = <0x20000 0x20000>;
cc-size = <0x0>;
no-map;
};
cmdline_region: memory@ffd00000 {
reg = <0 0xffd00000 0 0x1000>;
no-map;
};
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0 0x10 0>;
dma-ranges = <0 0 0 0 0x10 0>;
compatible = "simple-bus";
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sm6350";
reg = <0 0x00100000 0 0x1f0000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clock-names = "bi_tcxo",
"bi_tcxo_ao",
"sleep_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
};
ipcc: mailbox@408000 {
compatible = "qcom,sm6350-ipcc", "qcom,ipcc";
reg = <0 0x00408000 0 0x1000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
rng: rng@793000 {
compatible = "qcom,prng-ee";
reg = <0 0x00793000 0 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
sdhc_1: sdhci@7c4000 {
compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x007c4000 0 0x1000>,
<0 0x007c5000 0 0x1000>,
<0 0x007c8000 0 0x8000>;
reg-names = "hc", "cqhci", "ice";
interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "core", "xo";
qcom,dll-config = <0x000f642c>;
qcom,ddr-config = <0x80040868>;
power-domains = <&rpmhpd 0>;
operating-points-v2 = <&sdhc1_opp_table>;
bus-width = <8>;
non-removable;
supports-cqe;
status = "disabled";
sdhc1_opp_table: sdhc1-opp-table {
compatible = "operating-points-v2";
opp-19200000 {
opp-hz = /bits/ 64 <19200000>;
required-opps = <&rpmhpd_opp_min_svs>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
#hwlock-cells = <1>;
};
sdhc_2: sdhci@8804000 {
compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "core", "xo";
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
power-domains = <&rpmhpd 0>;
operating-points-v2 = <&sdhc2_opp_table>;
bus-width = <4>;
status = "disabled";
sdhc2_opp_table: sdhc2-opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
usb_1_hsphy: phy@88e3000 {
compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
reg = <0 0x088e3000 0 0x400>;
status = "disabled";
#phy-cells = <0>;
clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>;
clock-names = "cfg_ahb", "ref";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
};
usb_1_qmpphy: phy@88e9000 {
compatible = "qcom,sc7180-qmp-usb3-dp-phy";
reg = <0 0x088e9000 0 0x200>,
<0 0x088e8000 0 0x40>,
<0 0x088ea000 0 0x200>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&rpmhcc RPMH_QLINK_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
<&xo_board>;
clock-names = "aux", "ref", "com_aux", "cfg_ahb";
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "phy", "common";
usb_1_ssphy: usb3-phy@88e9200 {
reg = <0 0x088e9200 0 0x200>,
<0 0x088e9400 0 0x200>,
<0 0x088e9c00 0 0x400>,
<0 0x088e9600 0 0x200>,
<0 0x088e9800 0 0x200>,
<0 0x088e9a00 0 0x100>;
#clock-cells = <0>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
dp_phy: dp-phy@88ea200 {
reg = <0 0x088ea200 0 0x200>,
<0 0x088ea400 0 0x200>,
<0 0x088eac00 0 0x400>,
<0 0x088ea600 0 0x200>,
<0 0x088ea800 0 0x200>,
<0 0x088eaa00 0 0x100>;
#phy-cells = <0>;
#clock-cells = <1>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
};
system-cache-controller@9200000 {
compatible = "qcom,sm6350-llcc";
reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
};
usb_1: usb@a6f8800 {
compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
clock-names = "cfg_noc", "core", "iface", "mock_utmi",
"sleep";
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
"dm_hs_phy_irq", "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
resets = <&gcc GCC_USB30_PRIM_BCR>;
usb_1_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0x540 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm6350-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
qcom,pdc-ranges = <0 480 94>, <94 609 31>,
<125 63 1>, <126 655 12>, <138 139 15>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
tsens0: thermal-sensor@c263000 {
compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
reg = <0 0x0c263000 0 0x1ff>, /* TM */
<0 0x0c222000 0 0x8>; /* SROT */
#qcom,sensors = <16>;
interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
tsens1: thermal-sensor@c265000 {
compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
reg = <0 0x0c265000 0 0x1ff>, /* TM */
<0 0x0c223000 0 0x8>; /* SROT */
#qcom,sensors = <16>;
interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp";
reg = <0 0x0c300000 0 0x1000>;
interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
#power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0 0xc440000 0 0x1100>,
<0 0xc600000 0 0x2000000>,
<0 0xe600000 0 0x100000>,
<0 0xe700000 0 0xa0000>,
<0 0xc40a000 0 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
};
tlmm: pinctrl@f100000 {
compatible = "qcom,sm6350-tlmm";
reg = <0 0x0f100000 0 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 157>;
};
apps_smmu: iommu@15000000 {
compatible = "qcom,sm6350-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
};
watchdog@17c10000 {
compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
timer@17c20000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x17c20000 0x0 0x1000>;
clock-frequency = <19200000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
frame@17c21000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c21000 0x0 0x1000>,
<0x0 0x17c22000 0x0 0x1000>;
};
frame@17c23000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c23000 0x0 0x1000>;
status = "disabled";
};
frame@17c25000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c25000 0x0 0x1000>;
status = "disabled";
};
frame@17c27000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c27000 0x0 0x1000>;
status = "disabled";
};
frame@17c29000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c29000 0x0 0x1000>;
status = "disabled";
};
frame@17c2b000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c2b000 0x0 0x1000>;
status = "disabled";
};
frame@17c2d000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c2d000 0x0 0x1000>;
status = "disabled";
};
};
apps_rsc: rsc@18200000 {
compatible = "qcom,rpmh-rsc";
label = "apps_rsc";
reg = <0x0 0x18200000 0x0 0x10000>,
<0x0 0x18210000 0x0 0x10000>,
<0x0 0x18220000 0x0 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
<WAKE_TCS 3>, <CONTROL_TCS 1>;
rpmhcc: clock-controller {
compatible = "qcom,sm6350-rpmh-clk";
#clock-cells = <1>;
clock-names = "xo";
clocks = <&xo_board>;
};
rpmhpd: power-controller {
compatible = "qcom,sm6350-rpmhpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmhpd_opp_table>;
rpmhpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmhpd_opp_ret: opp1 {
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
};
rpmhpd_opp_min_svs: opp2 {
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
};
rpmhpd_opp_low_svs: opp3 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};
rpmhpd_opp_svs: opp4 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};
rpmhpd_opp_svs_l1: opp5 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
rpmhpd_opp_nom: opp6 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
};
rpmhpd_opp_nom_l1: opp7 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
};
rpmhpd_opp_nom_l2: opp8 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
};
rpmhpd_opp_turbo: opp9 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
};
rpmhpd_opp_turbo_l1: opp10 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
};
};
};
apps_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
};
};
cpufreq_hw: cpufreq@18323000 {
compatible = "qcom,cpufreq-hw";
reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
reg-names = "freq-domain0", "freq-domain1";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
};
};
timer {
compatible = "arm,armv8-timer";
clock-frequency = <19200000>;
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
};
arch/arm64/boot/dts/qcom/sm8150.dtsi
View file @ c7613530
......@@ -6,7 +6,6 @@
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
......@@ -1729,13 +1728,14 @@ remoteproc_slpi: remoteproc@2400000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
<&rpmhpd 3>,
power-domains = <&rpmhpd 3>,
<&rpmhpd 2>;
power-domain-names = "load_state", "lcx", "lmx";
power-domain-names = "lcx", "lmx";
memory-region = <&slpi_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&slpi_smp2p_out 0>;
qcom,smem-state-names = "stop";
......@@ -2319,13 +2319,14 @@ remoteproc_mpss: remoteproc@4080000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
<&rpmhpd 7>,
power-domains = <&rpmhpd 7>,
<&rpmhpd 0>;
power-domain-names = "load_state", "cx", "mss";
power-domain-names = "cx", "mss";
memory-region = <&mpss_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
......@@ -2945,12 +2946,12 @@ remoteproc_cdsp: remoteproc@8300000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
<&rpmhpd 7>;
power-domain-names = "load_state", "cx";
power-domains = <&rpmhpd 7>;
memory-region = <&cdsp_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&cdsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
......@@ -3174,7 +3175,6 @@ aoss_qmp: power-controller@c300000 {
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
#power-domain-cells = <1>;
};
tsens0: thermal-sensor@c263000 {
......@@ -3321,12 +3321,12 @@ remoteproc_adsp: remoteproc@17300000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
<&rpmhpd 7>;
power-domain-names = "load_state", "cx";
power-domains = <&rpmhpd 7>;
memory-region = <&adsp_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
......
arch/arm64/boot/dts/qcom/sm8250.dtsi
View file @ c7613530
......@@ -13,7 +13,6 @@
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm8250.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
......@@ -2088,13 +2087,14 @@ slpi: remoteproc@5c00000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
<&rpmhpd SM8250_LCX>,
power-domains = <&rpmhpd SM8250_LCX>,
<&rpmhpd SM8250_LMX>;
power-domain-names = "load_state", "lcx", "lmx";
power-domain-names = "lcx", "lmx";
memory-region = <&slpi_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_slpi_out 0>;
qcom,smem-state-names = "stop";
......@@ -2154,12 +2154,12 @@ cdsp: remoteproc@8300000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
<&rpmhpd SM8250_CX>;
power-domain-names = "load_state", "cx";
power-domains = <&rpmhpd SM8250_CX>;
memory-region = <&cdsp_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_cdsp_out 0>;
qcom,smem-state-names = "stop";
......@@ -2907,7 +2907,6 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
#power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
......@@ -3824,13 +3823,14 @@ adsp: remoteproc@17300000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
<&rpmhpd SM8250_LCX>,
power-domains = <&rpmhpd SM8250_LCX>,
<&rpmhpd SM8250_LMX>;
power-domain-names = "load_state", "lcx", "lmx";
power-domain-names = "lcx", "lmx";
memory-region = <&adsp_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
......
arch/arm64/boot/dts/qcom/sm8350.dtsi
View file @ c7613530
......@@ -8,7 +8,6 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,sm8350.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/thermal/thermal.h>
......@@ -726,15 +725,16 @@ mpss: remoteproc@4080000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
<&rpmhpd 0>,
power-domains = <&rpmhpd 0>,
<&rpmhpd 12>;
power-domain-names = "load_state", "cx", "mss";
power-domain-names = "cx", "mss";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
memory-region = <&pil_modem_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_modem_out 0>;
qcom,smem-state-names = "stop";
......@@ -794,7 +794,6 @@ aoss_qmp: power-controller@c300000 {
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
#power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
......@@ -1107,13 +1106,14 @@ slpi: remoteproc@5c00000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
<&rpmhpd 4>,
power-domains = <&rpmhpd 4>,
<&rpmhpd 5>;
power-domain-names = "load_state", "lcx", "lmx";
power-domain-names = "lcx", "lmx";
memory-region = <&pil_slpi_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_slpi_out 0>;
qcom,smem-state-names = "stop";
......@@ -1147,15 +1147,16 @@ cdsp: remoteproc@98900000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
<&rpmhpd 0>,
power-domains = <&rpmhpd 0>,
<&rpmhpd 10>;
power-domain-names = "load_state", "cx", "mxc";
power-domain-names = "cx", "mxc";
interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
memory-region = <&pil_cdsp_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_cdsp_out 0>;
qcom,smem-state-names = "stop";
......@@ -1381,13 +1382,14 @@ adsp: remoteproc@17300000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
<&rpmhpd 4>,
power-domains = <&rpmhpd 4>,
<&rpmhpd 5>;
power-domain-names = "load_state", "lcx", "lmx";
power-domain-names = "lcx", "lmx";
memory-region = <&pil_adsp_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
......
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