Commit c80dfd9b authored by Pan Wen's avatar Pan Wen Committed by Stephen Boyd

clk: hisilicon: add CRG driver for Hi3516CV300 SoC

Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset
Generator) module generates clock and reset signals used
by other module blocks on SoC.
Signed-off-by: default avatarPan Wen <wenpan@hisilicon.com>
Signed-off-by: default avatarJiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 707d33cb
config COMMON_CLK_HI3516CV300
tristate "HI3516CV300 Clock Driver"
depends on ARCH_HISI || COMPILE_TEST
select RESET_HISI
default ARCH_HISI
help
Build the clock driver for hi3516cv300.
config COMMON_CLK_HI3519
tristate "Hi3519 Clock Driver"
depends on ARCH_HISI || COMPILE_TEST
......
......@@ -7,6 +7,7 @@ obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
......
This diff is collapsed.
/*
* Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __DTS_HI3516CV300_CLOCK_H
#define __DTS_HI3516CV300_CLOCK_H
/* hi3516CV300 core CRG */
#define HI3516CV300_APB_CLK 0
#define HI3516CV300_UART0_CLK 1
#define HI3516CV300_UART1_CLK 2
#define HI3516CV300_UART2_CLK 3
#define HI3516CV300_SPI0_CLK 4
#define HI3516CV300_SPI1_CLK 5
#define HI3516CV300_FMC_CLK 6
#define HI3516CV300_MMC0_CLK 7
#define HI3516CV300_MMC1_CLK 8
#define HI3516CV300_MMC2_CLK 9
#define HI3516CV300_MMC3_CLK 10
#define HI3516CV300_ETH_CLK 11
#define HI3516CV300_ETH_MACIF_CLK 12
#define HI3516CV300_DMAC_CLK 13
#define HI3516CV300_PWM_CLK 14
#define HI3516CV300_USB2_BUS_CLK 15
#define HI3516CV300_USB2_OHCI48M_CLK 16
#define HI3516CV300_USB2_OHCI12M_CLK 17
#define HI3516CV300_USB2_OTG_UTMI_CLK 18
#define HI3516CV300_USB2_HST_PHY_CLK 19
#define HI3516CV300_USB2_UTMI0_CLK 20
#define HI3516CV300_USB2_PHY_CLK 21
/* hi3516CV300 sysctrl CRG */
#define HI3516CV300_WDT_CLK 1
#endif /* __DTS_HI3516CV300_CLOCK_H */
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment