Commit c84700cc authored by James Hogan's avatar James Hogan Committed by Ralf Baechle

MIPS: Add missing tlbinvf/XPA microMIPS encodings

Hardcoded MIPS instruction encodings are provided for tlbinvf, mfhc0 &
mthc0 instructions, but microMIPS encodings are missing. I doubt any
microMIPS cores exist at present which support these instructions, but
the microMIPS encodings exist, and microMIPS cores may support them in
the future. Add the missing microMIPS encodings using the new macros.
Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13313/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 6e1b29c3
...@@ -1083,7 +1083,9 @@ static inline void tlbinvf(void) ...@@ -1083,7 +1083,9 @@ static inline void tlbinvf(void)
__asm__ __volatile__( __asm__ __volatile__(
".set push\n\t" ".set push\n\t"
".set noreorder\n\t" ".set noreorder\n\t"
".word 0x42000004\n\t" /* tlbinvf */ "# tlbinvf\n\t"
_ASM_INSN_IF_MIPS(0x42000004)
_ASM_INSN32_IF_MM(0x0000537c)
".set pop"); ".set pop");
} }
...@@ -1304,9 +1306,9 @@ do { \ ...@@ -1304,9 +1306,9 @@ do { \
" .set push \n" \ " .set push \n" \
" .set noat \n" \ " .set noat \n" \
" .set mips32r2 \n" \ " .set mips32r2 \n" \
" .insn \n" \
" # mfhc0 $1, %1 \n" \ " # mfhc0 $1, %1 \n" \
" .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \ _ASM_INSN_IF_MIPS(0x40410000 | ((%1 & 0x1f) << 11)) \
_ASM_INSN32_IF_MM(0x002000f4 | ((%1 & 0x1f) << 16)) \
" move %0, $1 \n" \ " move %0, $1 \n" \
" .set pop \n" \ " .set pop \n" \
: "=r" (__res) \ : "=r" (__res) \
...@@ -1322,8 +1324,8 @@ do { \ ...@@ -1322,8 +1324,8 @@ do { \
" .set mips32r2 \n" \ " .set mips32r2 \n" \
" move $1, %0 \n" \ " move $1, %0 \n" \
" # mthc0 $1, %1 \n" \ " # mthc0 $1, %1 \n" \
" .insn \n" \ _ASM_INSN_IF_MIPS(0x40c10000 | ((%1 & 0x1f) << 11)) \
" .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \ _ASM_INSN32_IF_MM(0x002002f4 | ((%1 & 0x1f) << 16)) \
" .set pop \n" \ " .set pop \n" \
: \ : \
: "r" (value), "i" (register)); \ : "r" (value), "i" (register)); \
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment