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Commit c84f2c3f authored by Russell King's avatar Russell King
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[ARM] Move common CPU initialisation into head.S

parent a359e554
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Showing with 285 additions and 340 deletions
arch/arm/kernel/head.S
View file @ c84f2c3f
......@@ -14,6 +14,7 @@
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/domain.h>
#include <asm/mach-types.h>
#include <asm/procinfo.h>
#include <asm/ptrace.h>
......@@ -166,7 +167,9 @@ __mmap_switched:
/*
* Setup common bits before finally enabling the MMU.
* Setup common bits before finally enabling the MMU. Essentially
* this is just loading the page table pointer and domain access
* registers.
*/
.type __enable_mmu, %function
__enable_mmu:
......@@ -175,6 +178,21 @@ __enable_mmu:
#else
bic r0, r0, #CR_A
#endif
#ifdef CONFIG_CPU_DCACHE_DISABLE
bic r0, r0, #CR_C
#endif
#ifdef CONFIG_CPU_BPREDICT_DISABLE
bic r0, r0, #CR_Z
#endif
#ifdef CONFIG_CPU_ICACHE_DISABLE
bic r0, r0, #CR_I
#endif
mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT))
mcr p15, 0, r5, c3, c0, 0 @ load domain access register
mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
b __turn_mmu_on
/*
......
arch/arm/mm/proc-arm1020.S
View file @ c84f2c3f
......@@ -30,7 +30,6 @@
#include <asm/assembler.h>
#include <asm/constants.h>
#include <asm/pgtable.h>
#include <asm/domain.h>
#include <asm/procinfo.h>
#include <asm/ptrace.h>
#include <asm/hardware.h>
......@@ -432,39 +431,29 @@ __arm1020_setup:
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
mcr p15, 0, r4, c2, c0 @ load page table pointer
mov r0, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT))
mcr p15, 0, r0, c3, c0 @ load domain access register
mrc p15, 0, r0, c1, c0 @ get control register v4
/*
* Clear out 'unwanted' bits (then put them in if we need them)
*/
bic r0, r0, #0x1e00 @ i...??r.........
bic r0, r0, #0x000e @ ............wca.
/*
* Turn on what we want
*/
orr r0, r0, #0x0031 @ ..........DP...M
orr r0, r0, #0x0100 @ .......S........
ldr r5, arm1020_cr1_clear
bic r0, r0, r5
ldr r5, arm1020_cr1_set
orr r0, r0, r5
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .R..............
#endif
#ifndef CONFIG_CPU_BPREDICT_DISABLE
orr r0, r0, #0x0800 @ ....Z...........
#endif
#ifndef CONFIG_CPU_DCACHE_DISABLE
orr r0, r0, #0x0004 @ Enable D cache
#endif
#ifndef CONFIG_CPU_ICACHE_DISABLE
orr r0, r0, #0x1000 @ I Cache on
orr r0, r0, #0x4000 @ .R.. .... .... ....
#endif
mov pc, lr
.size __arm1020_setup, . - __arm1020_setup
/*
* R
* .RVI ZFRS BLDP WCAM
* .0.1 1001 ..11 0101 /* FIXME: why no V bit? */
*/
.type arm1020_cr1_clear, #object
.type arm1020_cr1_set, #object
arm1020_cr1_clear:
.word 0x593f
arm1020_cr1_set:
.word 0x1935
__INITDATA
/*
......
arch/arm/mm/proc-arm1020e.S
View file @ c84f2c3f
......@@ -30,7 +30,6 @@
#include <asm/assembler.h>
#include <asm/constants.h>
#include <asm/pgtable.h>
#include <asm/domain.h>
#include <asm/procinfo.h>
#include <asm/ptrace.h>
#include <asm/hardware.h>
......@@ -414,40 +413,29 @@ __arm1020e_setup:
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
mcr p15, 0, r4, c2, c0 @ load page table pointer
mov r0, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT))
mcr p15, 0, r0, c3, c0 @ load domain access register
mrc p15, 0, r0, c1, c0 @ get control register v4
/*
* Clear out 'unwanted' bits (then put them in if we need them)
*/
bic r0, r0, #0x1e00 @ i...??r.........
bic r0, r0, #0x000e @ ............wca.
/*
* Turn on what we want
*/
orr r0, r0, #0x0031 @ ..........DP...M
orr r0, r0, #0x0100 @ .......S........
ldr r5, arm1020e_cr1_clear
bic r0, r0, r5
ldr r5, arm1020e_cr1_set
orr r0, r0, r5
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .R..............
#endif
#ifndef CONFIG_CPU_BPREDICT_DISABLE
orr r0, r0, #0x0800 @ ....Z...........
#endif
#ifndef CONFIG_CPU_DCACHE_DISABLE
orr r0, r0, #0x0004 @ Enable D cache
#endif
#ifndef CONFIG_CPU_ICACHE_DISABLE
orr r0, r0, #0x1000 @ I Cache on
orr r0, r0, #0x4000 @ .R.. .... .... ....
#endif
mov pc, lr
.size __arm1020e_setup, . - __arm1020e_setup
/*
* R
* .RVI ZFRS BLDP WCAM
* .0.1 1001 ..11 0101 /* FIXME: why no V bit? */
*/
.type arm1020e_cr1_clear, #object
.type arm1020e_cr1_set, #object
arm1020e_cr1_clear:
.word 0x5f3f
arm1020e_cr1_set:
.word 0x1935
__INITDATA
/*
......
arch/arm/mm/proc-arm1022.S
View file @ c84f2c3f
......@@ -19,7 +19,6 @@
#include <asm/assembler.h>
#include <asm/constants.h>
#include <asm/pgtable.h>
#include <asm/domain.h>
#include <asm/procinfo.h>
#include <asm/ptrace.h>
......@@ -395,39 +394,30 @@ __arm1022_setup:
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
mcr p15, 0, r4, c2, c0 @ load page table pointer
mov r0, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT))
mcr p15, 0, r0, c3, c0 @ load domain access register
mrc p15, 0, r0, c1, c0 @ get control register v4
/*
* Clear out 'unwanted' bits (then put them in if we need them)
*/
bic r0, r0, #0x1e00 @ ...i??r.........
bic r0, r0, #0x000e @ ............wca.
/*
* Turn on what we want
*/
orr r0, r0, #0x0031 @ ..........DP...M
orr r0, r0, #0x2100 @ ..V....S........
ldr r5, arm1022_cr1_clear
bic r0, r0, r5
ldr r5, arm1022_cr1_set
orr r0, r0, r5
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .R..............
#endif
#ifndef CONFIG_CPU_BPREDICT_DISABLE
orr r0, r0, #0x0800 @ ....Z...........
#endif
#ifndef CONFIG_CPU_DCACHE_DISABLE
orr r0, r0, #0x0004 @ .............C..
#endif
#ifndef CONFIG_CPU_ICACHE_DISABLE
orr r0, r0, #0x1000 @ ...I............
#endif
mov pc, lr
.size __arm1022_setup, . - __arm1022_setup
/*
* R
* .RVI ZFRS BLDP WCAM
* .011 1001 ..11 0101
*
*/
.type arm1022_cr1_clear, #object
.type arm1022_cr1_set, #object
arm1022_cr1_clear:
.word 0x7f3f
arm1022_cr1_set:
.word 0x3935
__INITDATA
/*
......
arch/arm/mm/proc-arm1026.S
View file @ c84f2c3f
......@@ -19,7 +19,6 @@
#include <asm/assembler.h>
#include <asm/constants.h>
#include <asm/pgtable.h>
#include <asm/domain.h>
#include <asm/procinfo.h>
#include <asm/ptrace.h>
......@@ -390,38 +389,30 @@ __arm1026_setup:
mov r0, #4 @ explicitly disable writeback
mcr p15, 7, r0, c15, c0, 0
#endif
mov r0, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT))
mcr p15, 0, r0, c3, c0 @ load domain access register
mrc p15, 0, r0, c1, c0 @ get control register v4
/*
* Clear out 'unwanted' bits (then put them in if we need them)
*/
bic r0, r0, #0x1e00 @ ...i??r.........
bic r0, r0, #0x000e @ ............wca.
/*
* Turn on what we want
*/
orr r0, r0, #0x0031 @ ..........DP...M
orr r0, r0, #0x2100 @ ..V....S........
ldr r5, arm1026_cr1_clear
bic r0, r0, r5
ldr r5, arm1026_cr1_set
orr r0, r0, r5
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .R..............
#endif
#ifndef CONFIG_CPU_BPREDICT_DISABLE
orr r0, r0, #0x0800 @ ....Z...........
#endif
#ifndef CONFIG_CPU_DCACHE_DISABLE
orr r0, r0, #0x0004 @ .............C..
#endif
#ifndef CONFIG_CPU_ICACHE_DISABLE
orr r0, r0, #0x1000 @ ...I............
orr r0, r0, #0x4000 @ .R.. .... .... ....
#endif
mov pc, lr
.size __arm1026_setup, . - __arm1026_setup
/*
* R
* .RVI ZFRS BLDP WCAM
* .011 1001 ..11 0101
*
*/
.type arm1026_cr1_clear, #object
.type arm1026_cr1_set, #object
arm1026_cr1_clear:
.word 0x7f3f
arm1026_cr1_set:
.word 0x3935
__INITDATA
/*
......
arch/arm/mm/proc-arm6_7.S
View file @ c84f2c3f
......@@ -15,7 +15,6 @@
#include <asm/assembler.h>
#include <asm/constants.h>
#include <asm/pgtable.h>
#include <asm/domain.h>
#include <asm/procinfo.h>
#include <asm/ptrace.h>
......@@ -254,12 +253,6 @@ ENTRY(cpu_arm7_reset)
__arm6_setup: mov r0, #0
mcr p15, 0, r0, c7, c0 @ flush caches on v3
mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
mcr p15, 0, r4, c2, c0 @ load page table pointer
mov r0, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT))
mcr p15, 0, r0, c3, c0 @ load domain access register
mov r0, #0x3d @ . ..RS BLDP WCAM
orr r0, r0, #0x100 @ . ..01 0011 1101
mov pc, lr
......@@ -269,11 +262,6 @@ __arm6_setup: mov r0, #0
__arm7_setup: mov r0, #0
mcr p15, 0, r0, c7, c0 @ flush caches on v3
mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
mcr p15, 0, r4, c2, c0 @ load page table pointer
mov r0, #(domain_val(DOMAIN_IO, DOMAIN_CLIENT) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
domain_val(DOMAIN_USER, DOMAIN_MANAGER))
mcr p15, 0, r0, c3, c0 @ load domain access register
mov r0, #0x7d @ . ..RS BLDP WCAM
orr r0, r0, #0x100 @ . ..01 0111 1101
......
arch/arm/mm/proc-arm720.S
View file @ c84f2c3f
......@@ -35,7 +35,6 @@
#include <asm/assembler.h>
#include <asm/constants.h>
#include <asm/pgtable.h>
#include <asm/domain.h>
#include <asm/procinfo.h>
#include <asm/ptrace.h>
#include <asm/hardware.h>
......@@ -125,43 +124,59 @@ ENTRY(cpu_arm720_reset)
mcr p15, 0, ip, c1, c0, 0 @ ctrl register
mov pc, r0
__INIT
.type __arm710_setup, #function
__arm710_setup: mov r0, #0
mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
mcr p15, 0, r4, c2, c0 @ load page table pointer
mov r0, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT))
mcr p15, 0, r0, c3, c0 @ load domain access register
mrc p15, 0, r0, c1, c0 @ get control register
bic r0, r0, #0x0e00 @ ..V. ..RS BLDP WCAM
orr r0, r0, #0x0100 @ .... .... .111 .... (old)
orr r0, r0, #0x003d @ .... ..01 ..11 1101 (new)
mov pc, lr @ __ret (head.S)
.size __arm710_setup, . - __arm710_setup
.type __arm720_setup, #function
__arm720_setup: mov r0, #0
mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
mcr p15, 0, r4, c2, c0 @ load page table pointer
mov r0, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT))
mcr p15, 0, r0, c3, c0 @ load domain access register
mrc p15, 0, r0, c1, c0 @ get control register
bic r0, r0, #0x0e00 @ ..V. ..RS BLDP WCAM
orr r0, r0, #0x2100 @ .... .... .111 .... (old)
orr r0, r0, #0x003d @ ..1. ..01 ..11 1101 (new)
mov pc, lr @ __ret (head.S)
.size __arm720_setup, . - __arm720_setup
__INIT
.type __arm710_setup, #function
__arm710_setup:
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
mrc p15, 0, r0, c1, c0 @ get control register
ldr r5, arm710_cr1_clear
bic r0, r0, r5
ldr r5, arm710_cr1_set
orr r0, r0, r5
mov pc, lr @ __ret (head.S)
.size __arm710_setup, . - __arm710_setup
/*
* R
* .RVI ZFRS BLDP WCAM
* .... 0001 ..11 1101
*
*/
.type arm710_cr1_clear, #object
.type arm710_cr1_set, #object
arm710_cr1_clear:
.word 0x0f3f
arm710_cr1_set:
.word 0x013d
.type __arm720_setup, #function
__arm720_setup:
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
mrc p15, 0, r0, c1, c0 @ get control register
ldr r5, arm720_cr1_clear
bic r0, r0, r5
ldr r5, arm720_cr1_set
orr r0, r0, r5
mov pc, lr @ __ret (head.S)
.size __arm720_setup, . - __arm720_setup
/*
* R
* .RVI ZFRS BLDP WCAM
* ..1. 1001 ..11 1101
*
*/
.type arm720_cr1_clear, #object
.type arm720_cr1_set, #object
arm720_cr1_clear:
.word 0x2f3f
arm720_cr1_set:
.word 0x213d
__INITDATA
......
arch/arm/mm/proc-arm920.S
View file @ c84f2c3f
......@@ -29,7 +29,6 @@
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/pgtable.h>
#include <asm/domain.h>
#include <asm/procinfo.h>
#include <asm/hardware.h>
#include <asm/page.h>
......@@ -383,36 +382,27 @@ __arm920_setup:
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
mcr p15, 0, r4, c2, c0 @ load page table pointer
mov r0, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT))
mcr p15, 0, r0, c3, c0 @ load domain access register
mrc p15, 0, r0, c1, c0 @ get control register v4
/*
* Clear out 'unwanted' bits (then put them in if we need them)
*/
@ VI ZFRS BLDP WCAM
bic r0, r0, #0x0e00
bic r0, r0, #0x0002
bic r0, r0, #0x000c
bic r0, r0, #0x1000 @ ...0 000. .... 000.
/*
* Turn on what we want
*/
orr r0, r0, #0x0031
orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1
#ifndef CONFIG_CPU_DCACHE_DISABLE
orr r0, r0, #0x0004 @ .... .... .... .1..
#endif
#ifndef CONFIG_CPU_ICACHE_DISABLE
orr r0, r0, #0x1000 @ ...1 .... .... ....
#endif
ldr r5, arm920_cr1_clear
bic r0, r0, r5
ldr r5, arm920_cr1_set
orr r0, r0, r5
mov pc, lr
.size __arm920_setup, . - __arm920_setup
/*
* R
* .RVI ZFRS BLDP WCAM
* ..11 0001 ..11 0101
*
*/
.type arm920_cr1_clear, #object
.type arm920_cr1_set, #object
arm920_cr1_clear:
.word 0x3f3f
arm920_cr1_set:
.word 0x3135
__INITDATA
/*
......
arch/arm/mm/proc-arm922.S
View file @ c84f2c3f
......@@ -30,7 +30,6 @@
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/pgtable.h>
#include <asm/domain.h>
#include <asm/procinfo.h>
#include <asm/hardware.h>
#include <asm/page.h>
......@@ -387,36 +386,27 @@ __arm922_setup:
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
mcr p15, 0, r4, c2, c0 @ load page table pointer
mov r0, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT))
mcr p15, 0, r0, c3, c0 @ load domain access register
mrc p15, 0, r0, c1, c0 @ get control register v4
/*
* Clear out 'unwanted' bits (then put them in if we need them)
*/
@ VI ZFRS BLDP WCAM
bic r0, r0, #0x0e00
bic r0, r0, #0x0002
bic r0, r0, #0x000c
bic r0, r0, #0x1000 @ ...0 000. .... 000.
/*
* Turn on what we want
*/
orr r0, r0, #0x0031
orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1
#ifndef CONFIG_CPU_DCACHE_DISABLE
orr r0, r0, #0x0004 @ .... .... .... .1..
#endif
#ifndef CONFIG_CPU_ICACHE_DISABLE
orr r0, r0, #0x1000 @ ...1 .... .... ....
#endif
ldr r5, arm922_cr1_clear
bic r0, r0, r5
ldr r5, arm922_cr1_set
orr r0, r0, r5
mov pc, lr
.size __arm922_setup, . - __arm922_setup
/*
* R
* .RVI ZFRS BLDP WCAM
* ..11 0001 ..11 0101
*
*/
.type arm922_cr1_clear, #object
.type arm922_cr1_set, #object
arm922_cr1_clear:
.word 0x3f3f
arm922_cr1_set:
.word 0x3135
__INITDATA
/*
......
arch/arm/mm/proc-arm925.S
View file @ c84f2c3f
......@@ -52,7 +52,6 @@
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/pgtable.h>
#include <asm/domain.h>
#include <asm/procinfo.h>
#include <asm/hardware.h>
#include <asm/page.h>
......@@ -440,48 +439,36 @@ __arm925_setup:
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
mcr p15, 0, r4, c2, c0 @ load page table pointer
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mov r0, #4 @ disable write-back on caches explicitly
mcr p15, 7, r0, c15, c0, 0
#endif
mov r0, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT))
mcr p15, 0, r0, c3, c0 @ load domain access register
mrc p15, 0, r0, c1, c0 @ get control register v4
/*
* Clear out 'unwanted' bits (then put them in if we need them)
*/
@ VI ZFRS BLDP WCAM
bic r0, r0, #0x0e00
bic r0, r0, #0x0002
bic r0, r0, #0x000c
bic r0, r0, #0x1000 @ ...0 000. .... 000.
/*
* Turn on what we want
*/
orr r0, r0, #0x0031
orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1
/* Writebuffer on */
orr r0, r0, #0x0008 @ .... .... .... 1...
ldr r5, arm925_cr1_clear
bic r0, r0, r5
ldr r5, arm925_cr1_set
orr r0, r0, r5
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .1.. .... .... ....
#endif
#ifndef CONFIG_CPU_DCACHE_DISABLE
orr r0, r0, #0x0004 @ .... .... .... .1..
#endif
#ifndef CONFIG_CPU_ICACHE_DISABLE
orr r0, r0, #0x1000 @ ...1 .... .... ....
#endif
mov pc, lr
.size __arm925_setup, . - __arm925_setup
/*
* R
* .RVI ZFRS BLDP WCAM
* .011 0001 ..11 1101
*
*/
.type arm925_cr1_clear, #object
.type arm925_cr1_set, #object
arm925_cr1_clear:
.word 0x7f3f
arm925_cr1_set:
.word 0x313d
__INITDATA
/*
......
arch/arm/mm/proc-arm926.S
View file @ c84f2c3f
......@@ -29,7 +29,6 @@
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/pgtable.h>
#include <asm/domain.h>
#include <asm/procinfo.h>
#include <asm/hardware.h>
#include <asm/page.h>
......@@ -389,7 +388,6 @@ __arm926_setup:
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
mcr p15, 0, r4, c2, c0 @ load page table pointer
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
......@@ -397,38 +395,30 @@ __arm926_setup:
mcr p15, 7, r0, c15, c0, 0
#endif
mov r0, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT))
mcr p15, 0, r0, c3, c0 @ load domain access register
mrc p15, 0, r0, c1, c0 @ get control register v4
/*
* Clear out 'unwanted' bits (then put them in if we need them)
*/
@ VI ZFRS BLDP WCAM
bic r0, r0, #0x0e00
bic r0, r0, #0x0002
bic r0, r0, #0x000c
bic r0, r0, #0x1000 @ ...0 000. .... 000.
/*
* Turn on what we want
*/
orr r0, r0, #0x0031
orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1
ldr r5, arm926_cr1_clear
bic r0, r0, r5
ldr r5, arm926_cr1_set
orr r0, r0, r5
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .1.. .... .... ....
#endif
#ifndef CONFIG_CPU_DCACHE_DISABLE
orr r0, r0, #0x0004 @ .... .... .... .1..
#endif
#ifndef CONFIG_CPU_ICACHE_DISABLE
orr r0, r0, #0x1000 @ ...1 .... .... ....
#endif
mov pc, lr
.size __arm926_setup, . - __arm926_setup
/*
* R
* .RVI ZFRS BLDP WCAM
* .011 0001 ..11 0101
*
*/
.type arm926_cr1_clear, #object
.type arm926_cr1_set, #object
arm926_cr1_clear:
.word 0x7f3f
arm926_cr1_set:
.word 0x3135
__INITDATA
/*
......
arch/arm/mm/proc-sa110.S
View file @ c84f2c3f
......@@ -19,7 +19,6 @@
#include <asm/procinfo.h>
#include <asm/hardware.h>
#include <asm/pgtable.h>
#include <asm/domain.h>
#include <asm/ptrace.h>
/*
......@@ -187,24 +186,31 @@ ENTRY(cpu_sa110_set_pte)
.type __sa110_setup, #function
__sa110_setup:
mrc p15, 0, r0, c1, c0 @ get control register v4
bic r0, r0, #0x2e00 @ ..VI ZFRS BLDP WCAM
bic r0, r0, #0x0002 @ ..0. 000. .... ..0.
orr r0, r0, #0x003d
orr r0, r0, #0x1100 @ ...1 ...1 ..11 11.1
mov r10, #0
mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
mcr p15, 0, r4, c2, c0 @ load page table pointer
mov r10, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT))
mcr p15, 0, r10, c3, c0 @ load domain access register
mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, sa110_cr1_clear
bic r0, r0, r5
ldr r5, sa110_cr1_set
orr r0, r0, r5
mov pc, lr
.size __sa110_setup, . - __sa110_setup
/*
* R
* .RVI ZFRS BLDP WCAM
* ..01 0001 ..11 1101
*
*/
.type sa110_cr1_clear, #object
.type sa110_cr1_set, #object
sa110_cr1_clear:
.word 0x3f3f
sa110_cr1_set:
.word 0x113d
__INITDATA
/*
......
arch/arm/mm/proc-sa1100.S
View file @ c84f2c3f
......@@ -20,7 +20,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/domain.h>
#include <asm/constants.h>
#include <asm/procinfo.h>
#include <asm/hardware.h>
......@@ -210,24 +209,31 @@ ENTRY(cpu_sa1100_set_pte)
.type __sa1100_setup, #function
__sa1100_setup:
mov r10, #0
mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
mov r0, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT))
mcr p15, 0, r0, c3, c0 @ load domain access register
mcr p15, 0, r4, c2, c0 @ load page table pointer
mov r0, #0
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
mrc p15, 0, r0, c1, c0 @ get control register v4
bic r0, r0, #0x0e00 @ ..VI ZFRS BLDP WCAM
bic r0, r0, #0x0002 @ .... 000. .... ..0.
orr r0, r0, #0x003d
orr r0, r0, #0x3100 @ ..11 ...1 ..11 11.1
ldr r5, sa1100_cr1_clear
bic r0, r0, r5
ldr r5, sa1100_cr1_set
orr r0, r0, r5
mov pc, lr
.size __sa1100_setup, . - __sa1100_setup
/*
* R
* .RVI ZFRS BLDP WCAM
* ..11 0001 ..11 1101
*
*/
.type sa1100_cr1_clear, #object
.type sa1100_cr1_set, #object
sa1100_cr1_clear:
.word 0x3f3f
sa1100_cr1_set:
.word 0x313d
__INITDATA
/*
......
arch/arm/mm/proc-v6.S
View file @ c84f2c3f
......@@ -14,7 +14,6 @@
#include <asm/constants.h>
#include <asm/procinfo.h>
#include <asm/pgtable.h>
#include <asm/domain.h>
#include "proc-macros.S"
......@@ -190,30 +189,24 @@ cpu_v6_name:
* - cache type register is implemented
*/
__v6_setup:
mov r10, #0
mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D cache
mcr p15, 0, r10, c7, c5, 0 @ invalidate I cache
mcr p15, 0, r10, c7, c15, 0 @ clean+invalidate cache
mcr p15, 0, r10, c7, c10, 4 @ drain write buffer
mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
mcr p15, 0, r10, c2, c0, 2 @ TTB control register
mcr p15, 0, r4, c2, c0, 0 @ load TTB0
mov r0, #0
mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
mcr p15, 0, r0, c2, c0, 2 @ TTB control register
mcr p15, 0, r4, c2, c0, 1 @ load TTB1
mov r10, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT))
mcr p15, 0, r10, c3, c0, 0 @ load domain access register
mrc p15, 0, r0, c1, c0, 0 @ read control register
#ifdef CONFIG_VFP
mrc p15, 0, r10, c1, c0, 2
orr r10, r10, #(3 << 20)
mcr p15, 0, r10, c1, c0, 2 @ Enable full access to VFP
mrc p15, 0, r0, c1, c0, 2
orr r0, r0, #(3 << 20)
mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP
#endif
ldr r10, cr1_clear @ get mask for bits to clear
bic r0, r0, r10 @ clear bits them
ldr r10, cr1_set @ get mask for bits to set
orr r0, r0, r10 @ set them
mrc p15, 0, r0, c1, c0, 0 @ read control register
ldr r5, v6_cr1_clear @ get mask for bits to clear
bic r0, r0, r5 @ clear bits them
ldr r5, v6_cr1_set @ get mask for bits to set
orr r0, r0, r5 @ set them
mov pc, lr @ return to head.S:__ret
/*
......@@ -222,11 +215,11 @@ __v6_setup:
* rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
* 0 110 0011 1.00 .111 1101 < we want
*/
.type cr1_clear, #object
.type cr1_set, #object
cr1_clear:
.word 0x0120c302
cr1_set:
.type v6_cr1_clear, #object
.type v6_cr1_set, #object
v6_cr1_clear:
.word 0x01e0fb7f
v6_cr1_set:
.word 0x00c0387d
.type v6_processor_functions, #object
......
arch/arm/mm/proc-xscale.S
View file @ c84f2c3f
......@@ -26,7 +26,6 @@
#include <asm/procinfo.h>
#include <asm/hardware.h>
#include <asm/pgtable.h>
#include <asm/domain.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"
......@@ -595,17 +594,9 @@ ENTRY(cpu_xscale_set_pte)
.type __xscale_setup, #function
__xscale_setup:
mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
msr cpsr_c, r0
mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
mov r0, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT))
mcr p15, 0, r0, c3, c0, 0 @ load domain access register
#ifdef CONFIG_IWMMXT
mov r0, #0 @ initially disallow access to CP0/CP1
#else
......@@ -615,13 +606,26 @@ __xscale_setup:
orr r0, r0, #1 << 13 @ Its undefined whether this
mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
mrc p15, 0, r0, c1, c0, 0 @ get control register
bic r0, r0, #0x0200 @ .... ..R. .... ....
bic r0, r0, #0x0002 @ .... .... .... ..A.
orr r0, r0, #0x0005 @ .... .... .... .C.M
orr r0, r0, #0x3900 @ ..VI Z..S .... ....
ldr r5, xscale_cr1_clear
bic r0, r0, r5
ldr r5, xscale_cr1_set
orr r0, r0, r5
mov pc, lr
.size __xscale_setup, . - __xscale_setup
/*
* R
* .RVI ZFRS BLDP WCAM
* ..11 1.01 .... .101
*
*/
.type xscale_cr1_clear, #object
.type xscale_cr1_set, #object
xscale_cr1_clear:
.word 0x3b07
xscale_cr1_set:
.word 0x3905
__INITDATA
/*
......
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