drm/amd/pm: fix MP1 state setting failure in s3 test

Skip PP_MP1_STATE_NONE in MP1 state setting, otherwise, it will
break S3 sequence.

[   50.188269] [drm:amdgpu_device_ip_suspend_phase2 [amdgpu]] *ERROR* SMC failed to set mp1 state 0, -22
[   50.969901] amdgpu 0000:03:00.0: amdgpu: SMU is resuming...
[   50.970024] sd 0:0:0:0: [sda] Starting disk
[   50.979723] serial 00:02: activated
[   51.353644] ata4: SATA link down (SStatus 4 SControl 300)
[   51.353669] ata3: SATA link down (SStatus 4 SControl 300)
[   51.353747] ata6: SATA link down (SStatus 4 SControl 300)
[   51.357694] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[   51.357711] ata5: SATA link down (SStatus 4 SControl 300)
[   51.357729] ata2: SATA link down (SStatus 4 SControl 300)
[   51.358005] ata1.00: supports DRM functions and may not be fully accessible
[   51.360491] ata1.00: supports DRM functions and may not be fully accessible
[   51.362573] ata1.00: configured for UDMA/133
[   51.362610] ahci 0000:00:17.0: port does not support device sleep
[   51.362946] ata1.00: Enabling discard_zeroes_data
[   52.566438] amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state!
[   54.126316] amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state!
[   54.126317] amdgpu 0000:03:00.0: amdgpu: Failed to SetDriverDramAddr!
[   54.126318] amdgpu 0000:03:00.0: amdgpu: Failed to setup smc hw!
[   54.126319] [drm:amdgpu_device_ip_resume_phase2 [amdgpu]] *ERROR* resume of IP block <smu> failed -62
[   54.126398] amdgpu 0000:03:00.0: amdgpu: amdgpu_device_ip_resume failed (-62).
[   54.126399] PM: dpm_run_callback(): pci_pm_resume+0x0/0x90 returns -62
[   54.126403] PM: Device 0000:03:00.0 failed to resume async: error -62

Fixes: 1689fca0 ("drm/amd/pm: fix Navi1x runtime resume failure V2")
Signed-off-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/pm/amdgpu_dpm.c

@@ -1027,6 +1027,9 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,
 	int ret = 0;
 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 
+	if (mp1_state == PP_MP1_STATE_NONE)
+		return 0;
+
 	if (pp_funcs && pp_funcs->set_mp1_state) {
 		ret = pp_funcs->set_mp1_state(
 				adev->powerplay.pp_handle,