drm/amd/include: add bitfield define for EDC registers

Add EDC registers to support VEGA20 RAS Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/include: add bitfield define for EDC registers
Add EDC registers to support VEGA20 RAS Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
ca3f422f · Dennis Li · Alex Deucher · 7cdc2ee3 · ca3f422f
Commit ca3f422f authored Jul 19, 2019 by Dennis Li Committed by Alex Deucher Jul 31, 2019
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drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h +157 -0

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--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h