Commit ca691f71 authored by Doug Anderson's avatar Doug Anderson Committed by Lee Jones

mfd: cros ec: spi: Increase wait time to 200ms

This is a sucky change to bump up the time we'll wait for the EC.  Why
is it sucky?  If 200ms for a transfer is a common thing it will have a
massively bad impact on keyboard responsiveness.

It still seems like a good idea to do this, though, because we have a
gas gauge that claims that in an extreme case it could stretch the i2c
clock for 144ms.  It's not a common case so it shouldn't affect
responsiveness, but it can happen.  It's much better to have a single
slow keyboard response than to start returning errors when we don't
have to.

In newer EC designs we should probably implement a virtual battery to
respond to the kernel to insulate the kernel from these types of
issues.
Signed-off-by: default avatarDoug Anderson <dianders@chromium.org>
Signed-off-by: default avatarEnric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: default avatarLee Jones <lee.jones@linaro.org>
parent d5aa11bf
...@@ -45,8 +45,11 @@ ...@@ -45,8 +45,11 @@
* on the other end and need to transfer ~256 bytes, then we need: * on the other end and need to transfer ~256 bytes, then we need:
* 10 us/bit * ~10 bits/byte * ~256 bytes = ~25ms * 10 us/bit * ~10 bits/byte * ~256 bytes = ~25ms
* *
* We'll wait 4 times that to handle clock stretching and other * We'll wait 8 times that to handle clock stretching and other
* paranoia. * paranoia. Note that some battery gas gauge ICs claim to have a
* clock stretch of 144ms in rare situations. That's incentive for
* not directly passing i2c through, but it's too late for that for
* existing hardware.
* *
* It's pretty unlikely that we'll really see a 249 byte tunnel in * It's pretty unlikely that we'll really see a 249 byte tunnel in
* anything other than testing. If this was more common we might * anything other than testing. If this was more common we might
...@@ -54,7 +57,7 @@ ...@@ -54,7 +57,7 @@
* wait loop. The 'flash write' command would be another candidate * wait loop. The 'flash write' command would be another candidate
* for this, clocking in at 2-3ms. * for this, clocking in at 2-3ms.
*/ */
#define EC_MSG_DEADLINE_MS 100 #define EC_MSG_DEADLINE_MS 200
/* /*
* Time between raising the SPI chip select (for the end of a * Time between raising the SPI chip select (for the end of a
......
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