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Commit ca8e8a18 authored by Lucas Tanure's avatar Lucas Tanure Committed by Mark Brown
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spi: amd: Refactor code to use less spi_master_get_devdata 

Get master data in the start and then just use struct amd_spi
as it has the needed variable
Signed-off-by: default avatarLucas Tanure <tanureal@opensource.cirrus.com>
Reviewed-by: default avatarCharles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20210910111529.12539-1-tanureal@opensource.cirrus.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent becbca18
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Showing with 34 additions and 60 deletions
drivers/spi/spi-amd.c
View file @ ca8e8a18
...@@ -41,85 +41,66 @@ struct amd_spi { ...@@ -41,85 +41,66 @@ struct amd_spi {
u8 chip_select; u8 chip_select;
}; };
static inline u8 amd_spi_readreg8(struct spi_master *master, int idx) static inline u8 amd_spi_readreg8(struct amd_spi *amd_spi, int idx)
{ {
struct amd_spi *amd_spi = spi_master_get_devdata(master);
return ioread8((u8 __iomem *)amd_spi->io_remap_addr + idx); return ioread8((u8 __iomem *)amd_spi->io_remap_addr + idx);
} }
static inline void amd_spi_writereg8(struct spi_master *master, int idx, static inline void amd_spi_writereg8(struct amd_spi *amd_spi, int idx, u8 val)
u8 val)
{ {
struct amd_spi *amd_spi = spi_master_get_devdata(master);
iowrite8(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx)); iowrite8(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
} }
static inline void amd_spi_setclear_reg8(struct spi_master *master, int idx, static void amd_spi_setclear_reg8(struct amd_spi *amd_spi, int idx, u8 set, u8 clear)
u8 set, u8 clear)
{ {
u8 tmp = amd_spi_readreg8(master, idx); u8 tmp = amd_spi_readreg8(amd_spi, idx);
tmp = (tmp & ~clear) | set; tmp = (tmp & ~clear) | set;
amd_spi_writereg8(master, idx, tmp); amd_spi_writereg8(amd_spi, idx, tmp);
} }
static inline u32 amd_spi_readreg32(struct spi_master *master, int idx) static inline u32 amd_spi_readreg32(struct amd_spi *amd_spi, int idx)
{ {
struct amd_spi *amd_spi = spi_master_get_devdata(master);
return ioread32((u8 __iomem *)amd_spi->io_remap_addr + idx); return ioread32((u8 __iomem *)amd_spi->io_remap_addr + idx);
} }
static inline void amd_spi_writereg32(struct spi_master *master, int idx, static inline void amd_spi_writereg32(struct amd_spi *amd_spi, int idx, u32 val)
u32 val)
{ {
struct amd_spi *amd_spi = spi_master_get_devdata(master);
iowrite32(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx)); iowrite32(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
} }
static inline void amd_spi_setclear_reg32(struct spi_master *master, int idx, static inline void amd_spi_setclear_reg32(struct amd_spi *amd_spi, int idx, u32 set, u32 clear)
u32 set, u32 clear)
{ {
u32 tmp = amd_spi_readreg32(master, idx); u32 tmp = amd_spi_readreg32(amd_spi, idx);
tmp = (tmp & ~clear) | set; tmp = (tmp & ~clear) | set;
amd_spi_writereg32(master, idx, tmp); amd_spi_writereg32(amd_spi, idx, tmp);
} }
static void amd_spi_select_chip(struct spi_master *master) static void amd_spi_select_chip(struct amd_spi *amd_spi)
{ {
struct amd_spi *amd_spi = spi_master_get_devdata(master); amd_spi_setclear_reg8(amd_spi, AMD_SPI_ALT_CS_REG, amd_spi->chip_select,
u8 chip_select = amd_spi->chip_select;
amd_spi_setclear_reg8(master, AMD_SPI_ALT_CS_REG, chip_select,
AMD_SPI_ALT_CS_MASK); AMD_SPI_ALT_CS_MASK);
} }
static void amd_spi_clear_fifo_ptr(struct spi_master *master) static void amd_spi_clear_fifo_ptr(struct amd_spi *amd_spi)
{ {
amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, AMD_SPI_FIFO_CLEAR);
AMD_SPI_FIFO_CLEAR);
} }
static void amd_spi_set_opcode(struct spi_master *master, u8 cmd_opcode) static void amd_spi_set_opcode(struct amd_spi *amd_spi, u8 cmd_opcode)
{ {
amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, cmd_opcode, amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, cmd_opcode, AMD_SPI_OPCODE_MASK);
AMD_SPI_OPCODE_MASK);
} }
static inline void amd_spi_set_rx_count(struct spi_master *master, static inline void amd_spi_set_rx_count(struct amd_spi *amd_spi, u8 rx_count)
u8 rx_count)
{ {
amd_spi_setclear_reg8(master, AMD_SPI_RX_COUNT_REG, rx_count, 0xff); amd_spi_setclear_reg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count, 0xff);
} }
static inline void amd_spi_set_tx_count(struct spi_master *master, static inline void amd_spi_set_tx_count(struct amd_spi *amd_spi, u8 tx_count)
u8 tx_count)
{ {
amd_spi_setclear_reg8(master, AMD_SPI_TX_COUNT_REG, tx_count, 0xff); amd_spi_setclear_reg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count, 0xff);
} }
static inline int amd_spi_busy_wait(struct amd_spi *amd_spi) static inline int amd_spi_busy_wait(struct amd_spi *amd_spi)
...@@ -142,22 +123,18 @@ static inline int amd_spi_busy_wait(struct amd_spi *amd_spi) ...@@ -142,22 +123,18 @@ static inline int amd_spi_busy_wait(struct amd_spi *amd_spi)
return 0; return 0;
} }
static void amd_spi_execute_opcode(struct spi_master *master) static void amd_spi_execute_opcode(struct amd_spi *amd_spi)
{ {
struct amd_spi *amd_spi = spi_master_get_devdata(master);
/* Set ExecuteOpCode bit in the CTRL0 register */ /* Set ExecuteOpCode bit in the CTRL0 register */
amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD, amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD, AMD_SPI_EXEC_CMD);
AMD_SPI_EXEC_CMD);
amd_spi_busy_wait(amd_spi); amd_spi_busy_wait(amd_spi);
} }
static int amd_spi_master_setup(struct spi_device *spi) static int amd_spi_master_setup(struct spi_device *spi)
{ {
struct spi_master *master = spi->master; struct amd_spi *amd_spi = spi_master_get_devdata(spi->master);
amd_spi_clear_fifo_ptr(master); amd_spi_clear_fifo_ptr(amd_spi);
return 0; return 0;
} }
...@@ -185,19 +162,18 @@ static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi, ...@@ -185,19 +162,18 @@ static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi,
tx_len = xfer->len - 1; tx_len = xfer->len - 1;
cmd_opcode = *(u8 *)xfer->tx_buf; cmd_opcode = *(u8 *)xfer->tx_buf;
buf++; buf++;
amd_spi_set_opcode(master, cmd_opcode); amd_spi_set_opcode(amd_spi, cmd_opcode);
/* Write data into the FIFO. */ /* Write data into the FIFO. */
for (i = 0; i < tx_len; i++) { for (i = 0; i < tx_len; i++) {
iowrite8(buf[i], iowrite8(buf[i], ((u8 __iomem *)amd_spi->io_remap_addr +
((u8 __iomem *)amd_spi->io_remap_addr +
AMD_SPI_FIFO_BASE + i)); AMD_SPI_FIFO_BASE + i));
} }
amd_spi_set_tx_count(master, tx_len); amd_spi_set_tx_count(amd_spi, tx_len);
amd_spi_clear_fifo_ptr(master); amd_spi_clear_fifo_ptr(amd_spi);
/* Execute command */ /* Execute command */
amd_spi_execute_opcode(master); amd_spi_execute_opcode(amd_spi);
} }
if (m_cmd & AMD_SPI_XFER_RX) { if (m_cmd & AMD_SPI_XFER_RX) {
/* /*
...@@ -206,15 +182,13 @@ static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi, ...@@ -206,15 +182,13 @@ static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi,
*/ */
rx_len = xfer->len; rx_len = xfer->len;
buf = (u8 *)xfer->rx_buf; buf = (u8 *)xfer->rx_buf;
amd_spi_set_rx_count(master, rx_len); amd_spi_set_rx_count(amd_spi, rx_len);
amd_spi_clear_fifo_ptr(master); amd_spi_clear_fifo_ptr(amd_spi);
/* Execute command */ /* Execute command */
amd_spi_execute_opcode(master); amd_spi_execute_opcode(amd_spi);
/* Read data from FIFO to receive buffer */ /* Read data from FIFO to receive buffer */
for (i = 0; i < rx_len; i++) for (i = 0; i < rx_len; i++)
buf[i] = amd_spi_readreg8(master, buf[i] = amd_spi_readreg8(amd_spi, AMD_SPI_FIFO_BASE + tx_len + i);
AMD_SPI_FIFO_BASE +
tx_len + i);
} }
} }
...@@ -234,7 +208,7 @@ static int amd_spi_master_transfer(struct spi_master *master, ...@@ -234,7 +208,7 @@ static int amd_spi_master_transfer(struct spi_master *master,
struct spi_device *spi = msg->spi; struct spi_device *spi = msg->spi;
amd_spi->chip_select = spi->chip_select; amd_spi->chip_select = spi->chip_select;
amd_spi_select_chip(master); amd_spi_select_chip(amd_spi);
/* /*
* Extract spi_transfers from the spi message and * Extract spi_transfers from the spi message and
......
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