drm/amdgpu: add CSDMA reg offsets for NBIO v7.7.0

This patch will add CSDMA reg offsets for NBIO v7.7.0
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_offset.h

@@ -4005,6 +4005,8 @@
 #define regGDC0_BIF_VCN0_DOORBELL_RANGE_BASE_IDX                                                        3
 #define regGDC0_BIF_RLC_DOORBELL_RANGE                                                                  0x4f0af5
 #define regGDC0_BIF_RLC_DOORBELL_RANGE_BASE_IDX                                                         3
+#define regGDC0_BIF_CSDMA_DOORBELL_RANGE                                                                0x4f0afb
+#define regGDC0_BIF_CSDMA_DOORBELL_RANGE_BASE_IDX                                                       3
 #define regGDC0_ATDMA_MISC_CNTL                                                                         0x4f0afd
 #define regGDC0_ATDMA_MISC_CNTL_BASE_IDX                                                                3
 #define regGDC0_BIF_DOORBELL_FENCE_CNTL                                                                 0x4f0afe
@@ -21535,6 +21537,8 @@
 #define regGDC1_BIF_SDMA4_DOORBELL_RANGE_BASE_IDX                                                       5
 #define regGDC1_BIF_SDMA5_DOORBELL_RANGE                                                                0x2ffc0efa
 #define regGDC1_BIF_SDMA5_DOORBELL_RANGE_BASE_IDX                                                       5
+#define regGDC1_BIF_CSDMA_DOORBELL_RANGE                                                                0x2ffc0efb
+#define regGDC1_BIF_CSDMA_DOORBELL_RANGE_BASE_IDX                                                       5
 #define regGDC1_ATDMA_MISC_CNTL                                                                         0x2ffc0efd
 #define regGDC1_ATDMA_MISC_CNTL_BASE_IDX                                                                5
 #define regGDC1_BIF_DOORBELL_FENCE_CNTL                                                                 0x2ffc0efe

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_sh_mask.h

@@ -31641,6 +31641,11 @@
 #define GDC0_BIF_RLC_DOORBELL_RANGE__SIZE__SHIFT                                                              0x10
 #define GDC0_BIF_RLC_DOORBELL_RANGE__OFFSET_MASK                                                              0x00000FFCL
 #define GDC0_BIF_RLC_DOORBELL_RANGE__SIZE_MASK                                                                0x001F0000L
+//GDC0_BIF_CSDMA_DOORBELL_RANGE
+#define GDC0_BIF_CSDMA_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
+#define GDC0_BIF_CSDMA_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
+#define GDC0_BIF_CSDMA_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
+#define GDC0_BIF_CSDMA_DOORBELL_RANGE__SIZE_MASK                                                              0x00FF0000L
 //GDC0_ATDMA_MISC_CNTL
 #define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT                                                             0x0
 #define GDC0_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN__SHIFT                                 0x1
@@ -119765,6 +119770,11 @@
 #define GDC1_BIF_SDMA5_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
 #define GDC1_BIF_SDMA5_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
 #define GDC1_BIF_SDMA5_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
+//GDC1_BIF_CSDMA_DOORBELL_RANGE
+#define GDC1_BIF_CSDMA_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
+#define GDC1_BIF_CSDMA_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
+#define GDC1_BIF_CSDMA_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
+#define GDC1_BIF_CSDMA_DOORBELL_RANGE__SIZE_MASK                                                              0x00FF0000L
 //GDC1_ATDMA_MISC_CNTL
 #define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT                                                             0x0
 #define GDC1_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN__SHIFT                                 0x1