Commit cb562edd authored by Peng Fan's avatar Peng Fan Committed by Shawn Guo

arm64: dts: imx8mm-prt8mm: update pinctrl to match dtschema

The dtschema requires 'grp' in the end, so update the name
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 4629e559
...@@ -264,7 +264,7 @@ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 ...@@ -264,7 +264,7 @@ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>; >;
}; };
pinctrl_usdhc3_100mhz: usdhc3grp100mhz { pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = < fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
...@@ -280,7 +280,7 @@ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 ...@@ -280,7 +280,7 @@ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>; >;
}; };
pinctrl_usdhc3_200mhz: usdhc3grp200mhz { pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = < fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
......
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