Commit cb8bcc98 authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu/display: fix build without CONFIG_DRM_AMD_DC_DCN3_0

Need to guard some new DCN3.0 stuff.
Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f0bfa78b
...@@ -288,13 +288,16 @@ void optc1_program_timing( ...@@ -288,13 +288,16 @@ void optc1_program_timing(
if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2) if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2)
h_div = H_TIMING_DIV_BY2; h_div = H_TIMING_DIV_BY2;
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) { if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) {
if (optc1->opp_count == 4) if (optc1->opp_count == 4)
h_div = H_TIMING_DIV_BY4; h_div = H_TIMING_DIV_BY4;
REG_UPDATE(OTG_H_TIMING_CNTL, REG_UPDATE(OTG_H_TIMING_CNTL,
OTG_H_TIMING_DIV_MODE, h_div); OTG_H_TIMING_DIV_MODE, h_div);
} else { } else
#endif
{
REG_UPDATE(OTG_H_TIMING_CNTL, REG_UPDATE(OTG_H_TIMING_CNTL,
OTG_H_TIMING_DIV_BY2, h_div); OTG_H_TIMING_DIV_BY2, h_div);
} }
......
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