drm/amd/display: add mode support check to dml vba code

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h

@@ -26,7 +26,7 @@
 #define __DISPLAY_MODE_ENUMS_H__
 
 enum output_encoder_class {
-	dm_dp = 0, dm_hdmi = 1, dm_wb = 2
+	dm_dp = 0, dm_hdmi = 1, dm_wb = 2, dm_edp
 };
 enum output_format_class {
 	dm_444 = 0, dm_420 = 1, dm_n422, dm_s422
@@ -39,7 +39,9 @@ enum source_format_class {
 	dm_420_10 = 4,
 	dm_422_8 = 5,
 	dm_422_10 = 6,
-	dm_444_8 = 7
+	dm_444_8 = 7,
+	dm_mono_8,
+	dm_mono_16
 };
 enum output_bpc_class {
 	dm_out_6 = 0, dm_out_8 = 1, dm_out_10 = 2, dm_out_12 = 3, dm_out_16 = 4
@@ -79,7 +81,9 @@ enum dm_swizzle_mode {
 	dm_sw_SPARE_15 = 28,
 	dm_sw_var_s_x = 29,
 	dm_sw_var_d_x = 30,
-	dm_sw_64kb_r_x
+	dm_sw_64kb_r_x,
+	dm_sw_gfx7_2d_thin_lvp,
+	dm_sw_gfx7_2d_thin_gl
 };
 enum lb_depth {
 	dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16

drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h

@@ -66,6 +66,7 @@ struct _vcs_dpi_mode_evaluation_st {
 
 struct _vcs_dpi_voltage_scaling_st {
 	int state;
+	double dscclk_mhz;
 	double dcfclk_mhz;
 	double socclk_mhz;
 	double dram_speed_mhz;
@@ -131,6 +132,9 @@ struct	_vcs_dpi_ip_params_st	{
 	unsigned int	writeback_chroma_line_buffer_width_pixels;
 	unsigned int	max_page_table_levels;
 	unsigned int	max_num_dpp;
+	unsigned int	max_num_otg;
+	unsigned int	cursor_chunk_size;
+	unsigned int	cursor_buffer_size;
 	unsigned int	max_num_wb;
 	unsigned int	max_dchub_pscl_bw_pix_per_clk;
 	unsigned int	max_pscl_lb_bw_pix_per_clk;
@@ -224,6 +228,7 @@ struct writeback_st {
 };
 
 struct	_vcs_dpi_display_output_params_st	{
+	int	dp_lanes;
 	int	output_bpp;
 	int	dsc_enable;
 	int	wb_enable;

drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c

@@ -35,6 +35,18 @@ double dml_max(double a, double b)
 {
 	return (double) dcn_bw_max2(a, b);
 }
+double dml_max3(double a, double b, double c)
+{
+	return dml_max(dml_max(a, b), c);
+}
+double dml_max4(double a, double b, double c, double d)
+{
+	return dml_max(dml_max(a, b), dml_max(c, d));
+}
+double dml_max5(double a, double b, double c, double d, double e)
+{
+	return dml_max(dml_max4(a, b, c, d), e);
+}
 
 double dml_ceil(double a, double granularity)
 {

drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h

@@ -36,6 +36,9 @@
 
 double dml_min(double a, double b);
 double dml_max(double a, double b);
+double dml_max3(double a, double b, double c);
+double dml_max4(double a, double b, double c, double d);
+double dml_max5(double a, double b, double c, double d, double e);
 bool dml_util_is_420(enum source_format_class sorce_format);
 double dml_ceil_ex(double x, double granularity);
 double dml_floor_ex(double x, double granularity);