Commit cc60f887 authored by Simon Guinot's avatar Simon Guinot Committed by Dan Williams

dmaengine: fix interrupt clearing for mv_xor

When using simultaneously the two DMA channels on a same engine, some
transfers are never completed. For example, an endless lock can occur
while writing heavily on a RAID5 array (with async-tx offload support
enabled).

Note that this issue can also be reproduced by using the DMA test
client.

On a same engine, the interrupt cause register is shared between two
DMA channels. This patch make sure that the cause bit is only cleared
for the requested channel.
Signed-off-by: default avatarSimon Guinot <sguinot@lacie.com>
Tested-by: default avatarLuc Saillard <luc@saillard.org>
Acked-by: default avatarsaeed bishara <saeed.bishara@gmail.com>
Cc: <stable@kernel.org>
Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent d3f3cf85
...@@ -162,7 +162,7 @@ static int mv_is_err_intr(u32 intr_cause) ...@@ -162,7 +162,7 @@ static int mv_is_err_intr(u32 intr_cause)
static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan) static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan)
{ {
u32 val = (1 << (1 + (chan->idx * 16))); u32 val = ~(1 << (chan->idx * 16));
dev_dbg(chan->device->common.dev, "%s, val 0x%08x\n", __func__, val); dev_dbg(chan->device->common.dev, "%s, val 0x%08x\n", __func__, val);
__raw_writel(val, XOR_INTR_CAUSE(chan)); __raw_writel(val, XOR_INTR_CAUSE(chan));
} }
......
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