Commit ccaf725a authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by David S. Miller

ftgmac100: Fix potential ordering issue in NAPI poll

We need to ensure the loads from the descriptor are done after the
MMIO store clearing the interrupts has completed, otherwise we
might still miss work.

A read back from the MMIO register will "push" the posted store and
ioread32 has a barrier on weakly aordered architectures that will
order subsequent accesses.
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 33de6932
...@@ -1349,6 +1349,13 @@ static int ftgmac100_poll(struct napi_struct *napi, int budget) ...@@ -1349,6 +1349,13 @@ static int ftgmac100_poll(struct napi_struct *napi, int budget)
*/ */
iowrite32(FTGMAC100_INT_RXTX, iowrite32(FTGMAC100_INT_RXTX,
priv->base + FTGMAC100_OFFSET_ISR); priv->base + FTGMAC100_OFFSET_ISR);
/* Push the above (and provides a barrier vs. subsequent
* reads of the descriptor).
*/
ioread32(priv->base + FTGMAC100_OFFSET_ISR);
/* Check RX and TX descriptors for more work to do */
if (ftgmac100_check_rx(priv) || if (ftgmac100_check_rx(priv) ||
ftgmac100_tx_buf_cleanable(priv)) ftgmac100_tx_buf_cleanable(priv))
return budget; return budget;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment