Commit cd58a174 authored by Andrey Smirnov's avatar Andrey Smirnov Committed by Shawn Guo

ARM: dts: imx6: rdu2: Disable WP for USDHC2 and USDHC3

RDU2 production units come with resistor connecting WP pin to
correpsonding GPIO DNPed for both SD card slots. Drop any WP related
configuration and mark both slots with "disable-wp".
Reported-by: default avatarChris Healy <cphealy@gmail.com>
Reviewed-by: default avatarChris Healy <cphealy@gmail.com>
Reviewed-by: default avatarLucas Stach <l.stach@pengutronix.de>
Signed-off-by: default avatarAndrey Smirnov <andrew.smirnov@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent f3042a86
...@@ -660,7 +660,7 @@ &usdhc2 { ...@@ -660,7 +660,7 @@ &usdhc2 {
pinctrl-0 = <&pinctrl_usdhc2>; pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>; bus-width = <4>;
cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; disable-wp;
vmmc-supply = <&reg_3p3v_sd>; vmmc-supply = <&reg_3p3v_sd>;
vqmmc-supply = <&reg_3p3v>; vqmmc-supply = <&reg_3p3v>;
no-1-8-v; no-1-8-v;
...@@ -673,7 +673,7 @@ &usdhc3 { ...@@ -673,7 +673,7 @@ &usdhc3 {
pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <4>; bus-width = <4>;
cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; disable-wp;
vmmc-supply = <&reg_3p3v_sd>; vmmc-supply = <&reg_3p3v_sd>;
vqmmc-supply = <&reg_3p3v>; vqmmc-supply = <&reg_3p3v>;
no-1-8-v; no-1-8-v;
...@@ -1097,7 +1097,6 @@ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 ...@@ -1097,7 +1097,6 @@ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x40010040
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x40010040 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x40010040
>; >;
}; };
...@@ -1110,7 +1109,6 @@ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 ...@@ -1110,7 +1109,6 @@ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x40010040
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x40010040 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x40010040
>; >;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment