Commit cd594a3b authored by Robin Farine's avatar Robin Farine Committed by Russell King

[ARM PATCH] 1879/1: fix a few xscale "drain write & fill buffer" instructions

Patch from Robin Farine

Fix the xscale cache handling routines that were invalidating a D 
cache line instead of draining the write & fill buffer as intended.
parent 6ef8f0dc
...@@ -298,7 +298,7 @@ ENTRY(xscale_dma_inv_range) ...@@ -298,7 +298,7 @@ ENTRY(xscale_dma_inv_range)
add r0, r0, #CACHELINESIZE add r0, r0, #CACHELINESIZE
cmp r0, r1 cmp r0, r1
blo 1b blo 1b
mcr p15, 0, r0, c7, c10, 1 @ Drain Write (& Fill) Buffer mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
mov pc, lr mov pc, lr
/* /*
...@@ -315,7 +315,7 @@ ENTRY(xscale_dma_clean_range) ...@@ -315,7 +315,7 @@ ENTRY(xscale_dma_clean_range)
add r0, r0, #CACHELINESIZE add r0, r0, #CACHELINESIZE
cmp r0, r1 cmp r0, r1
blo 1b blo 1b
mcr p15, 0, r0, c7, c10, 1 @ Drain Write (& Fill) Buffer mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
mov pc, lr mov pc, lr
/* /*
...@@ -333,7 +333,7 @@ ENTRY(xscale_dma_flush_range) ...@@ -333,7 +333,7 @@ ENTRY(xscale_dma_flush_range)
add r0, r0, #CACHELINESIZE add r0, r0, #CACHELINESIZE
cmp r0, r1 cmp r0, r1
blo 1b blo 1b
mcr p15, 0, r0, c7, c10, 1 @ Drain Write (& Fill) Buffer mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
mov pc, lr mov pc, lr
ENTRY(xscale_cache_fns) ENTRY(xscale_cache_fns)
......
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