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Commit cdd854bc authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc 

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (79 commits)
  powerpc/8xx: Add support for the MPC8xx based boards from TQC
  powerpc/85xx: Introduce support for the Freescale P1022DS reference board
  powerpc/85xx: Adding DTS for the STx GP3-SSA MPC8555 board
  powerpc/85xx: Change deprecated binding for 85xx-based boards
  powerpc/tqm85xx: add a quirk for ti1520 PCMCIA bridge
  powerpc/tqm85xx: update PCI interrupt-map attribute
  powerpc/mpc8308rdb: support for MPC8308RDB board from Freescale
  powerpc/fsl_pci: add quirk for mpc8308 pcie bridge
  powerpc/85xx: Cleanup QE initialization for MPC85xxMDS boards
  powerpc/85xx: Fix booting for P1021MDS boards
  powerpc/85xx: Fix SWIOTLB initalization for MPC85xxMDS boards
  powerpc/85xx: kexec for SMP 85xx BookE systems
  powerpc/5200/i2c: improve i2c bus error recovery
  of/xilinxfb: update tft compatible versions
  powerpc/fsl-diu-fb: Support setting display mode using EDID
  powerpc/5121: doc/dts-bindings: update doc of FSL DIU bindings
  powerpc/5121: shared DIU framebuffer support
  powerpc/5121: move fsl-diu-fb.h to include/linux
  powerpc/5121: fsl-diu-fb: fix issue with re-enabling DIU area descriptor
  powerpc/512x: add clock structure for Video-IN (VIU) unit
  ...
parents bbc4fd12 42a0ae22
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Documentation/powerpc/dts-bindings/fsl/diu.txt
View file @ cdd854bc
......@@ -4,10 +4,17 @@ The Freescale DIU is a LCD controller, with proper hardware, it can also
drive DVI monitors.
Required properties:
- compatible : should be "fsl-diu".
- compatible : should be "fsl,diu" or "fsl,mpc5121-diu".
- reg : should contain at least address and length of the DIU register
set.
- Interrupts : one DIU interrupt should be describe here.
- interrupts : one DIU interrupt should be described here.
- interrupt-parent : the phandle for the interrupt controller that
services interrupts for this device.
Optional properties:
- edid : verbatim EDID data block describing attached display.
Data from the detailed timing descriptor will be used to
program the display controller.
Example (MPC8610HPCD):
display@2c000 {
......@@ -16,3 +23,12 @@ Example (MPC8610HPCD):
interrupts = <72 2>;
interrupt-parent = <&mpic>;
};
Example for MPC5121:
display@2100 {
compatible = "fsl,mpc5121-diu";
reg = <0x2100 0x100>;
interrupts = <64 0x8>;
interrupt-parent = <&ipic>;
edid = [edid-data];
};
Documentation/powerpc/dts-bindings/fsl/i2c.txt
View file @ cdd854bc
......@@ -20,6 +20,7 @@ Recommended properties :
- fsl,preserve-clocking : boolean; if defined, the clock settings
from the bootloader are preserved (not touched).
- clock-frequency : desired I2C bus clock frequency in Hz.
- fsl,timeout : I2C bus timeout in microseconds.
Examples :
......@@ -59,4 +60,5 @@ Examples :
interrupts = <43 2>;
interrupt-parent = <&mpic>;
clock-frequency = <400000>;
fsl,timeout = <10000>;
};
arch/powerpc/Kconfig
View file @ cdd854bc
......@@ -141,6 +141,7 @@ config PPC
select GENERIC_ATOMIC64 if PPC32
select HAVE_PERF_EVENTS
select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64
config EARLY_PRINTK
bool
......@@ -218,7 +219,7 @@ config ARCH_HIBERNATION_POSSIBLE
config ARCH_SUSPEND_POSSIBLE
def_bool y
depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \
PPC_85xx || PPC_86xx
PPC_85xx || PPC_86xx || PPC_PSERIES
config PPC_DCR_NATIVE
bool
......@@ -351,7 +352,7 @@ config ARCH_ENABLE_MEMORY_HOTREMOVE
config KEXEC
bool "kexec system call (EXPERIMENTAL)"
depends on (PPC_BOOK3S || (FSL_BOOKE && !SMP)) && EXPERIMENTAL
depends on (PPC_BOOK3S || FSL_BOOKE) && EXPERIMENTAL
help
kexec is a system call that implements the ability to shutdown your
current kernel, and to start another kernel. It is like a reboot
......@@ -368,8 +369,8 @@ config KEXEC
config CRASH_DUMP
bool "Build a kdump crash kernel"
depends on PPC64 || 6xx
select RELOCATABLE if PPC64
depends on PPC64 || 6xx || FSL_BOOKE
select RELOCATABLE if PPC64 || FSL_BOOKE
help
Build a kernel suitable for use as a kdump capture kernel.
The same kernel binary can be used as production kernel and dump
......@@ -668,7 +669,7 @@ config NEED_SG_DMA_LENGTH
config GENERIC_ISA_DMA
bool
depends on PPC64 || POWER4 || 6xx && !CPM2
depends on ISA_DMA_API
default y
config PPC_INDIRECT_PCI
......@@ -897,7 +898,7 @@ config KERNEL_START_BOOL
config KERNEL_START
hex "Virtual address of kernel base" if KERNEL_START_BOOL
default PAGE_OFFSET if PAGE_OFFSET_BOOL
default "0xc2000000" if CRASH_DUMP
default "0xc2000000" if CRASH_DUMP && !RELOCATABLE
default "0xc0000000"
config PHYSICAL_START_BOOL
......@@ -910,7 +911,7 @@ config PHYSICAL_START_BOOL
config PHYSICAL_START
hex "Physical address where the kernel is loaded" if PHYSICAL_START_BOOL
default "0x02000000" if PPC_STD_MMU && CRASH_DUMP
default "0x02000000" if PPC_STD_MMU && CRASH_DUMP && !RELOCATABLE
default "0x00000000"
config PHYSICAL_ALIGN
......
arch/powerpc/boot/dts/canyonlands.dts
View file @ cdd854bc
......@@ -270,7 +270,7 @@ UART2: serial@ef600500 {
clock-frequency = <0>; /* Filled in by U-Boot */
current-speed = <0>; /* Filled in by U-Boot */
interrupt-parent = <&UIC1>;
interrupts = <0x1d 0x4>;
interrupts = <28 0x4>;
};
UART3: serial@ef600600 {
......@@ -281,7 +281,7 @@ UART3: serial@ef600600 {
clock-frequency = <0>; /* Filled in by U-Boot */
current-speed = <0>; /* Filled in by U-Boot */
interrupt-parent = <&UIC1>;
interrupts = <0x1e 0x4>;
interrupts = <29 0x4>;
};
IIC0: i2c@ef600700 {
......
arch/powerpc/boot/dts/glacier.dts
View file @ cdd854bc
......@@ -259,7 +259,7 @@ UART2: serial@ef600500 {
clock-frequency = <0>; /* Filled in by U-Boot */
current-speed = <0>; /* Filled in by U-Boot */
interrupt-parent = <&UIC1>;
interrupts = <0x1d 0x4>;
interrupts = <28 0x4>;
};
UART3: serial@ef600600 {
......@@ -270,7 +270,7 @@ UART3: serial@ef600600 {
clock-frequency = <0>; /* Filled in by U-Boot */
current-speed = <0>; /* Filled in by U-Boot */
interrupt-parent = <&UIC1>;
interrupts = <0x1e 0x4>;
interrupts = <29 0x4>;
};
IIC0: i2c@ef600700 {
......
arch/powerpc/boot/dts/mpc8308rdb.dts 0 → 100644
View file @ cdd854bc
/*
* MPC8308RDB Device Tree Source
*
* Copyright 2009 Freescale Semiconductor Inc.
* Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
compatible = "fsl,mpc8308rdb";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8308@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <16384>;
i-cache-size = <16384>;
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>; // 128MB at 0
};
localbus@e0005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
reg = <0xe0005000 0x1000>;
interrupts = <77 0x8>;
interrupt-parent = <&ipic>;
// CS0 and CS1 are swapped when
// booting from nand, but the
// addresses are the same.
ranges = <0x0 0x0 0xfe000000 0x00800000
0x1 0x0 0xe0600000 0x00002000
0x2 0x0 0xf0000000 0x00020000
0x3 0x0 0xfa000000 0x00008000>;
flash@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x800000>;
bank-width = <2>;
device-width = <1>;
u-boot@0 {
reg = <0x0 0x60000>;
read-only;
};
env@60000 {
reg = <0x60000 0x10000>;
};
env1@70000 {
reg = <0x70000 0x10000>;
};
kernel@80000 {
reg = <0x80000 0x200000>;
};
dtb@280000 {
reg = <0x280000 0x10000>;
};
ramdisk@290000 {
reg = <0x290000 0x570000>;
};
};
nand@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8315-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <0x1 0x0 0x2000>;
jffs2@0 {
reg = <0x0 0x2000000>;
};
};
};
immr@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8315-immr", "simple-bus";
ranges = <0 0xe0000000 0x00100000>;
reg = <0xe0000000 0x00000200>;
bus-frequency = <0>;
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <14 0x8>;
interrupt-parent = <&ipic>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
usb@23000 {
compatible = "fsl-usb2-dr";
reg = <0x23000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&ipic>;
interrupts = <38 0x8>;
dr_mode = "peripheral";
phy_type = "ulpi";
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x24000 0x1000>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <32 0x8 33 0x8 34 0x8>;
interrupt-parent = <&ipic>;
tbi-handle = < &tbi0 >;
phy-handle = < &phy2 >;
fsl,magic-packet;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy2: ethernet-phy@2 {
interrupt-parent = <&ipic>;
interrupts = <17 0x8>;
reg = <0x2>;
device_type = "ethernet-phy";
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 0x8 36 0x8 37 0x8>;
interrupt-parent = <&ipic>;
tbi-handle = < &tbi1 >;
/* Vitesse 7385 isn't on the MDIO bus */
fixed-link = <1 1 1000 0 0>;
fsl,magic-packet;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <133333333>;
interrupts = <9 0x8>;
interrupt-parent = <&ipic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <133333333>;
interrupts = <10 0x8>;
interrupt-parent = <&ipic>;
};
gpio@c00 {
#gpio-cells = <2>;
device_type = "gpio";
compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
reg = <0xc00 0x18>;
interrupts = <74 0x8>;
interrupt-parent = <&ipic>;
gpio-controller;
};
/* IPIC
* interrupts cell = <intr #, sense>
* sense values match linux IORESOURCE_IRQ_* defines:
* sense == 8: Level, low assertion
* sense == 2: Edge, high-to-low change
*/
ipic: interrupt-controller@700 {
compatible = "fsl,ipic";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x700 0x100>;
device_type = "ipic";
};
ipic-msi@7c0 {
compatible = "fsl,ipic-msi";
reg = <0x7c0 0x40>;
msi-available-ranges = <0x0 0x100>;
interrupts = < 0x43 0x8
0x4 0x8
0x51 0x8
0x52 0x8
0x56 0x8
0x57 0x8
0x58 0x8
0x59 0x8 >;
interrupt-parent = < &ipic >;
};
};
pci0: pcie@e0009000 {
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
reg = <0xe0009000 0x00001000
0xb0000000 0x01000000>;
ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
bus-range = <0 0>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0 0 0 1 &ipic 1 8
0 0 0 2 &ipic 1 8
0 0 0 3 &ipic 1 8
0 0 0 4 &ipic 1 8>;
interrupts = <0x1 0x8>;
interrupt-parent = <&ipic>;
clock-frequency = <0>;
pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
reg = <0 0 0 0 0>;
ranges = <0x02000000 0 0xa0000000
0x02000000 0 0xa0000000
0 0x10000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00800000>;
};
};
};
arch/powerpc/boot/dts/mpc8540ads.dts
View file @ cdd854bc
......@@ -71,14 +71,14 @@ ecm@1000 {
};
memory-controller@2000 {
compatible = "fsl,8540-memory-controller";
compatible = "fsl,mpc8540-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
compatible = "fsl,mpc8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2, 256K
......
arch/powerpc/boot/dts/mpc8541cds.dts
View file @ cdd854bc
......@@ -71,14 +71,14 @@ ecm@1000 {
};
memory-controller@2000 {
compatible = "fsl,8541-memory-controller";
compatible = "fsl,mpc8541-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,8541-l2-cache-controller";
compatible = "fsl,mpc8541-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2, 256K
......
arch/powerpc/boot/dts/mpc8544ds.dts
View file @ cdd854bc
......@@ -73,14 +73,14 @@ ecm@1000 {
};
memory-controller@2000 {
compatible = "fsl,8544-memory-controller";
compatible = "fsl,mpc8544-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,8544-l2-cache-controller";
compatible = "fsl,mpc8544-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2, 256K
......
arch/powerpc/boot/dts/mpc8548cds.dts
View file @ cdd854bc
......@@ -74,14 +74,14 @@ ecm@1000 {
};
memory-controller@2000 {
compatible = "fsl,8548-memory-controller";
compatible = "fsl,mpc8548-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,8548-l2-cache-controller";
compatible = "fsl,mpc8548-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x80000>; // L2, 512K
......
arch/powerpc/boot/dts/mpc8555cds.dts
View file @ cdd854bc
......@@ -71,14 +71,14 @@ ecm@1000 {
};
memory-controller@2000 {
compatible = "fsl,8555-memory-controller";
compatible = "fsl,mpc8555-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,8555-l2-cache-controller";
compatible = "fsl,mpc8555-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2, 256K
......
arch/powerpc/boot/dts/mpc8560ads.dts
View file @ cdd854bc
......@@ -71,14 +71,14 @@ ecm@1000 {
};
memory-controller@2000 {
compatible = "fsl,8540-memory-controller";
compatible = "fsl,mpc8540-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
compatible = "fsl,mpc8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2, 256K
......
arch/powerpc/boot/dts/mpc8568mds.dts
View file @ cdd854bc
......@@ -124,14 +124,14 @@ ecm@1000 {
};
memory-controller@2000 {
compatible = "fsl,8568-memory-controller";
compatible = "fsl,mpc8568-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,8568-l2-cache-controller";
compatible = "fsl,mpc8568-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x80000>; // L2, 512K
......
arch/powerpc/boot/dts/p1021mds.dts
View file @ cdd854bc
......@@ -617,6 +617,7 @@ qe@ffe80000 {
bus-frequency = <0>;
fsl,qe-num-riscs = <1>;
fsl,qe-num-snums = <28>;
status = "disabled"; /* no firmware loaded */
qeic: interrupt-controller@80 {
interrupt-controller;
......
arch/powerpc/boot/dts/p1022ds.dts 0 → 100644
View file @ cdd854bc
This diff is collapsed.
arch/powerpc/boot/dts/pdm360ng.dts 0 → 100644
View file @ cdd854bc
/*
* Device Tree Source for IFM PDM360NG.
*
* Copyright 2009 - 2010 DENX Software Engineering.
* Anatolij Gustschin <agust@denx.de>
*
* Based on MPC5121E ADS dts.
* Copyright 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "pdm360ng";
compatible = "ifm,pdm360ng";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&ipic>;
aliases {
ethernet0 = &eth0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,5121@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <0x20>; // 32 bytes
i-cache-line-size = <0x20>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
bus-frequency = <198000000>; // 198 MHz csb bus
clock-frequency = <396000000>; // 396 MHz ppc core
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; // 512MB at 0
};
nfc@40000000 {
compatible = "fsl,mpc5121-nfc";
reg = <0x40000000 0x100000>;
interrupts = <0x6 0x8>;
#address-cells = <0x1>;
#size-cells = <0x1>;
bank-width = <0x1>;
chips = <0x1>;
partition@0 {
label = "nand0";
reg = <0x0 0x40000000>;
};
};
sram@50000000 {
compatible = "fsl,mpc5121-sram";
reg = <0x50000000 0x20000>; // 128K at 0x50000000
};
localbus@80000020 {
compatible = "fsl,mpc5121-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x80000020 0x40>;
ranges = <0x0 0x0 0xf0000000 0x10000000 /* Flash */
0x2 0x0 0x50040000 0x00020000>; /* CS2: MRAM */
flash@0,0 {
compatible = "amd,s29gl01gp", "cfi-flash";
reg = <0 0x00000000 0x08000000
0 0x08000000 0x08000000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <4>;
device-width = <2>;
partition@0 {
label = "u-boot";
reg = <0x00000000 0x00080000>;
read-only;
};
partition@80000 {
label = "environment";
reg = <0x00080000 0x00080000>;
read-only;
};
partition@100000 {
label = "splash-image";
reg = <0x00100000 0x00080000>;
read-only;
};
partition@180000 {
label = "device-tree";
reg = <0x00180000 0x00040000>;
};
partition@1c0000 {
label = "kernel";
reg = <0x001c0000 0x00500000>;
};
partition@6c0000 {
label = "filesystem";
reg = <0x006c0000 0x07940000>;
};
};
mram0@2,0 {
compatible = "mtd-ram";
reg = <2 0x00000 0x10000>;
bank-width = <2>;
};
mram1@2,10000 {
compatible = "mtd-ram";
reg = <2 0x010000 0x10000>;
bank-width = <2>;
};
};
soc@80000000 {
compatible = "fsl,mpc5121-immr";
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
ranges = <0x0 0x80000000 0x400000>;
reg = <0x80000000 0x400000>;
bus-frequency = <66000000>; // 66 MHz ips bus
// IPIC
// interrupts cell = <intr #, sense>
// sense values match linux IORESOURCE_IRQ_* defines:
// sense == 8: Level, low assertion
// sense == 2: Edge, high-to-low change
//
ipic: interrupt-controller@c00 {
compatible = "fsl,mpc5121-ipic", "fsl,ipic";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0xc00 0x100>;
};
rtc@a00 { // Real time clock
compatible = "fsl,mpc5121-rtc";
reg = <0xa00 0x100>;
interrupts = <79 0x8 80 0x8>;
};
reset@e00 { // Reset module
compatible = "fsl,mpc5121-reset";
reg = <0xe00 0x100>;
};
clock@f00 { // Clock control
compatible = "fsl,mpc5121-clock";
reg = <0xf00 0x100>;
};
pmc@1000{ //Power Management Controller
compatible = "fsl,mpc5121-pmc";
reg = <0x1000 0x100>;
interrupts = <83 0x2>;
};
gpio@1100 {
compatible = "fsl,mpc5121-gpio";
reg = <0x1100 0x100>;
interrupts = <78 0x8>;
};
can@1300 {
compatible = "fsl,mpc5121-mscan";
interrupts = <12 0x8>;
reg = <0x1300 0x80>;
};
can@1380 {
compatible = "fsl,mpc5121-mscan";
interrupts = <13 0x8>;
reg = <0x1380 0x80>;
};
i2c@1700 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5121-i2c";
reg = <0x1700 0x20>;
interrupts = <0x9 0x8>;
fsl,preserve-clocking;
eeprom@50 {
compatible = "at,24c01";
reg = <0x50>;
};
rtc@68 {
compatible = "stm,m41t00";
reg = <0x68>;
};
};
i2c@1740 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5121-i2c";
reg = <0x1740 0x20>;
interrupts = <0xb 0x8>;
fsl,preserve-clocking;
};
i2ccontrol@1760 {
compatible = "fsl,mpc5121-i2c-ctrl";
reg = <0x1760 0x8>;
};
axe@2000 {
compatible = "fsl,mpc5121-axe";
reg = <0x2000 0x100>;
interrupts = <42 0x8>;
};
display@2100 {
compatible = "fsl,mpc5121-diu";
reg = <0x2100 0x100>;
interrupts = <64 0x8>;
};
can@2300 {
compatible = "fsl,mpc5121-mscan";
interrupts = <90 0x8>;
reg = <0x2300 0x80>;
};
can@2380 {
compatible = "fsl,mpc5121-mscan";
interrupts = <91 0x8>;
reg = <0x2380 0x80>;
};
viu@2400 {
compatible = "fsl,mpc5121-viu";
reg = <0x2400 0x400>;
interrupts = <67 0x8>;
};
mdio@2800 {
compatible = "fsl,mpc5121-fec-mdio";
reg = <0x2800 0x200>;
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@0 {
compatible = "smsc,lan8700";
reg = <0x1f>;
};
};
eth0: ethernet@2800 {
compatible = "fsl,mpc5121-fec";
reg = <0x2800 0x200>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <4 0x8>;
phy-handle = < &phy >;
};
// USB1 using external ULPI PHY
usb@3000 {
compatible = "fsl,mpc5121-usb2-dr";
reg = <0x3000 0x600>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <43 0x8>;
dr_mode = "host";
phy_type = "ulpi";
};
// USB0 using internal UTMI PHY
usb@4000 {
compatible = "fsl,mpc5121-usb2-dr";
reg = <0x4000 0x600>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <44 0x8>;
dr_mode = "otg";
phy_type = "utmi_wide";
fsl,invert-pwr-fault;
};
// IO control
ioctl@a000 {
compatible = "fsl,mpc5121-ioctl";
reg = <0xA000 0x1000>;
};
// 512x PSCs are not 52xx PSCs compatible
serial@11000 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
cell-index = <0>;
reg = <0x11000 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
serial@11100 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
cell-index = <1>;
reg = <0x11100 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
serial@11200 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
cell-index = <2>;
reg = <0x11200 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
serial@11300 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
cell-index = <3>;
reg = <0x11300 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
serial@11400 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
cell-index = <4>;
reg = <0x11400 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
serial@11600 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
cell-index = <6>;
reg = <0x11600 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
serial@11800 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
cell-index = <8>;
reg = <0x11800 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
serial@11B00 {
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
cell-index = <11>;
reg = <0x11B00 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
};
pscfifo@11f00 {
compatible = "fsl,mpc5121-psc-fifo";
reg = <0x11f00 0x100>;
interrupts = <40 0x8>;
};
spi@11900 {
compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
cell-index = <9>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x11900 0x100>;
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
// 7845 touch screen controller
ts@0 {
compatible = "ti,ads7846";
reg = <0x0>;
spi-max-frequency = <3000000>;
// pen irq is GPIO25
interrupts = <78 0x8>;
};
};
dma@14000 {
compatible = "fsl,mpc5121-dma";
reg = <0x14000 0x1800>;
interrupts = <65 0x8>;
};
};
};
arch/powerpc/boot/dts/stxssa8555.dts 0 → 100644
View file @ cdd854bc
/*
* MPC8555-based STx GP3 Device Tree Source
*
* Copyright 2006, 2008 Freescale Semiconductor Inc.
*
* Copyright 2010 Silicon Turnkey Express LLC.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "stx,gp3";
compatible = "stx,gp3-8560", "stx,gp3";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8555@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
next-level-cache = <&L2>;
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>;
};
soc8555@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x0 0xe0000000 0x100000>;
bus-frequency = <0>;
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <8>;
};
ecm@1000 {
compatible = "fsl,mpc8555-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
memory-controller@2000 {
compatible = "fsl,mpc8555-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,mpc8555-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8555-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8555-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8555-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8555-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <0x2>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@4 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <0x4>;
device_type = "ethernet-phy";
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi1>;
phy-handle = <&phy1>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
crypto@30000 {
compatible = "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <45 2>;
interrupt-parent = <&mpic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x7e>;
fsl,descriptor-types-mask = <0x01010ebf>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
cpm@919c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
reg = <0x919c0 0x30>;
ranges;
muram@80000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x80000 0x10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0x0 0x2000 0x9000 0x1000>;
};
};
brg@919f0 {
compatible = "fsl,mpc8555-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <0x919f0 0x10 0x915f0 0x10>;
};
cpmpic: pic@90c00 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
interrupts = <46 2>;
interrupt-parent = <&mpic>;
reg = <0x90c00 0x80>;
compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
};
};
};
pci0: pci@e0008000 {
interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x10 */
0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x11 */
0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x12 (Slot 1) */
0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x13 (Slot 2) */
0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
/* IDSEL 0x14 (Slot 3) */
0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x15 (Slot 4) */
0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
/* Bus 1 (Tundra Bridge) */
/* IDSEL 0x12 (ISA bridge) */
0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
bus-range = <0 0>;
ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe0008000 0x1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
i8259@19000 {
interrupt-controller;
device_type = "interrupt-controller";
reg = <0x19000 0x0 0x0 0x0 0x1>;
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
interrupts = <1>;
interrupt-parent = <&pci0>;
};
};
pci1: pci@e0009000 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x15 */
0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
interrupt-parent = <&mpic>;
interrupts = <25 2>;
bus-range = <0 0>;
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe0009000 0x1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};
};
arch/powerpc/boot/dts/tqm8540.dts
View file @ cdd854bc
......@@ -289,7 +289,14 @@ pci0: pci@e0008000 {
interrupt-map = <
/* IDSEL 28 */
0xe000 0 0 1 &mpic 2 1
0xe000 0 0 2 &mpic 3 1>;
0xe000 0 0 2 &mpic 3 1
0xe000 0 0 3 &mpic 6 1
0xe000 0 0 4 &mpic 5 1
/* IDSEL 11 */
0x5800 0 0 1 &mpic 6 1
0x5800 0 0 2 &mpic 5 1
>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
......
arch/powerpc/boot/dts/tqm8541.dts
View file @ cdd854bc
......@@ -311,7 +311,14 @@ pci0: pci@e0008000 {
interrupt-map = <
/* IDSEL 28 */
0xe000 0 0 1 &mpic 2 1
0xe000 0 0 2 &mpic 3 1>;
0xe000 0 0 2 &mpic 3 1
0xe000 0 0 3 &mpic 6 1
0xe000 0 0 4 &mpic 5 1
/* IDSEL 11 */
0x5800 0 0 1 &mpic 6 1
0x5800 0 0 2 &mpic 5 1
>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
......
arch/powerpc/boot/dts/tqm8548-bigflash.dts
View file @ cdd854bc
......@@ -442,7 +442,14 @@ pci0: pci@a0008000 {
interrupt-map = <
/* IDSEL 28 */
0xe000 0 0 1 &mpic 2 1
0xe000 0 0 2 &mpic 3 1>;
0xe000 0 0 2 &mpic 3 1
0xe000 0 0 3 &mpic 6 1
0xe000 0 0 4 &mpic 5 1
/* IDSEL 11 */
0x5800 0 0 1 &mpic 6 1
0x5800 0 0 2 &mpic 5 1
>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
......
arch/powerpc/boot/dts/tqm8548.dts
View file @ cdd854bc
......@@ -442,7 +442,14 @@ pci0: pci@e0008000 {
interrupt-map = <
/* IDSEL 28 */
0xe000 0 0 1 &mpic 2 1
0xe000 0 0 2 &mpic 3 1>;
0xe000 0 0 2 &mpic 3 1
0xe000 0 0 3 &mpic 6 1
0xe000 0 0 4 &mpic 5 1
/* IDSEL 11 */
0x5800 0 0 1 &mpic 6 1
0x5800 0 0 2 &mpic 5 1
>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
......
arch/powerpc/boot/dts/tqm8555.dts
View file @ cdd854bc
......@@ -311,7 +311,14 @@ pci0: pci@e0008000 {
interrupt-map = <
/* IDSEL 28 */
0xe000 0 0 1 &mpic 2 1
0xe000 0 0 2 &mpic 3 1>;
0xe000 0 0 2 &mpic 3 1
0xe000 0 0 3 &mpic 6 1
0xe000 0 0 4 &mpic 5 1
/* IDSEL 11 */
0x5800 0 0 1 &mpic 6 1
0x5800 0 0 2 &mpic 5 1
>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
......
arch/powerpc/boot/dts/tqm8560.dts
View file @ cdd854bc
......@@ -382,7 +382,14 @@ pci0: pci@e0008000 {
interrupt-map = <
/* IDSEL 28 */
0xe000 0 0 1 &mpic 2 1
0xe000 0 0 2 &mpic 3 1>;
0xe000 0 0 2 &mpic 3 1
0xe000 0 0 3 &mpic 6 1
0xe000 0 0 4 &mpic 5 1
/* IDSEL 11 */
0x5800 0 0 1 &mpic 6 1
0x5800 0 0 2 &mpic 5 1
>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
......
arch/powerpc/boot/dts/tqm8xx.dts 0 → 100644
View file @ cdd854bc
/*
* TQM8XX Device Tree Source
*
* Heiko Schocher <hs@denx.de>
* 2010 DENX Software Engineering GmbH
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "TQM8xx";
compatible = "tqc,tqm8xx";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &eth0;
ethernet1 = &eth1;
mdio1 = &phy1;
serial0 = &smc1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,860@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <16>; // 16 bytes
i-cache-line-size = <16>; // 16 bytes
d-cache-size = <0x1000>; // L1, 4K
i-cache-size = <0x1000>; // L1, 4K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
interrupts = <15 2>; // decrementer interrupt
interrupt-parent = <&PIC>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x2000000>;
};
localbus@fff00100 {
compatible = "fsl,mpc860-localbus", "fsl,pq1-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0xfff00100 0x40>;
ranges = <
0x0 0x0 0x40000000 0x800000
>;
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x800000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <4>;
device-width = <2>;
};
};
soc@fff00000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0x0 0xfff00000 0x00004000>;
phy1: mdio@e00 {
compatible = "fsl,mpc866-fec-mdio", "fsl,pq1-fec-mdio";
reg = <0xe00 0x188>;
#address-cells = <1>;
#size-cells = <0>;
PHY: ethernet-phy@f {
reg = <0xf>;
device_type = "ethernet-phy";
};
};
eth1: ethernet@e00 {
device_type = "network";
compatible = "fsl,mpc866-fec-enet",
"fsl,pq1-fec-enet";
reg = <0xe00 0x188>;
interrupts = <3 1>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY>;
linux,network-index = <1>;
};
PIC: pic@0 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x24>;
compatible = "fsl,mpc860-pic", "fsl,pq1-pic";
};
cpm@9c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc860-cpm", "fsl,cpm1";
ranges;
reg = <0x9c0 0x40>;
brg-frequency = <0>;
interrupts = <0 2>; // cpm error interrupt
interrupt-parent = <&CPM_PIC>;
muram@2000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2000 0x2000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0x0 0x2000>;
};
};
brg@9f0 {
compatible = "fsl,mpc860-brg",
"fsl,cpm1-brg",
"fsl,cpm-brg";
reg = <0x9f0 0x10>;
clock-frequency = <0>;
};
CPM_PIC: pic@930 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupts = <5 2 0 2>;
interrupt-parent = <&PIC>;
reg = <0x930 0x20>;
compatible = "fsl,mpc860-cpm-pic",
"fsl,cpm1-pic";
};
smc1: serial@a80 {
device_type = "serial";
compatible = "fsl,mpc860-smc-uart",
"fsl,cpm1-smc-uart";
reg = <0xa80 0x10 0x3e80 0x40>;
interrupts = <4>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <0x90>;
};
eth0: ethernet@a00 {
device_type = "network";
compatible = "fsl,mpc860-scc-enet",
"fsl,cpm1-scc-enet";
reg = <0xa00 0x18 0x3c00 0x100>;
interrupts = <30>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-command = <0000>;
linux,network-index = <0>;
fixed-link = <0 0 10 0 0>;
};
};
};
};
arch/powerpc/configs/mpc85xx_defconfig
View file @ cdd854bc
......@@ -19,7 +19,8 @@ CONFIG_E500=y
CONFIG_FSL_EMB_PERFMON=y
CONFIG_BOOKE=y
CONFIG_FSL_BOOKE=y
# CONFIG_PHYS_64BIT is not set
CONFIG_PTE_64BIT=y
CONFIG_PHYS_64BIT=y
CONFIG_SPE=y
CONFIG_PPC_MMU_NOHASH=y
CONFIG_PPC_MMU_NOHASH_32=y
......@@ -28,7 +29,7 @@ CONFIG_PPC_BOOK3E_MMU=y
# CONFIG_SMP is not set
CONFIG_PPC32=y
CONFIG_WORD_SIZE=32
# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
CONFIG_MMU=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_TIME=y
......@@ -239,6 +240,7 @@ CONFIG_MPC85xx_MDS=y
CONFIG_MPC8536_DS=y
CONFIG_MPC85xx_DS=y
CONFIG_MPC85xx_RDB=y
CONFIG_P1022_DS=y
CONFIG_SOCRATES=y
CONFIG_KSI8560=y
CONFIG_XES_MPC85xx=y
......@@ -311,7 +313,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_MIGRATION=y
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
......@@ -321,7 +323,7 @@ CONFIG_PPC_4K_PAGES=y
# CONFIG_PPC_16K_PAGES is not set
# CONFIG_PPC_64K_PAGES is not set
# CONFIG_PPC_256K_PAGES is not set
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_FORCE_MAX_ZONEORDER=12
CONFIG_PROC_DEVICETREE=y
# CONFIG_CMDLINE_BOOL is not set
CONFIG_EXTRA_TARGETS=""
......@@ -1122,16 +1124,13 @@ CONFIG_VGA_CONSOLE=y
# CONFIG_VGACON_SOFT_SCROLLBACK is not set
CONFIG_DUMMY_CONSOLE=y
CONFIG_SOUND=y
CONFIG_SOUND_OSS_CORE=y
CONFIG_SOUND_OSS_CORE_PRECLAIM=y
# CONFIG_SOUND_OSS_CORE is not set
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
# CONFIG_SND_SEQUENCER is not set
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
CONFIG_SND_PCM_OSS_PLUGINS=y
# CONFIG_SND_MIXER_OSS is not set
# CONFIG_SND_PCM_OSS is not set
# CONFIG_SND_HRTIMER is not set
# CONFIG_SND_DYNAMIC_MINORS is not set
# CONFIG_SND_SUPPORT_OLD_API is not set
......@@ -1145,12 +1144,7 @@ CONFIG_SND_VMASTER=y
# CONFIG_SND_SBAWE_SEQ is not set
# CONFIG_SND_EMU10K1_SEQ is not set
CONFIG_SND_AC97_CODEC=y
CONFIG_SND_DRIVERS=y
# CONFIG_SND_DUMMY is not set
# CONFIG_SND_MTPAV is not set
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set
# CONFIG_SND_AC97_POWER_SAVE is not set
# CONFIG_SND_DRIVERS is not set
CONFIG_SND_PCI=y
# CONFIG_SND_AD1889 is not set
# CONFIG_SND_ALS300 is not set
......@@ -1218,12 +1212,8 @@ CONFIG_SND_INTEL8X0=y
# CONFIG_SND_VIRTUOSO is not set
# CONFIG_SND_VX222 is not set
# CONFIG_SND_YMFPCI is not set
CONFIG_SND_PPC=y
CONFIG_SND_USB=y
# CONFIG_SND_USB_AUDIO is not set
# CONFIG_SND_USB_UA101 is not set
# CONFIG_SND_USB_USX2Y is not set
# CONFIG_SND_USB_CAIAQ is not set
# CONFIG_SND_PPC is not set
# CONFIG_SND_USB is not set
# CONFIG_SND_SOC is not set
# CONFIG_SOUND_PRIME is not set
CONFIG_AC97_BUS=y
......
arch/powerpc/configs/mpc85xx_smp_defconfig
View file @ cdd854bc
......@@ -19,7 +19,8 @@ CONFIG_E500=y
CONFIG_FSL_EMB_PERFMON=y
CONFIG_BOOKE=y
CONFIG_FSL_BOOKE=y
# CONFIG_PHYS_64BIT is not set
CONFIG_PTE_64BIT=y
CONFIG_PHYS_64BIT=y
CONFIG_SPE=y
CONFIG_PPC_MMU_NOHASH=y
CONFIG_PPC_MMU_NOHASH_32=y
......@@ -29,7 +30,7 @@ CONFIG_SMP=y
CONFIG_NR_CPUS=8
CONFIG_PPC32=y
CONFIG_WORD_SIZE=32
# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
CONFIG_MMU=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_TIME=y
......@@ -243,6 +244,7 @@ CONFIG_MPC85xx_MDS=y
CONFIG_MPC8536_DS=y
CONFIG_MPC85xx_DS=y
CONFIG_MPC85xx_RDB=y
CONFIG_P1022_DS=y
CONFIG_SOCRATES=y
CONFIG_KSI8560=y
CONFIG_XES_MPC85xx=y
......@@ -316,7 +318,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_MIGRATION=y
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
......@@ -326,7 +328,7 @@ CONFIG_PPC_4K_PAGES=y
# CONFIG_PPC_16K_PAGES is not set
# CONFIG_PPC_64K_PAGES is not set
# CONFIG_PPC_256K_PAGES is not set
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_FORCE_MAX_ZONEORDER=12
CONFIG_PROC_DEVICETREE=y
# CONFIG_CMDLINE_BOOL is not set
CONFIG_EXTRA_TARGETS=""
......@@ -1127,16 +1129,13 @@ CONFIG_VGA_CONSOLE=y
# CONFIG_VGACON_SOFT_SCROLLBACK is not set
CONFIG_DUMMY_CONSOLE=y
CONFIG_SOUND=y
CONFIG_SOUND_OSS_CORE=y
CONFIG_SOUND_OSS_CORE_PRECLAIM=y
# CONFIG_SOUND_OSS_CORE is not set
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
# CONFIG_SND_SEQUENCER is not set
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
CONFIG_SND_PCM_OSS_PLUGINS=y
# CONFIG_SND_MIXER_OSS is not set
# CONFIG_SND_PCM_OSS is not set
# CONFIG_SND_HRTIMER is not set
# CONFIG_SND_DYNAMIC_MINORS is not set
# CONFIG_SND_SUPPORT_OLD_API is not set
......@@ -1150,12 +1149,7 @@ CONFIG_SND_VMASTER=y
# CONFIG_SND_SBAWE_SEQ is not set
# CONFIG_SND_EMU10K1_SEQ is not set
CONFIG_SND_AC97_CODEC=y
CONFIG_SND_DRIVERS=y
# CONFIG_SND_DUMMY is not set
# CONFIG_SND_MTPAV is not set
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set
# CONFIG_SND_AC97_POWER_SAVE is not set
# CONFIG_SND_DRIVERS is not set
CONFIG_SND_PCI=y
# CONFIG_SND_AD1889 is not set
# CONFIG_SND_ALS300 is not set
......@@ -1223,12 +1217,8 @@ CONFIG_SND_INTEL8X0=y
# CONFIG_SND_VIRTUOSO is not set
# CONFIG_SND_VX222 is not set
# CONFIG_SND_YMFPCI is not set
CONFIG_SND_PPC=y
CONFIG_SND_USB=y
# CONFIG_SND_USB_AUDIO is not set
# CONFIG_SND_USB_UA101 is not set
# CONFIG_SND_USB_USX2Y is not set
# CONFIG_SND_USB_CAIAQ is not set
# CONFIG_SND_PPC is not set
# CONFIG_SND_USB is not set
# CONFIG_SND_SOC is not set
# CONFIG_SOUND_PRIME is not set
CONFIG_AC97_BUS=y
......
arch/powerpc/configs/tqm8xx_defconfig 0 → 100644
View file @ cdd854bc
This diff is collapsed.
arch/powerpc/include/asm/abs_addr.h
View file @ cdd854bc
......@@ -69,7 +69,7 @@ static inline unsigned long phys_to_abs(unsigned long pa)
* Legacy iSeries Hypervisor calls
*/
#define iseries_hv_addr(virtaddr) \
(0x8000000000000000 | virt_to_abs(virtaddr))
(0x8000000000000000UL | virt_to_abs(virtaddr))
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_ABS_ADDR_H */
arch/powerpc/include/asm/asm-compat.h
View file @ cdd854bc
......@@ -30,6 +30,7 @@
#define PPC_STLCX stringify_in_c(stdcx.)
#define PPC_CNTLZL stringify_in_c(cntlzd)
#define PPC_LR_STKOFF 16
#define PPC_MIN_STKFRM 112
/* Move to CR, single-entry optimized version. Only available
* on POWER4 and later.
......@@ -55,6 +56,7 @@
#define PPC_CNTLZL stringify_in_c(cntlzw)
#define PPC_MTOCRF stringify_in_c(mtcrf)
#define PPC_LR_STKOFF 4
#define PPC_MIN_STKFRM 16
#endif
......
arch/powerpc/include/asm/cputable.h
View file @ cdd854bc
......@@ -517,6 +517,10 @@ static inline int cpu_has_feature(unsigned long feature)
& feature);
}
#ifdef CONFIG_HAVE_HW_BREAKPOINT
#define HBP_NUM 1
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
#endif /* !__ASSEMBLY__ */
#endif /* __KERNEL__ */
......
arch/powerpc/include/asm/dbell.h
View file @ cdd854bc
......@@ -27,10 +27,10 @@ enum ppc_dbell {
PPC_G_DBELL_MC = 4, /* guest mcheck doorbell */
};
#ifdef CONFIG_SMP
extern unsigned long dbell_smp_message[NR_CPUS];
extern void smp_dbell_message_pass(int target, int msg);
#endif
extern void doorbell_message_pass(int target, int msg);
extern void doorbell_exception(struct pt_regs *regs);
extern void doorbell_check_self(void);
extern void doorbell_setup_this_cpu(void);
static inline void ppc_msgsnd(enum ppc_dbell type, u32 flags, u32 tag)
{
......
arch/powerpc/include/asm/hvcall.h
View file @ cdd854bc
......@@ -74,6 +74,7 @@
#define H_NOT_ENOUGH_RESOURCES -44
#define H_R_STATE -45
#define H_RESCINDEND -46
#define H_MULTI_THREADS_ACTIVE -9005
/* Long Busy is a condition that can be returned by the firmware
......
arch/powerpc/include/asm/hw_breakpoint.h 0 → 100644
View file @ cdd854bc
/*
* PowerPC BookIII S hardware breakpoint definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright 2010, IBM Corporation.
* Author: K.Prasad <prasad@linux.vnet.ibm.com>
*
*/
#ifndef _PPC_BOOK3S_64_HW_BREAKPOINT_H
#define _PPC_BOOK3S_64_HW_BREAKPOINT_H
#ifdef __KERNEL__
#ifdef CONFIG_HAVE_HW_BREAKPOINT
struct arch_hw_breakpoint {
bool extraneous_interrupt;
u8 len; /* length of the target data symbol */
int type;
unsigned long address;
};
#include <linux/kdebug.h>
#include <asm/reg.h>
#include <asm/system.h>
struct perf_event;
struct pmu;
struct perf_sample_data;
#define HW_BREAKPOINT_ALIGN 0x7
/* Maximum permissible length of any HW Breakpoint */
#define HW_BREAKPOINT_LEN 0x8
extern int hw_breakpoint_slots(int type);
extern int arch_bp_generic_fields(int type, int *gen_bp_type);
extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
unsigned long val, void *data);
int arch_install_hw_breakpoint(struct perf_event *bp);
void arch_uninstall_hw_breakpoint(struct perf_event *bp);
void hw_breakpoint_pmu_read(struct perf_event *bp);
extern void flush_ptrace_hw_breakpoint(struct task_struct *tsk);
extern struct pmu perf_ops_bp;
extern void ptrace_triggered(struct perf_event *bp, int nmi,
struct perf_sample_data *data, struct pt_regs *regs);
static inline void hw_breakpoint_disable(void)
{
set_dabr(0);
}
extern void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs);
#else /* CONFIG_HAVE_HW_BREAKPOINT */
static inline void hw_breakpoint_disable(void) { }
static inline void thread_change_pc(struct task_struct *tsk,
struct pt_regs *regs) { }
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
#endif /* __KERNEL__ */
#endif /* _PPC_BOOK3S_64_HW_BREAKPOINT_H */
arch/powerpc/include/asm/machdep.h
View file @ cdd854bc
......@@ -266,6 +266,7 @@ struct machdep_calls {
void (*suspend_disable_irqs)(void);
void (*suspend_enable_irqs)(void);
#endif
int (*suspend_disable_cpu)(void);
#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
ssize_t (*cpu_probe)(const char *, size_t);
......@@ -277,6 +278,7 @@ extern void e500_idle(void);
extern void power4_idle(void);
extern void power4_cpu_offline_powersave(void);
extern void ppc6xx_idle(void);
extern void book3e_idle(void);
/*
* ppc_md contains a copy of the machine description structure for the
......@@ -366,8 +368,5 @@ static inline void log_error(char *buf, unsigned int err_type, int fatal)
#define machine_late_initcall(mach,fn) __define_machine_initcall(mach,"7",fn,7)
#define machine_late_initcall_sync(mach,fn) __define_machine_initcall(mach,"7s",fn,7s)
void generic_suspend_disable_irqs(void);
void generic_suspend_enable_irqs(void);
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_MACHDEP_H */
arch/powerpc/include/asm/mmu-book3e.h
View file @ cdd854bc
......@@ -193,6 +193,10 @@ struct mmu_psize_def
{
unsigned int shift; /* number of bits */
unsigned int enc; /* PTE encoding */
unsigned int ind; /* Corresponding indirect page size shift */
unsigned int flags;
#define MMU_PAGE_SIZE_DIRECT 0x1 /* Supported as a direct size */
#define MMU_PAGE_SIZE_INDIRECT 0x2 /* Supported as an indirect size */
};
extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
......
arch/powerpc/include/asm/mpc5121.h
View file @ cdd854bc
......@@ -21,4 +21,36 @@ struct mpc512x_reset_module {
u32 rcer; /* Reset Control Enable Register */
};
/*
* Clock Control Module
*/
struct mpc512x_ccm {
u32 spmr; /* System PLL Mode Register */
u32 sccr1; /* System Clock Control Register 1 */
u32 sccr2; /* System Clock Control Register 2 */
u32 scfr1; /* System Clock Frequency Register 1 */
u32 scfr2; /* System Clock Frequency Register 2 */
u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
u32 bcr; /* Bread Crumb Register */
u32 p0ccr; /* PSC0 Clock Control Register */
u32 p1ccr; /* PSC1 CCR */
u32 p2ccr; /* PSC2 CCR */
u32 p3ccr; /* PSC3 CCR */
u32 p4ccr; /* PSC4 CCR */
u32 p5ccr; /* PSC5 CCR */
u32 p6ccr; /* PSC6 CCR */
u32 p7ccr; /* PSC7 CCR */
u32 p8ccr; /* PSC8 CCR */
u32 p9ccr; /* PSC9 CCR */
u32 p10ccr; /* PSC10 CCR */
u32 p11ccr; /* PSC11 CCR */
u32 spccr; /* SPDIF Clock Control Register */
u32 cccr; /* CFM Clock Control Register */
u32 dccr; /* DIU Clock Control Register */
u32 m1ccr; /* MSCAN1 CCR */
u32 m2ccr; /* MSCAN2 CCR */
u32 m3ccr; /* MSCAN3 CCR */
u32 m4ccr; /* MSCAN4 CCR */
u8 res[0x98]; /* Reserved */
};
#endif /* __ASM_POWERPC_MPC5121_H__ */
arch/powerpc/include/asm/paca.h
View file @ cdd854bc
......@@ -146,7 +146,7 @@ struct paca_struct {
extern struct paca_struct *paca;
extern __initdata struct paca_struct boot_paca;
extern void initialise_paca(struct paca_struct *new_paca, int cpu);
extern void setup_paca(struct paca_struct *new_paca);
extern void allocate_pacas(void);
extern void free_unused_pacas(void);
......
arch/powerpc/include/asm/percpu.h
View file @ cdd854bc
#ifndef _ASM_POWERPC_PERCPU_H_
#define _ASM_POWERPC_PERCPU_H_
#ifdef __powerpc64__
#include <linux/compiler.h>
/*
* Same as asm-generic/percpu.h, except that we store the per cpu offset
......@@ -12,9 +11,7 @@
#include <asm/paca.h>
#define __per_cpu_offset(cpu) (paca[cpu].data_offset)
#define __my_cpu_offset local_paca->data_offset
#define per_cpu_offset(x) (__per_cpu_offset(x))
#endif /* CONFIG_SMP */
#endif /* __powerpc64__ */
......
arch/powerpc/include/asm/ppc-opcode.h
View file @ cdd854bc
......@@ -52,13 +52,17 @@
#define PPC_INST_WAIT 0x7c00007c
#define PPC_INST_TLBIVAX 0x7c000624
#define PPC_INST_TLBSRX_DOT 0x7c0006a5
#define PPC_INST_XXLOR 0xf0000510
/* macros to insert fields into opcodes */
#define __PPC_RA(a) (((a) & 0x1f) << 16)
#define __PPC_RB(b) (((b) & 0x1f) << 11)
#define __PPC_RS(s) (((s) & 0x1f) << 21)
#define __PPC_RT(s) __PPC_RS(s)
#define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
#define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
#define __PPC_XT(s) __PPC_XS(s)
#define __PPC_T_TLB(t) (((t) & 0x3) << 21)
#define __PPC_WC(w) (((w) & 0x3) << 21)
/*
......@@ -106,9 +110,12 @@
* the 128 bit load store instructions based on that.
*/
#define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
#define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
#define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \
VSX_XX1((s), (a), (b)))
#define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \
VSX_XX1((s), (a), (b)))
#define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \
VSX_XX3((t), (a), (b)))
#endif /* _ASM_POWERPC_PPC_OPCODE_H */
arch/powerpc/include/asm/processor.h
View file @ cdd854bc
......@@ -209,6 +209,14 @@ struct thread_struct {
#ifdef CONFIG_PPC64
unsigned long start_tb; /* Start purr when proc switched in */
unsigned long accum_tb; /* Total accumilated purr for process */
#ifdef CONFIG_HAVE_HW_BREAKPOINT
struct perf_event *ptrace_bps[HBP_NUM];
/*
* Helps identify source of single-step exception and subsequent
* hw-breakpoint enablement
*/
struct perf_event *last_hit_ubp;
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
#endif
unsigned long dabr; /* Data address breakpoint register */
#ifdef CONFIG_ALTIVEC
......
arch/powerpc/include/asm/reg.h
View file @ cdd854bc
......@@ -890,7 +890,7 @@
#ifndef __ASSEMBLY__
#define mfmsr() ({unsigned long rval; \
asm volatile("mfmsr %0" : "=r" (rval)); rval;})
#ifdef CONFIG_PPC64
#ifdef CONFIG_PPC_BOOK3S_64
#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
: : "r" (v) : "memory")
#define mtmsrd(v) __mtmsrd((v), 0)
......
arch/powerpc/include/asm/reg_booke.h
View file @ cdd854bc
......@@ -29,8 +29,8 @@
#if defined(CONFIG_PPC_BOOK3E_64)
#define MSR_ MSR_ME | MSR_CE
#define MSR_KERNEL MSR_ | MSR_CM
#define MSR_USER32 MSR_ | MSR_PR | MSR_EE
#define MSR_USER64 MSR_USER32 | MSR_CM
#define MSR_USER32 MSR_ | MSR_PR | MSR_EE | MSR_DE
#define MSR_USER64 MSR_USER32 | MSR_CM | MSR_DE
#elif defined (CONFIG_40x)
#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
......@@ -62,6 +62,7 @@
#define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */
#define SPRN_MAS5_MAS6 0x15c /* MMU Assist Register 5 || 6 */
#define SPRN_MAS8_MAS1 0x15d /* MMU Assist Register 8 || 1 */
#define SPRN_EPTCFG 0x15e /* Embedded Page Table Config */
#define SPRN_MAS7_MAS3 0x174 /* MMU Assist Register 7 || 3 */
#define SPRN_MAS0_MAS1 0x175 /* MMU Assist Register 0 || 1 */
#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
......
arch/powerpc/include/asm/rtas.h
View file @ cdd854bc
......@@ -63,6 +63,14 @@ struct rtas_t {
struct device_node *dev; /* virtual address pointer */
};
struct rtas_suspend_me_data {
atomic_t working; /* number of cpus accessing this struct */
atomic_t done;
int token; /* ibm,suspend-me */
atomic_t error;
struct completion *complete; /* wait on this until working == 0 */
};
/* RTAS event classes */
#define RTAS_INTERNAL_ERROR 0x80000000 /* set bit 0 */
#define RTAS_EPOW_WARNING 0x40000000 /* set bit 1 */
......@@ -137,6 +145,9 @@ struct rtas_t {
#define RTAS_TYPE_PMGM_CONFIG_CHANGE 0x70
#define RTAS_TYPE_PMGM_SERVICE_PROC 0x71
/* RTAS check-exception vector offset */
#define RTAS_VECTOR_EXTERNAL_INTERRUPT 0x500
struct rtas_error_log {
unsigned long version:8; /* Architectural version */
unsigned long severity:3; /* Severity level of error */
......@@ -174,6 +185,8 @@ extern int rtas_set_indicator(int indicator, int index, int new_value);
extern int rtas_set_indicator_fast(int indicator, int index, int new_value);
extern void rtas_progress(char *s, unsigned short hex);
extern void rtas_initialize(void);
extern int rtas_suspend_cpu(struct rtas_suspend_me_data *data);
extern int rtas_suspend_last_cpu(struct rtas_suspend_me_data *data);
struct rtc_time;
extern unsigned long rtas_get_boot_time(void);
......
arch/powerpc/include/asm/time.h
View file @ cdd854bc
......@@ -28,16 +28,12 @@
extern unsigned long tb_ticks_per_jiffy;
extern unsigned long tb_ticks_per_usec;
extern unsigned long tb_ticks_per_sec;
extern u64 tb_to_xs;
extern unsigned tb_to_us;
struct rtc_time;
extern void to_tm(int tim, struct rtc_time * tm);
extern void GregorianDay(struct rtc_time *tm);
extern time_t last_rtc_update;
extern void generic_calibrate_decr(void);
extern void wakeup_decrementer(void);
extern void snapshot_timebase(void);
extern void set_dec_cpu6(unsigned int val);
......@@ -204,9 +200,6 @@ static inline unsigned long tb_ticks_since(unsigned long tstamp)
extern u64 mulhdu(u64, u64);
#endif
extern void smp_space_timers(unsigned int);
extern unsigned mulhwu_scale_factor(unsigned, unsigned);
extern void div128_by_32(u64 dividend_high, u64 dividend_low,
unsigned divisor, struct div_result *dr);
......
arch/powerpc/include/asm/topology.h
View file @ cdd854bc
......@@ -87,6 +87,9 @@ static inline int pcibus_to_node(struct pci_bus *bus)
.balance_interval = 1, \
}
extern int __node_distance(int, int);
#define node_distance(a, b) __node_distance(a, b)
extern void __init dump_numa_cpu_topology(void);
extern int sysfs_add_device_to_node(struct sys_device *dev, int nid);
......
arch/powerpc/include/asm/vdso_datapage.h
View file @ cdd854bc
......@@ -85,6 +85,7 @@ struct vdso_data {
__s32 wtom_clock_sec; /* Wall to monotonic clock */
__s32 wtom_clock_nsec;
struct timespec stamp_xtime; /* xtime as at tb_orig_stamp */
__u32 stamp_sec_fraction; /* fractional seconds of stamp_xtime */
__u32 syscall_map_64[SYSCALL_MAP_SIZE]; /* map of syscalls */
__u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
};
......@@ -105,6 +106,7 @@ struct vdso_data {
__s32 wtom_clock_sec; /* Wall to monotonic clock */
__s32 wtom_clock_nsec;
struct timespec stamp_xtime; /* xtime as at tb_orig_stamp */
__u32 stamp_sec_fraction; /* fractional seconds of stamp_xtime */
__u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
__u32 dcache_block_size; /* L1 d-cache block size */
__u32 icache_block_size; /* L1 i-cache block size */
......
arch/powerpc/kernel/Makefile
View file @ cdd854bc
......@@ -34,9 +34,10 @@ obj-y += vdso32/
obj-$(CONFIG_PPC64) += setup_64.o sys_ppc32.o \
signal_64.o ptrace32.o \
paca.o nvram_64.o firmware.o
obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_ppc970.o cpu_setup_pa6t.o
obj64-$(CONFIG_RELOCATABLE) += reloc_64.o
obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o
obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_book3e.o
obj-$(CONFIG_PPC64) += vdso64/
obj-$(CONFIG_ALTIVEC) += vecemu.o
obj-$(CONFIG_PPC_970_NAP) += idle_power4.o
......@@ -67,6 +68,7 @@ obj64-$(CONFIG_HIBERNATION) += swsusp_asm64.o
obj-$(CONFIG_MODULES) += module.o module_$(CONFIG_WORD_SIZE).o
obj-$(CONFIG_44x) += cpu_setup_44x.o
obj-$(CONFIG_FSL_BOOKE) += cpu_setup_fsl_booke.o dbell.o
obj-$(CONFIG_PPC_BOOK3E_64) += dbell.o
extra-y := head_$(CONFIG_WORD_SIZE).o
extra-$(CONFIG_PPC_BOOK3E_32) := head_new_booke.o
......
arch/powerpc/kernel/asm-offsets.c
View file @ cdd854bc
......@@ -194,7 +194,6 @@ int main(void)
DEFINE(PACA_STARTSPURR, offsetof(struct paca_struct, startspurr));
DEFINE(PACA_USER_TIME, offsetof(struct paca_struct, user_time));
DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time));
DEFINE(PACA_DATA_OFFSET, offsetof(struct paca_struct, data_offset));
DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save));
#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
DEFINE(PACA_KVM_SVCPU, offsetof(struct paca_struct, shadow_vcpu));
......@@ -342,6 +341,7 @@ int main(void)
DEFINE(WTOM_CLOCK_SEC, offsetof(struct vdso_data, wtom_clock_sec));
DEFINE(WTOM_CLOCK_NSEC, offsetof(struct vdso_data, wtom_clock_nsec));
DEFINE(STAMP_XTIME, offsetof(struct vdso_data, stamp_xtime));
DEFINE(STAMP_SEC_FRAC, offsetof(struct vdso_data, stamp_sec_fraction));
DEFINE(CFG_ICACHE_BLOCKSZ, offsetof(struct vdso_data, icache_block_size));
DEFINE(CFG_DCACHE_BLOCKSZ, offsetof(struct vdso_data, dcache_block_size));
DEFINE(CFG_ICACHE_LOGBLOCKSZ, offsetof(struct vdso_data, icache_log_block_size));
......
arch/powerpc/kernel/cputable.c
View file @ cdd854bc
......@@ -1364,10 +1364,10 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_4xx,
.platform = "ppc405",
},
{ /* 405EX */
.pvr_mask = 0xffff0004,
.pvr_value = 0x12910004,
.cpu_name = "405EX",
{ /* 405EX Rev. A/B with Security */
.pvr_mask = 0xffff000f,
.pvr_value = 0x12910007,
.cpu_name = "405EX Rev. A/B",
.cpu_features = CPU_FTRS_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
......@@ -1377,10 +1377,114 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_4xx,
.platform = "ppc405",
},
{ /* 405EXr */
.pvr_mask = 0xffff0004,
{ /* 405EX Rev. C without Security */
.pvr_mask = 0xffff000f,
.pvr_value = 0x1291000d,
.cpu_name = "405EX Rev. C",
.cpu_features = CPU_FTRS_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.mmu_features = MMU_FTR_TYPE_40x,
.icache_bsize = 32,
.dcache_bsize = 32,
.machine_check = machine_check_4xx,
.platform = "ppc405",
},
{ /* 405EX Rev. C with Security */
.pvr_mask = 0xffff000f,
.pvr_value = 0x1291000f,
.cpu_name = "405EX Rev. C",
.cpu_features = CPU_FTRS_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.mmu_features = MMU_FTR_TYPE_40x,
.icache_bsize = 32,
.dcache_bsize = 32,
.machine_check = machine_check_4xx,
.platform = "ppc405",
},
{ /* 405EX Rev. D without Security */
.pvr_mask = 0xffff000f,
.pvr_value = 0x12910003,
.cpu_name = "405EX Rev. D",
.cpu_features = CPU_FTRS_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.mmu_features = MMU_FTR_TYPE_40x,
.icache_bsize = 32,
.dcache_bsize = 32,
.machine_check = machine_check_4xx,
.platform = "ppc405",
},
{ /* 405EX Rev. D with Security */
.pvr_mask = 0xffff000f,
.pvr_value = 0x12910005,
.cpu_name = "405EX Rev. D",
.cpu_features = CPU_FTRS_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.mmu_features = MMU_FTR_TYPE_40x,
.icache_bsize = 32,
.dcache_bsize = 32,
.machine_check = machine_check_4xx,
.platform = "ppc405",
},
{ /* 405EXr Rev. A/B without Security */
.pvr_mask = 0xffff000f,
.pvr_value = 0x12910001,
.cpu_name = "405EXr Rev. A/B",
.cpu_features = CPU_FTRS_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.mmu_features = MMU_FTR_TYPE_40x,
.icache_bsize = 32,
.dcache_bsize = 32,
.machine_check = machine_check_4xx,
.platform = "ppc405",
},
{ /* 405EXr Rev. C without Security */
.pvr_mask = 0xffff000f,
.pvr_value = 0x12910009,
.cpu_name = "405EXr Rev. C",
.cpu_features = CPU_FTRS_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.mmu_features = MMU_FTR_TYPE_40x,
.icache_bsize = 32,
.dcache_bsize = 32,
.machine_check = machine_check_4xx,
.platform = "ppc405",
},
{ /* 405EXr Rev. C with Security */
.pvr_mask = 0xffff000f,
.pvr_value = 0x1291000b,
.cpu_name = "405EXr Rev. C",
.cpu_features = CPU_FTRS_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.mmu_features = MMU_FTR_TYPE_40x,
.icache_bsize = 32,
.dcache_bsize = 32,
.machine_check = machine_check_4xx,
.platform = "ppc405",
},
{ /* 405EXr Rev. D without Security */
.pvr_mask = 0xffff000f,
.pvr_value = 0x12910000,
.cpu_name = "405EXr",
.cpu_name = "405EXr Rev. D",
.cpu_features = CPU_FTRS_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.mmu_features = MMU_FTR_TYPE_40x,
.icache_bsize = 32,
.dcache_bsize = 32,
.machine_check = machine_check_4xx,
.platform = "ppc405",
},
{ /* 405EXr Rev. D with Security */
.pvr_mask = 0xffff000f,
.pvr_value = 0x12910002,
.cpu_name = "405EXr Rev. D",
.cpu_features = CPU_FTRS_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
......
arch/powerpc/kernel/crash_dump.c
View file @ cdd854bc
......@@ -128,9 +128,9 @@ ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
if (!csize)
return 0;
csize = min(csize, PAGE_SIZE);
csize = min_t(size_t, csize, PAGE_SIZE);
if (pfn < max_pfn) {
if ((min_low_pfn < pfn) && (pfn < max_pfn)) {
vaddr = __va(pfn << PAGE_SHIFT);
csize = copy_oldmem_vaddr(vaddr, buf, csize, offset, userbuf);
} else {
......
arch/powerpc/kernel/dbell.c
View file @ cdd854bc
......@@ -13,32 +13,88 @@
#include <linux/kernel.h>
#include <linux/smp.h>
#include <linux/threads.h>
#include <linux/percpu.h>
#include <asm/dbell.h>
#include <asm/irq_regs.h>
#ifdef CONFIG_SMP
unsigned long dbell_smp_message[NR_CPUS];
struct doorbell_cpu_info {
unsigned long messages; /* current messages bits */
unsigned int tag; /* tag value */
};
void smp_dbell_message_pass(int target, int msg)
static DEFINE_PER_CPU(struct doorbell_cpu_info, doorbell_cpu_info);
void doorbell_setup_this_cpu(void)
{
struct doorbell_cpu_info *info = &__get_cpu_var(doorbell_cpu_info);
info->messages = 0;
info->tag = mfspr(SPRN_PIR) & 0x3fff;
}
void doorbell_message_pass(int target, int msg)
{
struct doorbell_cpu_info *info;
int i;
if(target < NR_CPUS) {
set_bit(msg, &dbell_smp_message[target]);
ppc_msgsnd(PPC_DBELL, 0, target);
if (target < NR_CPUS) {
info = &per_cpu(doorbell_cpu_info, target);
set_bit(msg, &info->messages);
ppc_msgsnd(PPC_DBELL, 0, info->tag);
}
else if(target == MSG_ALL_BUT_SELF) {
else if (target == MSG_ALL_BUT_SELF) {
for_each_online_cpu(i) {
if (i == smp_processor_id())
continue;
set_bit(msg, &dbell_smp_message[i]);
ppc_msgsnd(PPC_DBELL, 0, i);
info = &per_cpu(doorbell_cpu_info, i);
set_bit(msg, &info->messages);
ppc_msgsnd(PPC_DBELL, 0, info->tag);
}
}
else { /* target == MSG_ALL */
for_each_online_cpu(i)
set_bit(msg, &dbell_smp_message[i]);
for_each_online_cpu(i) {
info = &per_cpu(doorbell_cpu_info, i);
set_bit(msg, &info->messages);
}
ppc_msgsnd(PPC_DBELL, PPC_DBELL_MSG_BRDCAST, 0);
}
}
#endif
void doorbell_exception(struct pt_regs *regs)
{
struct pt_regs *old_regs = set_irq_regs(regs);
struct doorbell_cpu_info *info = &__get_cpu_var(doorbell_cpu_info);
int msg;
/* Warning: regs can be NULL when called from irq enable */
if (!info->messages || (num_online_cpus() < 2))
goto out;
for (msg = 0; msg < 4; msg++)
if (test_and_clear_bit(msg, &info->messages))
smp_message_recv(msg);
out:
set_irq_regs(old_regs);
}
void doorbell_check_self(void)
{
struct doorbell_cpu_info *info = &__get_cpu_var(doorbell_cpu_info);
if (!info->messages)
return;
ppc_msgsnd(PPC_DBELL, 0, info->tag);
}
#else /* CONFIG_SMP */
void doorbell_exception(struct pt_regs *regs)
{
printk(KERN_WARNING "Received doorbell on non-smp system\n");
}
#endif /* CONFIG_SMP */
arch/powerpc/kernel/exceptions-64e.S
View file @ cdd854bc
......@@ -191,6 +191,12 @@ exc_##n##_bad_stack: \
sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \
b bad_stack_book3e; /* bad stack error */
/* WARNING: If you change the layout of this stub, make sure you chcek
* the debug exception handler which handles single stepping
* into exceptions from userspace, and the MM code in
* arch/powerpc/mm/tlb_nohash.c which patches the branch here
* and would need to be updated if that branch is moved
*/
#define EXCEPTION_STUB(loc, label) \
. = interrupt_base_book3e + loc; \
nop; /* To make debug interrupts happy */ \
......@@ -204,11 +210,30 @@ exc_##n##_bad_stack: \
lis r,TSR_FIS@h; \
mtspr SPRN_TSR,r
/* Used by asynchronous interrupt that may happen in the idle loop.
*
* This check if the thread was in the idle loop, and if yes, returns
* to the caller rather than the PC. This is to avoid a race if
* interrupts happen before the wait instruction.
*/
#define CHECK_NAPPING() \
clrrdi r11,r1,THREAD_SHIFT; \
ld r10,TI_LOCAL_FLAGS(r11); \
andi. r9,r10,_TLF_NAPPING; \
beq+ 1f; \
ld r8,_LINK(r1); \
rlwinm r7,r10,0,~_TLF_NAPPING; \
std r8,_NIP(r1); \
std r7,TI_LOCAL_FLAGS(r11); \
1:
#define MASKABLE_EXCEPTION(trapnum, label, hdlr, ack) \
START_EXCEPTION(label); \
NORMAL_EXCEPTION_PROLOG(trapnum, PROLOG_ADDITION_MASKABLE) \
EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE_ALL) \
ack(r8); \
CHECK_NAPPING(); \
addi r3,r1,STACK_FRAME_OVERHEAD; \
bl hdlr; \
b .ret_from_except_lite;
......@@ -246,11 +271,9 @@ interrupt_base_book3e: /* fake trap */
EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
EXCEPTION_STUB(0x1c0, data_tlb_miss)
EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
EXCEPTION_STUB(0x280, doorbell)
EXCEPTION_STUB(0x2a0, doorbell_crit)
#if 0
EXCEPTION_STUB(0x280, processor_doorbell)
EXCEPTION_STUB(0x220, processor_doorbell_crit)
#endif
.globl interrupt_end_book3e
interrupt_end_book3e:
......@@ -259,6 +282,7 @@ interrupt_end_book3e:
CRIT_EXCEPTION_PROLOG(0x100, PROLOG_ADDITION_NONE)
// EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE_ALL)
// bl special_reg_save_crit
// CHECK_NAPPING();
// addi r3,r1,STACK_FRAME_OVERHEAD
// bl .critical_exception
// b ret_from_crit_except
......@@ -270,6 +294,7 @@ interrupt_end_book3e:
// EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE_ALL)
// bl special_reg_save_mc
// addi r3,r1,STACK_FRAME_OVERHEAD
// CHECK_NAPPING();
// bl .machine_check_exception
// b ret_from_mc_except
b .
......@@ -340,6 +365,7 @@ interrupt_end_book3e:
CRIT_EXCEPTION_PROLOG(0x9f0, PROLOG_ADDITION_NONE)
// EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE_ALL)
// bl special_reg_save_crit
// CHECK_NAPPING();
// addi r3,r1,STACK_FRAME_OVERHEAD
// bl .unknown_exception
// b ret_from_crit_except
......@@ -428,6 +454,20 @@ interrupt_end_book3e:
kernel_dbg_exc:
b . /* NYI */
/* Doorbell interrupt */
MASKABLE_EXCEPTION(0x2070, doorbell, .doorbell_exception, ACK_NONE)
/* Doorbell critical Interrupt */
START_EXCEPTION(doorbell_crit);
CRIT_EXCEPTION_PROLOG(0x2080, PROLOG_ADDITION_NONE)
// EXCEPTION_COMMON(0x2080, PACA_EXCRIT, INTS_DISABLE_ALL)
// bl special_reg_save_crit
// CHECK_NAPPING();
// addi r3,r1,STACK_FRAME_OVERHEAD
// bl .doorbell_critical_exception
// b ret_from_crit_except
b .
/*
* An interrupt came in while soft-disabled; clear EE in SRR1,
......@@ -563,6 +603,8 @@ BAD_STACK_TRAMPOLINE(0xd00)
BAD_STACK_TRAMPOLINE(0xe00)
BAD_STACK_TRAMPOLINE(0xf00)
BAD_STACK_TRAMPOLINE(0xf20)
BAD_STACK_TRAMPOLINE(0x2070)
BAD_STACK_TRAMPOLINE(0x2080)
.globl bad_stack_book3e
bad_stack_book3e:
......
arch/powerpc/kernel/exceptions-64s.S
View file @ cdd854bc
......@@ -828,6 +828,7 @@ END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
/* We have a data breakpoint exception - handle it */
handle_dabr_fault:
bl .save_nvgprs
ld r4,_DAR(r1)
ld r5,_DSISR(r1)
addi r3,r1,STACK_FRAME_OVERHEAD
......
arch/powerpc/kernel/hw_breakpoint.c 0 → 100644
View file @ cdd854bc
/*
* HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
* using the CPU's debug registers. Derived from
* "arch/x86/kernel/hw_breakpoint.c"
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright 2010 IBM Corporation
* Author: K.Prasad <prasad@linux.vnet.ibm.com>
*
*/
#include <linux/hw_breakpoint.h>
#include <linux/notifier.h>
#include <linux/kprobes.h>
#include <linux/percpu.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <asm/hw_breakpoint.h>
#include <asm/processor.h>
#include <asm/sstep.h>
#include <asm/uaccess.h>
/*
* Stores the breakpoints currently in use on each breakpoint address
* register for every cpu
*/
static DEFINE_PER_CPU(struct perf_event *, bp_per_reg);
/*
* Returns total number of data or instruction breakpoints available.
*/
int hw_breakpoint_slots(int type)
{
if (type == TYPE_DATA)
return HBP_NUM;
return 0; /* no instruction breakpoints available */
}
/*
* Install a perf counter breakpoint.
*
* We seek a free debug address register and use it for this
* breakpoint.
*
* Atomic: we hold the counter->ctx->lock and we only handle variables
* and registers local to this cpu.
*/
int arch_install_hw_breakpoint(struct perf_event *bp)
{
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
struct perf_event **slot = &__get_cpu_var(bp_per_reg);
*slot = bp;
/*
* Do not install DABR values if the instruction must be single-stepped.
* If so, DABR will be populated in single_step_dabr_instruction().
*/
if (current->thread.last_hit_ubp != bp)
set_dabr(info->address | info->type | DABR_TRANSLATION);
return 0;
}
/*
* Uninstall the breakpoint contained in the given counter.
*
* First we search the debug address register it uses and then we disable
* it.
*
* Atomic: we hold the counter->ctx->lock and we only handle variables
* and registers local to this cpu.
*/
void arch_uninstall_hw_breakpoint(struct perf_event *bp)
{
struct perf_event **slot = &__get_cpu_var(bp_per_reg);
if (*slot != bp) {
WARN_ONCE(1, "Can't find the breakpoint");
return;
}
*slot = NULL;
set_dabr(0);
}
/*
* Perform cleanup of arch-specific counters during unregistration
* of the perf-event
*/
void arch_unregister_hw_breakpoint(struct perf_event *bp)
{
/*
* If the breakpoint is unregistered between a hw_breakpoint_handler()
* and the single_step_dabr_instruction(), then cleanup the breakpoint
* restoration variables to prevent dangling pointers.
*/
if (bp->ctx->task)
bp->ctx->task->thread.last_hit_ubp = NULL;
}
/*
* Check for virtual address in kernel space.
*/
int arch_check_bp_in_kernelspace(struct perf_event *bp)
{
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
return is_kernel_addr(info->address);
}
int arch_bp_generic_fields(int type, int *gen_bp_type)
{
switch (type) {
case DABR_DATA_READ:
*gen_bp_type = HW_BREAKPOINT_R;
break;
case DABR_DATA_WRITE:
*gen_bp_type = HW_BREAKPOINT_W;
break;
case (DABR_DATA_WRITE | DABR_DATA_READ):
*gen_bp_type = (HW_BREAKPOINT_W | HW_BREAKPOINT_R);
break;
default:
return -EINVAL;
}
return 0;
}
/*
* Validate the arch-specific HW Breakpoint register settings
*/
int arch_validate_hwbkpt_settings(struct perf_event *bp)
{
int ret = -EINVAL;
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
if (!bp)
return ret;
switch (bp->attr.bp_type) {
case HW_BREAKPOINT_R:
info->type = DABR_DATA_READ;
break;
case HW_BREAKPOINT_W:
info->type = DABR_DATA_WRITE;
break;
case HW_BREAKPOINT_R | HW_BREAKPOINT_W:
info->type = (DABR_DATA_READ | DABR_DATA_WRITE);
break;
default:
return ret;
}
info->address = bp->attr.bp_addr;
info->len = bp->attr.bp_len;
/*
* Since breakpoint length can be a maximum of HW_BREAKPOINT_LEN(8)
* and breakpoint addresses are aligned to nearest double-word
* HW_BREAKPOINT_ALIGN by rounding off to the lower address, the
* 'symbolsize' should satisfy the check below.
*/
if (info->len >
(HW_BREAKPOINT_LEN - (info->address & HW_BREAKPOINT_ALIGN)))
return -EINVAL;
return 0;
}
/*
* Restores the breakpoint on the debug registers.
* Invoke this function if it is known that the execution context is
* about to change to cause loss of MSR_SE settings.
*/
void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs)
{
struct arch_hw_breakpoint *info;
if (likely(!tsk->thread.last_hit_ubp))
return;
info = counter_arch_bp(tsk->thread.last_hit_ubp);
regs->msr &= ~MSR_SE;
set_dabr(info->address | info->type | DABR_TRANSLATION);
tsk->thread.last_hit_ubp = NULL;
}
/*
* Handle debug exception notifications.
*/
int __kprobes hw_breakpoint_handler(struct die_args *args)
{
int rc = NOTIFY_STOP;
struct perf_event *bp;
struct pt_regs *regs = args->regs;
int stepped = 1;
struct arch_hw_breakpoint *info;
unsigned int instr;
unsigned long dar = regs->dar;
/* Disable breakpoints during exception handling */
set_dabr(0);
/*
* The counter may be concurrently released but that can only
* occur from a call_rcu() path. We can then safely fetch
* the breakpoint, use its callback, touch its counter
* while we are in an rcu_read_lock() path.
*/
rcu_read_lock();
bp = __get_cpu_var(bp_per_reg);
if (!bp)
goto out;
info = counter_arch_bp(bp);
/*
* Return early after invoking user-callback function without restoring
* DABR if the breakpoint is from ptrace which always operates in
* one-shot mode. The ptrace-ed process will receive the SIGTRAP signal
* generated in do_dabr().
*/
if (bp->overflow_handler == ptrace_triggered) {
perf_bp_event(bp, regs);
rc = NOTIFY_DONE;
goto out;
}
/*
* Verify if dar lies within the address range occupied by the symbol
* being watched to filter extraneous exceptions. If it doesn't,
* we still need to single-step the instruction, but we don't
* generate an event.
*/
info->extraneous_interrupt = !((bp->attr.bp_addr <= dar) &&
(dar - bp->attr.bp_addr < bp->attr.bp_len));
/* Do not emulate user-space instructions, instead single-step them */
if (user_mode(regs)) {
bp->ctx->task->thread.last_hit_ubp = bp;
regs->msr |= MSR_SE;
goto out;
}
stepped = 0;
instr = 0;
if (!__get_user_inatomic(instr, (unsigned int *) regs->nip))
stepped = emulate_step(regs, instr);
/*
* emulate_step() could not execute it. We've failed in reliably
* handling the hw-breakpoint. Unregister it and throw a warning
* message to let the user know about it.
*/
if (!stepped) {
WARN(1, "Unable to handle hardware breakpoint. Breakpoint at "
"0x%lx will be disabled.", info->address);
perf_event_disable(bp);
goto out;
}
/*
* As a policy, the callback is invoked in a 'trigger-after-execute'
* fashion
*/
if (!info->extraneous_interrupt)
perf_bp_event(bp, regs);
set_dabr(info->address | info->type | DABR_TRANSLATION);
out:
rcu_read_unlock();
return rc;
}
/*
* Handle single-step exceptions following a DABR hit.
*/
int __kprobes single_step_dabr_instruction(struct die_args *args)
{
struct pt_regs *regs = args->regs;
struct perf_event *bp = NULL;
struct arch_hw_breakpoint *bp_info;
bp = current->thread.last_hit_ubp;
/*
* Check if we are single-stepping as a result of a
* previous HW Breakpoint exception
*/
if (!bp)
return NOTIFY_DONE;
bp_info = counter_arch_bp(bp);
/*
* We shall invoke the user-defined callback function in the single
* stepping handler to confirm to 'trigger-after-execute' semantics
*/
if (!bp_info->extraneous_interrupt)
perf_bp_event(bp, regs);
set_dabr(bp_info->address | bp_info->type | DABR_TRANSLATION);
current->thread.last_hit_ubp = NULL;
/*
* If the process was being single-stepped by ptrace, let the
* other single-step actions occur (e.g. generate SIGTRAP).
*/
if (test_thread_flag(TIF_SINGLESTEP))
return NOTIFY_DONE;
return NOTIFY_STOP;
}
/*
* Handle debug exception notifications.
*/
int __kprobes hw_breakpoint_exceptions_notify(
struct notifier_block *unused, unsigned long val, void *data)
{
int ret = NOTIFY_DONE;
switch (val) {
case DIE_DABR_MATCH:
ret = hw_breakpoint_handler(data);
break;
case DIE_SSTEP:
ret = single_step_dabr_instruction(data);
break;
}
return ret;
}
/*
* Release the user breakpoints used by ptrace
*/
void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
{
struct thread_struct *t = &tsk->thread;
unregister_hw_breakpoint(t->ptrace_bps[0]);
t->ptrace_bps[0] = NULL;
}
void hw_breakpoint_pmu_read(struct perf_event *bp)
{
/* TODO */
}
arch/powerpc/kernel/idle_book3e.S 0 → 100644
View file @ cdd854bc
/*
* Copyright 2010 IBM Corp, Benjamin Herrenschmidt <benh@kernel.crashing.org>
*
* Generic idle routine for Book3E processors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/threads.h>
#include <asm/reg.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/ppc-opcode.h>
#include <asm/processor.h>
#include <asm/thread_info.h>
/* 64-bit version only for now */
#ifdef CONFIG_PPC64
_GLOBAL(book3e_idle)
/* Save LR for later */
mflr r0
std r0,16(r1)
/* Hard disable interrupts */
wrteei 0
/* Now check if an interrupt came in while we were soft disabled
* since we may otherwise lose it (doorbells etc...). We know
* that since PACAHARDIRQEN will have been cleared in that case.
*/
lbz r3,PACAHARDIRQEN(r13)
cmpwi cr0,r3,0
beqlr
/* Now we are going to mark ourselves as soft and hard enables in
* order to be able to take interrupts while asleep. We inform lockdep
* of that. We don't actually turn interrupts on just yet tho.
*/
#ifdef CONFIG_TRACE_IRQFLAGS
stdu r1,-128(r1)
bl .trace_hardirqs_on
#endif
li r0,1
stb r0,PACASOFTIRQEN(r13)
stb r0,PACAHARDIRQEN(r13)
/* Interrupts will make use return to LR, so get something we want
* in there
*/
bl 1f
/* Hard disable interrupts again */
wrteei 0
/* Mark them off again in the PACA as well */
li r0,0
stb r0,PACASOFTIRQEN(r13)
stb r0,PACAHARDIRQEN(r13)
/* Tell lockdep about it */
#ifdef CONFIG_TRACE_IRQFLAGS
bl .trace_hardirqs_off
addi r1,r1,128
#endif
ld r0,16(r1)
mtlr r0
blr
1: /* Let's set the _TLF_NAPPING flag so interrupts make us return
* to the right spot
*/
clrrdi r11,r1,THREAD_SHIFT
ld r10,TI_LOCAL_FLAGS(r11)
ori r10,r10,_TLF_NAPPING
std r10,TI_LOCAL_FLAGS(r11)
/* We can now re-enable hard interrupts and go to sleep */
wrteei 1
1: PPC_WAIT(0)
b 1b
#endif /* CONFIG_PPC64 */
arch/powerpc/kernel/irq.c
View file @ cdd854bc
......@@ -64,6 +64,8 @@
#include <asm/ptrace.h>
#include <asm/machdep.h>
#include <asm/udbg.h>
#include <asm/dbell.h>
#ifdef CONFIG_PPC64
#include <asm/paca.h>
#include <asm/firmware.h>
......@@ -153,14 +155,28 @@ notrace void raw_local_irq_restore(unsigned long en)
if (get_hard_enabled())
return;
#if defined(CONFIG_BOOKE) && defined(CONFIG_SMP)
/* Check for pending doorbell interrupts and resend to ourself */
doorbell_check_self();
#endif
/*
* Need to hard-enable interrupts here. Since currently disabled,
* no need to take further asm precautions against preemption; but
* use local_paca instead of get_paca() to avoid preemption checking.
*/
local_paca->hard_enabled = en;
#ifndef CONFIG_BOOKE
/* On server, re-trigger the decrementer if it went negative since
* some processors only trigger on edge transitions of the sign bit.
*
* BookE has a level sensitive decrementer (latches in TSR) so we
* don't need that
*/
if ((int)mfspr(SPRN_DEC) < 0)
mtspr(SPRN_DEC, 1);
#endif /* CONFIG_BOOKE */
/*
* Force the delivery of pending soft-disabled interrupts on PS3.
......
arch/powerpc/kernel/machine_kexec.c
View file @ cdd854bc
......@@ -45,6 +45,18 @@ void machine_kexec_cleanup(struct kimage *image)
ppc_md.machine_kexec_cleanup(image);
}
void arch_crash_save_vmcoreinfo(void)
{
#ifdef CONFIG_NEED_MULTIPLE_NODES
VMCOREINFO_SYMBOL(node_data);
VMCOREINFO_LENGTH(node_data, MAX_NUMNODES);
#endif
#ifndef CONFIG_NEED_MULTIPLE_NODES
VMCOREINFO_SYMBOL(contig_page_data);
#endif
}
/*
* Do not allocate memory (or fail in any way) in machine_kexec().
* We are past the point of no return, committed to rebooting now.
......@@ -144,24 +156,24 @@ int overlaps_crashkernel(unsigned long start, unsigned long size)
}
/* Values we need to export to the second kernel via the device tree. */
static unsigned long kernel_end;
static unsigned long crashk_size;
static phys_addr_t kernel_end;
static phys_addr_t crashk_size;
static struct property kernel_end_prop = {
.name = "linux,kernel-end",
.length = sizeof(unsigned long),
.length = sizeof(phys_addr_t),
.value = &kernel_end,
};
static struct property crashk_base_prop = {
.name = "linux,crashkernel-base",
.length = sizeof(unsigned long),
.length = sizeof(phys_addr_t),
.value = &crashk_res.start,
};
static struct property crashk_size_prop = {
.name = "linux,crashkernel-size",
.length = sizeof(unsigned long),
.length = sizeof(phys_addr_t),
.value = &crashk_size,
};
......
arch/powerpc/kernel/machine_kexec_64.c
View file @ cdd854bc
......@@ -15,6 +15,8 @@
#include <linux/thread_info.h>
#include <linux/init_task.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/cpu.h>
#include <asm/page.h>
#include <asm/current.h>
......@@ -25,6 +27,7 @@
#include <asm/sections.h> /* _end */
#include <asm/prom.h>
#include <asm/smp.h>
#include <asm/hw_breakpoint.h>
int default_machine_kexec_prepare(struct kimage *image)
{
......@@ -165,6 +168,7 @@ static void kexec_smp_down(void *arg)
while(kexec_all_irq_disabled == 0)
cpu_relax();
mb(); /* make sure all irqs are disabled before this */
hw_breakpoint_disable();
/*
* Now every CPU has IRQs off, we can clear out any pending
* IPIs and be sure that no more will come in after this.
......@@ -180,8 +184,22 @@ static void kexec_prepare_cpus_wait(int wait_state)
{
int my_cpu, i, notified=-1;
hw_breakpoint_disable();
my_cpu = get_cpu();
/* Make sure each CPU has atleast made it to the state we need */
/* Make sure each CPU has at least made it to the state we need.
*
* FIXME: There is a (slim) chance of a problem if not all of the CPUs
* are correctly onlined. If somehow we start a CPU on boot with RTAS
* start-cpu, but somehow that CPU doesn't write callin_cpu_map[] in
* time, the boot CPU will timeout. If it does eventually execute
* stuff, the secondary will start up (paca[].cpu_start was written) and
* get into a peculiar state. If the platform supports
* smp_ops->take_timebase(), the secondary CPU will probably be spinning
* in there. If not (i.e. pseries), the secondary will continue on and
* try to online itself/idle/etc. If it survives that, we need to find
* these possible-but-not-online-but-should-be CPUs and chaperone them
* into kexec_smp_wait().
*/
for_each_online_cpu(i) {
if (i == my_cpu)
continue;
......@@ -189,9 +207,9 @@ static void kexec_prepare_cpus_wait(int wait_state)
while (paca[i].kexec_state < wait_state) {
barrier();
if (i != notified) {
printk( "kexec: waiting for cpu %d (physical"
" %d) to enter %i state\n",
i, paca[i].hw_cpu_id, wait_state);
printk(KERN_INFO "kexec: waiting for cpu %d "
"(physical %d) to enter %i state\n",
i, paca[i].hw_cpu_id, wait_state);
notified = i;
}
}
......@@ -199,9 +217,32 @@ static void kexec_prepare_cpus_wait(int wait_state)
mb();
}
static void kexec_prepare_cpus(void)
/*
* We need to make sure each present CPU is online. The next kernel will scan
* the device tree and assume primary threads are online and query secondary
* threads via RTAS to online them if required. If we don't online primary
* threads, they will be stuck. However, we also online secondary threads as we
* may be using 'cede offline'. In this case RTAS doesn't see the secondary
* threads as offline -- and again, these CPUs will be stuck.
*
* So, we online all CPUs that should be running, including secondary threads.
*/
static void wake_offline_cpus(void)
{
int cpu = 0;
for_each_present_cpu(cpu) {
if (!cpu_online(cpu)) {
printk(KERN_INFO "kexec: Waking offline cpu %d.\n",
cpu);
cpu_up(cpu);
}
}
}
static void kexec_prepare_cpus(void)
{
wake_offline_cpus();
smp_call_function(kexec_smp_down, NULL, /* wait */0);
local_irq_disable();
mb(); /* make sure IRQs are disabled before we say they are */
......@@ -215,7 +256,10 @@ static void kexec_prepare_cpus(void)
if (ppc_md.kexec_cpu_down)
ppc_md.kexec_cpu_down(0, 0);
/* Before removing MMU mapings make sure all CPUs have entered real mode */
/*
* Before removing MMU mappings make sure all CPUs have entered real
* mode:
*/
kexec_prepare_cpus_wait(KEXEC_STATE_REAL_MODE);
put_cpu();
......@@ -257,6 +301,12 @@ static void kexec_prepare_cpus(void)
static union thread_union kexec_stack __init_task_data =
{ };
/*
* For similar reasons to the stack above, the kexecing CPU needs to be on a
* static PACA; we switch to kexec_paca.
*/
struct paca_struct kexec_paca;
/* Our assembly helper, in kexec_stub.S */
extern NORET_TYPE void kexec_sequence(void *newstack, unsigned long start,
void *image, void *control,
......@@ -278,12 +328,28 @@ void default_machine_kexec(struct kimage *image)
if (crashing_cpu == -1)
kexec_prepare_cpus();
pr_debug("kexec: Starting switchover sequence.\n");
/* switch to a staticly allocated stack. Based on irq stack code.
* XXX: the task struct will likely be invalid once we do the copy!
*/
kexec_stack.thread_info.task = current_thread_info()->task;
kexec_stack.thread_info.flags = 0;
/* We need a static PACA, too; copy this CPU's PACA over and switch to
* it. Also poison per_cpu_offset to catch anyone using non-static
* data.
*/
memcpy(&kexec_paca, get_paca(), sizeof(struct paca_struct));
kexec_paca.data_offset = 0xedeaddeadeeeeeeeUL;
paca = (struct paca_struct *)RELOC_HIDE(&kexec_paca, 0) -
kexec_paca.paca_index;
setup_paca(&kexec_paca);
/* XXX: If anyone does 'dynamic lppacas' this will also need to be
* switched to a static version!
*/
/* Some things are best done in assembly. Finding globals with
* a toc is easier in C, so pass in what we can.
*/
......
arch/powerpc/kernel/paca.c
View file @ cdd854bc
......@@ -105,6 +105,16 @@ void __init initialise_paca(struct paca_struct *new_paca, int cpu)
#endif /* CONFIG_PPC_STD_MMU_64 */
}
/* Put the paca pointer into r13 and SPRG_PACA */
void setup_paca(struct paca_struct *new_paca)
{
local_paca = new_paca;
mtspr(SPRN_SPRG_PACA, local_paca);
#ifdef CONFIG_PPC_BOOK3E
mtspr(SPRN_SPRG_TLB_EXFRAME, local_paca->extlb);
#endif
}
static int __initdata paca_size;
void __init allocate_pacas(void)
......
arch/powerpc/kernel/process.c
View file @ cdd854bc
......@@ -37,6 +37,7 @@
#include <linux/kernel_stat.h>
#include <linux/personality.h>
#include <linux/random.h>
#include <linux/hw_breakpoint.h>
#include <asm/pgtable.h>
#include <asm/uaccess.h>
......@@ -462,14 +463,42 @@ struct task_struct *__switch_to(struct task_struct *prev,
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
switch_booke_debug_regs(&new->thread);
#else
/*
* For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
* schedule DABR
*/
#ifndef CONFIG_HAVE_HW_BREAKPOINT
if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr))
set_dabr(new->thread.dabr);
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
#endif
new_thread = &new->thread;
old_thread = &current->thread;
#if defined(CONFIG_PPC_BOOK3E_64)
/* XXX Current Book3E code doesn't deal with kernel side DBCR0,
* we always hold the user values, so we set it now.
*
* However, we ensure the kernel MSR:DE is appropriately cleared too
* to avoid spurrious single step exceptions in the kernel.
*
* This will have to change to merge with the ppc32 code at some point,
* but I don't like much what ppc32 is doing today so there's some
* thinking needed there
*/
if ((new_thread->dbcr0 | old_thread->dbcr0) & DBCR0_IDM) {
u32 dbcr0;
mtmsr(mfmsr() & ~MSR_DE);
isync();
dbcr0 = mfspr(SPRN_DBCR0);
dbcr0 = (dbcr0 & DBCR0_EDM) | new_thread->dbcr0;
mtspr(SPRN_DBCR0, dbcr0);
}
#endif /* CONFIG_PPC64_BOOK3E */
#ifdef CONFIG_PPC64
/*
* Collect processor utilization data per process
......@@ -642,7 +671,11 @@ void flush_thread(void)
{
discard_lazy_cpu_state();
#ifdef CONFIG_HAVE_HW_BREAKPOINTS
flush_ptrace_hw_breakpoint(current);
#else /* CONFIG_HAVE_HW_BREAKPOINTS */
set_debug_reg_defaults(&current->thread);
#endif /* CONFIG_HAVE_HW_BREAKPOINTS */
}
void
......@@ -660,6 +693,9 @@ void prepare_to_copy(struct task_struct *tsk)
flush_altivec_to_thread(current);
flush_vsx_to_thread(current);
flush_spe_to_thread(current);
#ifdef CONFIG_HAVE_HW_BREAKPOINT
flush_ptrace_hw_breakpoint(tsk);
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
}
/*
......
arch/powerpc/kernel/prom_init.c
View file @ cdd854bc
......@@ -311,6 +311,24 @@ static void __init prom_print_hex(unsigned long val)
call_prom("write", 3, 1, _prom->stdout, buf, nibbles);
}
/* max number of decimal digits in an unsigned long */
#define UL_DIGITS 21
static void __init prom_print_dec(unsigned long val)
{
int i, size;
char buf[UL_DIGITS+1];
struct prom_t *_prom = &RELOC(prom);
for (i = UL_DIGITS-1; i >= 0; i--) {
buf[i] = (val % 10) + '0';
val = val/10;
if (val == 0)
break;
}
/* shift stuff down */
size = UL_DIGITS - i;
call_prom("write", 3, 1, _prom->stdout, buf+i, size);
}
static void __init prom_printf(const char *format, ...)
{
......@@ -350,6 +368,14 @@ static void __init prom_printf(const char *format, ...)
v = va_arg(args, unsigned long);
prom_print_hex(v);
break;
case 'l':
++q;
if (*q == 'u') { /* '%lu' */
++q;
v = va_arg(args, unsigned long);
prom_print_dec(v);
}
break;
}
}
}
......@@ -835,11 +861,11 @@ static int __init prom_count_smt_threads(void)
if (plen == PROM_ERROR)
break;
plen >>= 2;
prom_debug("Found 0x%x smt threads per core\n", (unsigned long)plen);
prom_debug("Found %lu smt threads per core\n", (unsigned long)plen);
/* Sanity check */
if (plen < 1 || plen > 64) {
prom_printf("Threads per core 0x%x out of bounds, assuming 1\n",
prom_printf("Threads per core %lu out of bounds, assuming 1\n",
(unsigned long)plen);
return 1;
}
......@@ -869,12 +895,12 @@ static void __init prom_send_capabilities(void)
cores = (u32 *)PTRRELOC(&ibm_architecture_vec[IBM_ARCH_VEC_NRCORES_OFFSET]);
if (*cores != NR_CPUS) {
prom_printf("WARNING ! "
"ibm_architecture_vec structure inconsistent: 0x%x !\n",
"ibm_architecture_vec structure inconsistent: %lu!\n",
*cores);
} else {
*cores = DIV_ROUND_UP(NR_CPUS, prom_count_smt_threads());
prom_printf("Max number of cores passed to firmware: 0x%x\n",
(unsigned long)*cores);
prom_printf("Max number of cores passed to firmware: %lu (NR_CPUS = %lu)\n",
*cores, NR_CPUS);
}
/* try calling the ibm,client-architecture-support method */
......@@ -1482,7 +1508,7 @@ static void __init prom_hold_cpus(void)
reg = -1;
prom_getprop(node, "reg", &reg, sizeof(reg));
prom_debug("cpu hw idx = 0x%x\n", reg);
prom_debug("cpu hw idx = %lu\n", reg);
/* Init the acknowledge var which will be reset by
* the secondary cpu when it awakens from its OF
......@@ -1492,7 +1518,7 @@ static void __init prom_hold_cpus(void)
if (reg != _prom->cpu) {
/* Primary Thread of non-boot cpu */
prom_printf("starting cpu hw idx %x... ", reg);
prom_printf("starting cpu hw idx %lu... ", reg);
call_prom("start-cpu", 3, 0, node,
secondary_hold, reg);
......@@ -1507,7 +1533,7 @@ static void __init prom_hold_cpus(void)
}
#ifdef CONFIG_SMP
else
prom_printf("boot cpu hw idx %x\n", reg);
prom_printf("boot cpu hw idx %lu\n", reg);
#endif /* CONFIG_SMP */
}
......@@ -2420,7 +2446,7 @@ static void __init prom_find_boot_cpu(void)
prom_getprop(cpu_pkg, "reg", &getprop_rval, sizeof(getprop_rval));
_prom->cpu = getprop_rval;
prom_debug("Booting CPU hw index = 0x%x\n", _prom->cpu);
prom_debug("Booting CPU hw index = %lu\n", _prom->cpu);
}
static void __init prom_check_initrd(unsigned long r3, unsigned long r4)
......
arch/powerpc/kernel/ptrace.c
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arch/powerpc/kernel/rtas.c
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arch/powerpc/kernel/setup-common.c
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......@@ -94,6 +94,10 @@ struct screen_info screen_info = {
.orig_video_points = 16
};
/* Variables required to store legacy IO irq routing */
int of_i8042_kbd_irq;
int of_i8042_aux_irq;
#ifdef __DO_IRQ_CANON
/* XXX should go elsewhere eventually */
int ppc_do_canonicalize_irqs;
......@@ -575,6 +579,15 @@ int check_legacy_ioport(unsigned long base_port)
np = of_find_compatible_node(NULL, NULL, "pnpPNP,f03");
if (np) {
parent = of_get_parent(np);
of_i8042_kbd_irq = irq_of_parse_and_map(parent, 0);
if (!of_i8042_kbd_irq)
of_i8042_kbd_irq = 1;
of_i8042_aux_irq = irq_of_parse_and_map(parent, 1);
if (!of_i8042_aux_irq)
of_i8042_aux_irq = 12;
of_node_put(np);
np = parent;
break;
......
arch/powerpc/kernel/setup_64.c
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arch/powerpc/kernel/signal.c
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......@@ -11,6 +11,7 @@
#include <linux/tracehook.h>
#include <linux/signal.h>
#include <asm/hw_breakpoint.h>
#include <asm/uaccess.h>
#include <asm/unistd.h>
......@@ -149,6 +150,8 @@ static int do_signal_pending(sigset_t *oldset, struct pt_regs *regs)
if (current->thread.dabr)
set_dabr(current->thread.dabr);
#endif
/* Re-enable the breakpoints for the signal stack */
thread_change_pc(current, regs);
if (is32) {
if (ka.sa.sa_flags & SA_SIGINFO)
......
arch/powerpc/kernel/smp.c
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arch/powerpc/kernel/time.c
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arch/powerpc/kernel/traps.c
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arch/powerpc/kernel/vdso32/gettimeofday.S
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arch/powerpc/kernel/vdso64/gettimeofday.S
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arch/powerpc/kvm/timing.c
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......@@ -182,7 +182,7 @@ static ssize_t kvmppc_exit_timing_write(struct file *file,
}
if (c == 'c') {
struct seq_file *seqf = (struct seq_file *)file->private_data;
struct seq_file *seqf = file->private_data;
struct kvm_vcpu *vcpu = seqf->private;
/* Write does not affect our buffers previously generated with
* show. seq_file is locked here to prevent races of init with
......
arch/powerpc/lib/Makefile
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arch/powerpc/lib/sstep.c
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arch/powerpc/mm/fsl_booke_mmu.c
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arch/powerpc/mm/numa.c
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arch/powerpc/mm/pgtable.c
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arch/powerpc/mm/tlb_hash32.c
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arch/powerpc/mm/tlb_nohash.c
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arch/powerpc/oprofile/Makefile
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arch/powerpc/oprofile/common.c
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arch/powerpc/platforms/40x/Kconfig
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arch/powerpc/platforms/512x/Kconfig
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arch/powerpc/platforms/512x/Makefile
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arch/powerpc/platforms/512x/clock.c
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arch/powerpc/platforms/512x/mpc5121_ads.c
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arch/powerpc/platforms/512x/mpc512x.h
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arch/powerpc/platforms/52xx/lite5200_pm.c
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arch/powerpc/platforms/52xx/mpc52xx_pm.c
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arch/powerpc/platforms/83xx/Kconfig
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arch/powerpc/platforms/83xx/Makefile
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arch/powerpc/platforms/83xx/mpc830x_rdb.c 0 → 100644
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arch/powerpc/platforms/85xx/Kconfig
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arch/powerpc/platforms/85xx/Makefile
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arch/powerpc/platforms/85xx/mpc85xx_mds.c
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arch/powerpc/platforms/85xx/p1022_ds.c 0 → 100644
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arch/powerpc/platforms/85xx/smp.c
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arch/powerpc/platforms/85xx/tqm85xx.c
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arch/powerpc/platforms/8xx/Kconfig
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arch/powerpc/platforms/8xx/Makefile
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arch/powerpc/platforms/8xx/tqm8xx_setup.c 0 → 100644
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arch/powerpc/platforms/iseries/vio.c
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arch/powerpc/platforms/powermac/feature.c
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arch/powerpc/platforms/pseries/Makefile
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arch/powerpc/platforms/pseries/dlpar.c
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arch/powerpc/platforms/pseries/eeh_cache.c
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arch/powerpc/platforms/pseries/ras.c
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arch/powerpc/platforms/pseries/reconfig.c
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arch/powerpc/platforms/pseries/xics.c
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arch/powerpc/sysdev/fsl_pci.c
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arch/powerpc/sysdev/fsl_soc.h
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arch/powerpc/sysdev/mpic.c
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arch/powerpc/sysdev/mpic.h
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arch/powerpc/xmon/xmon.c
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drivers/char/hvc_console.c
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drivers/i2c/busses/i2c-mpc.c
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drivers/input/serio/i8042-io.h
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include/linux/pci_ids.h
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kernel/hw_breakpoint.c
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