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Commit ce136e15 authored by XueBing Chen's avatar XueBing Chen Committed by Alex Deucher
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drm/radeon: Clean up errors in si.c 

Fix the following errors reported by checkpatch:

ERROR: that open brace { should be on the previous line
ERROR: trailing statements should be on next lineo
Signed-off-by: default avatarXueBing Chen <chenxb_99091@126.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 17c31edf
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Showing with 22 additions and 41 deletions
drivers/gpu/drm/radeon/si.c
View file @ ce136e15
...@@ -138,8 +138,7 @@ static void si_fini_pg(struct radeon_device *rdev); ...@@ -138,8 +138,7 @@ static void si_fini_pg(struct radeon_device *rdev);
static void si_fini_cg(struct radeon_device *rdev); static void si_fini_cg(struct radeon_device *rdev);
static void si_rlc_stop(struct radeon_device *rdev); static void si_rlc_stop(struct radeon_device *rdev);
static const u32 crtc_offsets[] = static const u32 crtc_offsets[] = {
{
EVERGREEN_CRTC0_REGISTER_OFFSET, EVERGREEN_CRTC0_REGISTER_OFFSET,
EVERGREEN_CRTC1_REGISTER_OFFSET, EVERGREEN_CRTC1_REGISTER_OFFSET,
EVERGREEN_CRTC2_REGISTER_OFFSET, EVERGREEN_CRTC2_REGISTER_OFFSET,
...@@ -148,8 +147,7 @@ static const u32 crtc_offsets[] = ...@@ -148,8 +147,7 @@ static const u32 crtc_offsets[] =
EVERGREEN_CRTC5_REGISTER_OFFSET EVERGREEN_CRTC5_REGISTER_OFFSET
}; };
static const u32 si_disp_int_status[] = static const u32 si_disp_int_status[] = {
{
DISP_INTERRUPT_STATUS, DISP_INTERRUPT_STATUS,
DISP_INTERRUPT_STATUS_CONTINUE, DISP_INTERRUPT_STATUS_CONTINUE,
DISP_INTERRUPT_STATUS_CONTINUE2, DISP_INTERRUPT_STATUS_CONTINUE2,
...@@ -162,8 +160,7 @@ static const u32 si_disp_int_status[] = ...@@ -162,8 +160,7 @@ static const u32 si_disp_int_status[] =
#define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc)) #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
#define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc)) #define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc))
static const u32 verde_rlc_save_restore_register_list[] = static const u32 verde_rlc_save_restore_register_list[] = {
{
(0x8000 << 16) | (0x98f4 >> 2), (0x8000 << 16) | (0x98f4 >> 2),
0x00000000, 0x00000000,
(0x8040 << 16) | (0x98f4 >> 2), (0x8040 << 16) | (0x98f4 >> 2),
...@@ -384,8 +381,7 @@ static const u32 verde_rlc_save_restore_register_list[] = ...@@ -384,8 +381,7 @@ static const u32 verde_rlc_save_restore_register_list[] =
0x00000000 0x00000000
}; };
static const u32 tahiti_golden_rlc_registers[] = static const u32 tahiti_golden_rlc_registers[] = {
{
0xc424, 0xffffffff, 0x00601005, 0xc424, 0xffffffff, 0x00601005,
0xc47c, 0xffffffff, 0x10104040, 0xc47c, 0xffffffff, 0x10104040,
0xc488, 0xffffffff, 0x0100000a, 0xc488, 0xffffffff, 0x0100000a,
...@@ -394,8 +390,7 @@ static const u32 tahiti_golden_rlc_registers[] = ...@@ -394,8 +390,7 @@ static const u32 tahiti_golden_rlc_registers[] =
0xf4a8, 0xffffffff, 0x00000000 0xf4a8, 0xffffffff, 0x00000000
}; };
static const u32 tahiti_golden_registers[] = static const u32 tahiti_golden_registers[] = {
{
0x9a10, 0x00010000, 0x00018208, 0x9a10, 0x00010000, 0x00018208,
0x9830, 0xffffffff, 0x00000000, 0x9830, 0xffffffff, 0x00000000,
0x9834, 0xf00fffff, 0x00000400, 0x9834, 0xf00fffff, 0x00000400,
...@@ -429,13 +424,11 @@ static const u32 tahiti_golden_registers[] = ...@@ -429,13 +424,11 @@ static const u32 tahiti_golden_registers[] =
0x15c0, 0x000c0fc0, 0x000c0400 0x15c0, 0x000c0fc0, 0x000c0400
}; };
static const u32 tahiti_golden_registers2[] = static const u32 tahiti_golden_registers2[] = {
{
0xc64, 0x00000001, 0x00000001 0xc64, 0x00000001, 0x00000001
}; };
static const u32 pitcairn_golden_rlc_registers[] = static const u32 pitcairn_golden_rlc_registers[] = {
{
0xc424, 0xffffffff, 0x00601004, 0xc424, 0xffffffff, 0x00601004,
0xc47c, 0xffffffff, 0x10102020, 0xc47c, 0xffffffff, 0x10102020,
0xc488, 0xffffffff, 0x01000020, 0xc488, 0xffffffff, 0x01000020,
...@@ -443,8 +436,7 @@ static const u32 pitcairn_golden_rlc_registers[] = ...@@ -443,8 +436,7 @@ static const u32 pitcairn_golden_rlc_registers[] =
0xc30c, 0xffffffff, 0x800000a4 0xc30c, 0xffffffff, 0x800000a4
}; };
static const u32 pitcairn_golden_registers[] = static const u32 pitcairn_golden_registers[] = {
{
0x9a10, 0x00010000, 0x00018208, 0x9a10, 0x00010000, 0x00018208,
0x9830, 0xffffffff, 0x00000000, 0x9830, 0xffffffff, 0x00000000,
0x9834, 0xf00fffff, 0x00000400, 0x9834, 0xf00fffff, 0x00000400,
...@@ -474,8 +466,7 @@ static const u32 pitcairn_golden_registers[] = ...@@ -474,8 +466,7 @@ static const u32 pitcairn_golden_registers[] =
0x15c0, 0x000c0fc0, 0x000c0400 0x15c0, 0x000c0fc0, 0x000c0400
}; };
static const u32 verde_golden_rlc_registers[] = static const u32 verde_golden_rlc_registers[] = {
{
0xc424, 0xffffffff, 0x033f1005, 0xc424, 0xffffffff, 0x033f1005,
0xc47c, 0xffffffff, 0x10808020, 0xc47c, 0xffffffff, 0x10808020,
0xc488, 0xffffffff, 0x00800008, 0xc488, 0xffffffff, 0x00800008,
...@@ -483,8 +474,7 @@ static const u32 verde_golden_rlc_registers[] = ...@@ -483,8 +474,7 @@ static const u32 verde_golden_rlc_registers[] =
0xc30c, 0xffffffff, 0x80010014 0xc30c, 0xffffffff, 0x80010014
}; };
static const u32 verde_golden_registers[] = static const u32 verde_golden_registers[] = {
{
0x9a10, 0x00010000, 0x00018208, 0x9a10, 0x00010000, 0x00018208,
0x9830, 0xffffffff, 0x00000000, 0x9830, 0xffffffff, 0x00000000,
0x9834, 0xf00fffff, 0x00000400, 0x9834, 0xf00fffff, 0x00000400,
...@@ -539,8 +529,7 @@ static const u32 verde_golden_registers[] = ...@@ -539,8 +529,7 @@ static const u32 verde_golden_registers[] =
0x15c0, 0x000c0fc0, 0x000c0400 0x15c0, 0x000c0fc0, 0x000c0400
}; };
static const u32 oland_golden_rlc_registers[] = static const u32 oland_golden_rlc_registers[] = {
{
0xc424, 0xffffffff, 0x00601005, 0xc424, 0xffffffff, 0x00601005,
0xc47c, 0xffffffff, 0x10104040, 0xc47c, 0xffffffff, 0x10104040,
0xc488, 0xffffffff, 0x0100000a, 0xc488, 0xffffffff, 0x0100000a,
...@@ -548,8 +537,7 @@ static const u32 oland_golden_rlc_registers[] = ...@@ -548,8 +537,7 @@ static const u32 oland_golden_rlc_registers[] =
0xc30c, 0xffffffff, 0x800000f4 0xc30c, 0xffffffff, 0x800000f4
}; };
static const u32 oland_golden_registers[] = static const u32 oland_golden_registers[] = {
{
0x9a10, 0x00010000, 0x00018208, 0x9a10, 0x00010000, 0x00018208,
0x9830, 0xffffffff, 0x00000000, 0x9830, 0xffffffff, 0x00000000,
0x9834, 0xf00fffff, 0x00000400, 0x9834, 0xf00fffff, 0x00000400,
...@@ -579,8 +567,7 @@ static const u32 oland_golden_registers[] = ...@@ -579,8 +567,7 @@ static const u32 oland_golden_registers[] =
0x15c0, 0x000c0fc0, 0x000c0400 0x15c0, 0x000c0fc0, 0x000c0400
}; };
static const u32 hainan_golden_registers[] = static const u32 hainan_golden_registers[] = {
{
0x9a10, 0x00010000, 0x00018208, 0x9a10, 0x00010000, 0x00018208,
0x9830, 0xffffffff, 0x00000000, 0x9830, 0xffffffff, 0x00000000,
0x9834, 0xf00fffff, 0x00000400, 0x9834, 0xf00fffff, 0x00000400,
...@@ -608,13 +595,11 @@ static const u32 hainan_golden_registers[] = ...@@ -608,13 +595,11 @@ static const u32 hainan_golden_registers[] =
0x15c0, 0x000c0fc0, 0x000c0400 0x15c0, 0x000c0fc0, 0x000c0400
}; };
static const u32 hainan_golden_registers2[] = static const u32 hainan_golden_registers2[] = {
{
0x98f8, 0xffffffff, 0x02010001 0x98f8, 0xffffffff, 0x02010001
}; };
static const u32 tahiti_mgcg_cgcg_init[] = static const u32 tahiti_mgcg_cgcg_init[] = {
{
0xc400, 0xffffffff, 0xfffffffc, 0xc400, 0xffffffff, 0xfffffffc,
0x802c, 0xffffffff, 0xe0000000, 0x802c, 0xffffffff, 0xe0000000,
0x9a60, 0xffffffff, 0x00000100, 0x9a60, 0xffffffff, 0x00000100,
...@@ -743,8 +728,7 @@ static const u32 tahiti_mgcg_cgcg_init[] = ...@@ -743,8 +728,7 @@ static const u32 tahiti_mgcg_cgcg_init[] =
0xd8c0, 0xfffffff0, 0x00000100 0xd8c0, 0xfffffff0, 0x00000100
}; };
static const u32 pitcairn_mgcg_cgcg_init[] = static const u32 pitcairn_mgcg_cgcg_init[] = {
{
0xc400, 0xffffffff, 0xfffffffc, 0xc400, 0xffffffff, 0xfffffffc,
0x802c, 0xffffffff, 0xe0000000, 0x802c, 0xffffffff, 0xe0000000,
0x9a60, 0xffffffff, 0x00000100, 0x9a60, 0xffffffff, 0x00000100,
...@@ -841,8 +825,7 @@ static const u32 pitcairn_mgcg_cgcg_init[] = ...@@ -841,8 +825,7 @@ static const u32 pitcairn_mgcg_cgcg_init[] =
0xd8c0, 0xfffffff0, 0x00000100 0xd8c0, 0xfffffff0, 0x00000100
}; };
static const u32 verde_mgcg_cgcg_init[] = static const u32 verde_mgcg_cgcg_init[] = {
{
0xc400, 0xffffffff, 0xfffffffc, 0xc400, 0xffffffff, 0xfffffffc,
0x802c, 0xffffffff, 0xe0000000, 0x802c, 0xffffffff, 0xe0000000,
0x9a60, 0xffffffff, 0x00000100, 0x9a60, 0xffffffff, 0x00000100,
...@@ -941,8 +924,7 @@ static const u32 verde_mgcg_cgcg_init[] = ...@@ -941,8 +924,7 @@ static const u32 verde_mgcg_cgcg_init[] =
0xd8c0, 0xfffffff0, 0x00000100 0xd8c0, 0xfffffff0, 0x00000100
}; };
static const u32 oland_mgcg_cgcg_init[] = static const u32 oland_mgcg_cgcg_init[] = {
{
0xc400, 0xffffffff, 0xfffffffc, 0xc400, 0xffffffff, 0xfffffffc,
0x802c, 0xffffffff, 0xe0000000, 0x802c, 0xffffffff, 0xe0000000,
0x9a60, 0xffffffff, 0x00000100, 0x9a60, 0xffffffff, 0x00000100,
...@@ -1021,8 +1003,7 @@ static const u32 oland_mgcg_cgcg_init[] = ...@@ -1021,8 +1003,7 @@ static const u32 oland_mgcg_cgcg_init[] =
0xd8c0, 0xfffffff0, 0x00000100 0xd8c0, 0xfffffff0, 0x00000100
}; };
static const u32 hainan_mgcg_cgcg_init[] = static const u32 hainan_mgcg_cgcg_init[] = {
{
0xc400, 0xffffffff, 0xfffffffc, 0xc400, 0xffffffff, 0xfffffffc,
0x802c, 0xffffffff, 0xe0000000, 0x802c, 0xffffffff, 0xe0000000,
0x9a60, 0xffffffff, 0x00000100, 0x9a60, 0xffffffff, 0x00000100,
...@@ -1098,8 +1079,7 @@ static const u32 hainan_mgcg_cgcg_init[] = ...@@ -1098,8 +1079,7 @@ static const u32 hainan_mgcg_cgcg_init[] =
0xd8c0, 0xfffffff0, 0x00000100 0xd8c0, 0xfffffff0, 0x00000100
}; };
static u32 verde_pg_init[] = static u32 verde_pg_init[] = {
{
0x353c, 0xffffffff, 0x40000, 0x353c, 0xffffffff, 0x40000,
0x3538, 0xffffffff, 0x200010ff, 0x3538, 0xffffffff, 0x200010ff,
0x353c, 0xffffffff, 0x0, 0x353c, 0xffffffff, 0x0,
...@@ -1768,7 +1748,8 @@ static int si_init_microcode(struct radeon_device *rdev) ...@@ -1768,7 +1748,8 @@ static int si_init_microcode(struct radeon_device *rdev)
mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4; mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
smc_req_size = ALIGN(HAINAN_SMC_UCODE_SIZE, 4); smc_req_size = ALIGN(HAINAN_SMC_UCODE_SIZE, 4);
break; break;
default: BUG(); default:
BUG();
} }
/* this memory configuration requires special firmware */ /* this memory configuration requires special firmware */
......
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