Commit ce910686 authored by Thierry Reding's avatar Thierry Reding Committed by Stephen Warren

clk: tegra: Make gr2d and gr3d clocks children of pll_c

By default these clocks are children of pll_m, but in downstream kernels
they are reparented to pll_c. While at it, decrease their frequencies to
300 MHz because the defaults aren't in the specified range.

gr2d can reportedly run at much higher frequencies, but 300 MHz works
and is a more conservative default.
Signed-off-by: default avatarThierry Reding <thierry.reding@avionic-design.de>
Acked-by: default avatarMike Turquette <mturquette@linaro.org>
Acked-By: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent 4dd59cdd
......@@ -1247,6 +1247,8 @@ static __initdata struct tegra_clk_init_table init_table[] = {
{host1x, pll_c, 150000000, 0},
{disp1, pll_p, 600000000, 0},
{disp2, pll_p, 600000000, 0},
{gr2d, pll_c, 300000000, 0},
{gr3d, pll_c, 300000000, 0},
{clk_max, clk_max, 0, 0}, /* This MUST be the last entry */
};
......
......@@ -1911,6 +1911,8 @@ static __initdata struct tegra_clk_init_table init_table[] = {
{disp1, pll_p, 600000000, 0},
{disp2, pll_p, 600000000, 0},
{twd, clk_max, 0, 1},
{gr2d, pll_c, 300000000, 0},
{gr3d, pll_c, 300000000, 0},
{clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
};
......
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