[ARM PATCH] 2362/1: cleanup of PCI defines for IOP321 platforms

Patch from Dave Jiang

Signed-off-by: Dave Jiang

Major cleanup of the 321 PCI defines to make them more coherent. Unified some groups that were per platform to common proc specific. Removed some magic numbers.
Signed-off-by: Russell King

arch/arm/mach-iop3xx/iop321-pci.c

@@ -197,14 +197,6 @@ struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *sys)
 
 void iop321_init(void)
 {
-#if CONFIG_ARCH_EP80219
-    *IOP321_ATUCR = 0x2;
-    *IOP321_OIOWTVR = 0x90000000;
-    *IOP321_IABAR0  = 0x00000004;
-    *IOP321_IABAR2  = 0xa000000c;
-    *IOP321_IALR2   = 0xe0000000;
-#endif
-
 	DBG("PCI:  Intel 80321 PCI init code.\n");
 	DBG("\tATU: IOP321_ATUCMD=0x%04x\n", *IOP321_ATUCMD);
 	DBG("\tATU: IOP321_OMWTVR0=0x%04x, IOP321_OIOWTVR=0x%04x\n",

arch/arm/mach-iop3xx/iop321-setup.c

@@ -3,6 +3,7 @@
  *
  * Author: Nicolas Pitre <nico@cam.org>
  * Copyright (C) 2001 MontaVista Software, Inc.
+ * Copyright (C) 2004 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -40,10 +41,10 @@ static struct map_desc iop321_std_desc[] __initdata = {
  /* virtual     physical      length      type */
 
  /* mem mapped registers */
- { IOP321_VIRT_MEM_BASE,  IOP321_PHY_MEM_BASE,   0x00002000,  MT_DEVICE },
+ { IOP321_VIRT_MEM_BASE,  IOP321_PHYS_MEM_BASE,   0x00002000,  MT_DEVICE },
 
  /* PCI IO space */
- { 0xfe000000,  0x90000000,   0x00020000,  MT_DEVICE }
+ { IOP321_PCI_LOWER_IO_VA,  IOP321_PCI_LOWER_IO_PA,   IOP321_PCI_IO_WINDOW_SIZE,  MT_DEVICE }
 };
 
 #ifdef CONFIG_ARCH_IQ80321
@@ -71,6 +72,60 @@ static struct uart_port iop321_serial_ports[] = {
 	}
 };
 
+static struct resource iop32x_i2c_0_resources[] = {
+	[0] = {
+		.start = 0xfffff680,
+		.end = 0xfffff698,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_IOP321_I2C_0,
+		.end = IRQ_IOP321_I2C_0,
+		.flags = IORESOURCE_IRQ
+	}
+};
+
+static struct resource iop32x_i2c_1_resources[] = {
+	[0] = {
+		.start = 0xfffff6a0,
+		.end = 0xfffff6b8,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_IOP321_I2C_1,
+		.end = IRQ_IOP321_I2C_1,
+		.flags = IORESOURCE_IRQ
+	}
+};
+
+static struct platform_device iop32x_i2c_0_controller = {
+	.name = "IOP3xx-I2C",
+	.id = 0,
+	.num_resources = 2,
+	.resource = iop32x_i2c_0_resources
+};
+
+static struct platform_device iop32x_i2c_1_controller = {
+	.name = "IOP3xx-I2C",
+	.id = 1,
+	.num_resources = 2,
+	.resource = iop32x_i2c_1_resources
+};
+
+static struct platform_device *iop32x_devices[] __initdata = {
+	&iop32x_i2c_0_controller,
+	&iop32x_i2c_1_controller
+};
+
+void __init iop32x_init(void)
+{
+	if(iop_is_321())
+	{
+		platform_add_devices(iop32x_devices,
+				ARRAY_SIZE(iop32x_devices));
+	}
+}
+
 void __init iop321_map_io(void)
 {
 	iotable_init(iop321_std_desc, ARRAY_SIZE(iop321_std_desc));
@@ -97,6 +152,7 @@ MACHINE_START(IQ80321, "Intel IQ80321")
 	INITIRQ(iop321_init_irq)
 	.timer		= &iop321_timer,
     BOOT_PARAMS(0xa0000100)
+	INIT_MACHINE(iop32x_init)
 MACHINE_END
 #elif defined(CONFIG_ARCH_IQ31244)
 MACHINE_START(IQ31244, "Intel IQ31244")
@@ -106,6 +162,7 @@ MACHINE_START(IQ31244, "Intel IQ31244")
     INITIRQ(iop321_init_irq)
 	.timer		= &iop321_timer,
     BOOT_PARAMS(0xa0000100)
+	INIT_MACHINE(iop32x_init)
 MACHINE_END
 #else
 #error No machine descriptor defined for this IOP3XX implementation

arch/arm/mach-iop3xx/iq31244-pci.c

@@ -5,6 +5,7 @@
  *
  * Author: Rory Bolt <rorybolt@pacbell.net>
  * Copyright (C) 2002 Rory Bolt
+ * Copyright (C) 2004 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -77,28 +78,28 @@ static int iq31244_setup(int nr, struct pci_sys_data *sys)
 
 	memset(res, 0, sizeof(struct resource) * 2);
 
-	res[0].start = IQ31244_PCI_IO_BASE + 0x6e000000;
-	res[0].end   = IQ31244_PCI_IO_BASE + IQ31244_PCI_IO_SIZE - 1 + IQ31244_PCI_IO_OFFSET;
+	res[0].start = IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_OFFSET;
+	res[0].end   = IOP321_PCI_UPPER_IO_BA + IOP321_PCI_IO_OFFSET;
 	res[0].name  = "IQ31244 PCI I/O Space";
 	res[0].flags = IORESOURCE_IO;
 
-	res[1].start = IQ31244_PCI_MEM_BASE;
-	res[1].end   = IQ31244_PCI_MEM_BASE + IQ31244_PCI_MEM_SIZE;
+	res[1].start = IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_OFFSET;
+	res[1].end   = IOP321_PCI_UPPER_MEM_BA + IOP321_PCI_MEM_OFFSET;
 	res[1].name  = "IQ31244 PCI Memory Space";
 	res[1].flags = IORESOURCE_MEM;
 
 	request_resource(&ioport_resource, &res[0]);
 	request_resource(&iomem_resource, &res[1]);
 
+	sys->mem_offset = IOP321_PCI_MEM_OFFSET;
+	sys->io_offset  = IOP321_PCI_IO_OFFSET;
+
 	sys->resource[0] = &res[0];
 	sys->resource[1] = &res[1];
 	sys->resource[2] = NULL;
-	sys->io_offset   = IQ31244_PCI_IO_OFFSET;
-	sys->mem_offset = IQ80321_PCI_MEM_BASE -
-		(*IOP321_IABAR1 & PCI_BASE_ADDRESS_MEM_MASK);
 
-	iop3xx_pcibios_min_io = IQ31244_PCI_IO_BASE;
-	iop3xx_pcibios_min_mem = IQ31244_PCI_MEM_BASE;
+	iop3xx_pcibios_min_io = IOP321_PCI_LOWER_IO_VA;
+	iop3xx_pcibios_min_mem = IOP321_PCI_LOWER_MEM_VA;
 
 	return 1;
 }
@@ -106,9 +107,6 @@ static int iq31244_setup(int nr, struct pci_sys_data *sys)
 static void iq31244_preinit(void)
 {
 	iop321_init();
-	/* setting up the second translation window */
-	*IOP321_OMWTVR1 = IQ31244_PCI_MEM_BASE + 0x04000000;
-	*IOP321_OUMWTVR1 = 0x0;
 }
 
 static struct hw_pci iq31244_pci __initdata = {

arch/arm/mach-iop3xx/iq80321-pci.c

@@ -5,6 +5,7 @@
  *
  * Author: Rory Bolt <rorybolt@pacbell.net>
  * Copyright (C) 2002 Rory Bolt
+ * Copyright (C) 2004 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -71,44 +72,28 @@ static int iq80321_setup(int nr, struct pci_sys_data *sys)
 
 	memset(res, 0, sizeof(struct resource) * 2);
 
-	res[0].start = IQ80321_PCI_IO_BASE + IQ80321_PCI_IO_OFFSET;
-	res[0].end   = IQ80321_PCI_IO_BASE + IQ80321_PCI_IO_SIZE - 1 + IQ80321_PCI_IO_OFFSET;
+	res[0].start = IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_OFFSET;
+	res[0].end   = IOP321_PCI_UPPER_IO_BA + IOP321_PCI_IO_OFFSET;
 	res[0].name  = "IQ80321 PCI I/O Space";
 	res[0].flags = IORESOURCE_IO;
 
-	res[1].start = IQ80321_PCI_MEM_BASE;
-	res[1].end   = IQ80321_PCI_MEM_BASE + IQ80321_PCI_MEM_SIZE;
+	res[1].start = IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_OFFSET;
+	res[1].end   = IOP321_PCI_UPPER_MEM_BA + IOP321_PCI_MEM_OFFSET;
 	res[1].name  = "IQ80321 PCI Memory Space";
 	res[1].flags = IORESOURCE_MEM;
 
 	request_resource(&ioport_resource, &res[0]);
 	request_resource(&iomem_resource, &res[1]);
 
-	/*
-	 * Since the IQ80321 is a slave card on a PCI backplane,
-	 * it uses BAR1 to reserve a portion of PCI memory space for
-	 * use with the private devices on the secondary bus
-	 * (GigE and PCI-X slot). We read BAR1 and configure
-	 * our outbound translation windows to target that
-	 * address range and assign all devices in that
-	 * address range. W/O this, certain BIOSes will fail
-	 * to boot as the IQ80321 claims addresses that are
-	 * in use by other devices.
-	 *
-	 * Note that the same cannot be done  with I/O space,
-	 * so hopefully the host will stick to the lower 64K for
-	 * PCI I/O and leave us alone.
-	 */
-	sys->mem_offset = IQ80321_PCI_MEM_BASE -
-		(*IOP321_IABAR1 & PCI_BASE_ADDRESS_MEM_MASK);
+	sys->mem_offset = IOP321_PCI_MEM_OFFSET;
+	sys->io_offset  = IOP321_PCI_IO_OFFSET;
 
 	sys->resource[0] = &res[0];
 	sys->resource[1] = &res[1];
 	sys->resource[2] = NULL;
-	sys->io_offset   = IQ80321_PCI_IO_OFFSET;
 
-	iop3xx_pcibios_min_io = IQ80321_PCI_IO_BASE;
-	iop3xx_pcibios_min_mem = IQ80321_PCI_MEM_BASE;
+	iop3xx_pcibios_min_io = IOP321_PCI_LOWER_IO_VA;
+	iop3xx_pcibios_min_mem = IOP321_PCI_LOWER_MEM_VA;
 
 	return 1;
 }

include/asm-arm/arch-iop3xx/iop321.h

@@ -5,6 +5,7 @@
  *
  * Author: Rory Bolt <rorybolt@pacbell.net>
  * Copyright (C) 2002 Rory Bolt
+ * Copyright (C) 2004 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -30,21 +31,30 @@
 /*
  * IOP321 I/O and Mem space regions for PCI autoconfiguration
  */
-#define IOP321_PCI_LOWER_IO             0x90000000
-#define IOP321_PCI_UPPER_IO             0x9000ffff
-#define IOP321_PCI_LOWER_MEM            0x80000000
-#define IOP321_PCI_UPPER_MEM            0x83ffffff
-
-#define IOP321_PCI_WINDOW_SIZE          64 * 0x100000
+#define IOP321_PCI_IO_WINDOW_SIZE   0x10000
+#define IOP321_PCI_LOWER_IO_PA      0x90000000
+#define IOP321_PCI_LOWER_IO_VA      0xfe000000
+#define IOP321_PCI_LOWER_IO_BA      (*IOP321_OIOWTVR)
+#define IOP321_PCI_UPPER_IO_PA      (IOP321_PCI_LOWER_IO_PA + IOP321_PCI_IO_WINDOW_SIZE - 1)
+#define IOP321_PCI_UPPER_IO_VA      (IOP321_PCI_LOWER_IO_VA + IOP321_PCI_IO_WINDOW_SIZE - 1)
+#define IOP321_PCI_UPPER_IO_BA      (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1)
+#define IOP321_PCI_IO_OFFSET        (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA)
+
+#define IOP321_PCI_MEM_WINDOW_SIZE  (~*IOP321_IALR1 + 1)
+#define IOP321_PCI_LOWER_MEM_PA     0x80000000
+#define IOP321_PCI_LOWER_MEM_VA     0x80000000
+#define IOP321_PCI_LOWER_MEM_BA     (*IOP321_OMWTVR0)
+#define IOP321_PCI_UPPER_MEM_PA     (IOP321_PCI_LOWER_MEM_PA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
+#define IOP321_PCI_UPPER_MEM_VA     (IOP321_PCI_LOWER_MEM_VA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
+#define IOP321_PCI_UPPER_MEM_BA     (IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
+#define IOP321_PCI_MEM_OFFSET       (IOP321_PCI_LOWER_MEM_VA - IOP321_PCI_LOWER_MEM_BA)
 
 
 /*
  * IOP321 chipset registers
  */
 #define IOP321_VIRT_MEM_BASE 0xfeffe000  /* chip virtual mem address*/
-//#define IOP321_VIRT_MEM_BASE 0xfff00000  /* chip virtual mem address*/
-
-#define IOP321_PHY_MEM_BASE  0xffffe000  /* chip physical memory address */
+#define IOP321_PHYS_MEM_BASE 0xffffe000  /* chip physical memory address */
 #define IOP321_REG_ADDR(reg) (IOP321_VIRT_MEM_BASE | (reg))
 
 /* Reserved 0x00000000 through 0x000000FF */

include/asm-arm/arch-iop3xx/iq31244.h

@@ -7,8 +7,6 @@
 #ifndef _IQ31244_H_
 #define _IQ31244_H_
 
-#define IQ31244_RAMBASE		0xa0000000
-
 #define	IQ31244_FLASHBASE	0xf0000000	/* Flash */
 #define	IQ31244_FLASHSIZE	0x00800000
 #define	IQ31244_FLASHWIDTH	2
@@ -19,16 +17,6 @@
 #define IQ31244_ROTARY_SW	0xfe8d0000	/* Rotary Switch */
 #define IQ31244_BATT_STAT	0xfe8f0000	/* Battery Status */
 
-/*
- * IQ31244 PCI I/O and Mem space regions
- */
-#define IQ31244_PCI_IO_BASE	0x90000000
-#define IQ31244_PCI_IO_SIZE	0x00010000
-#define IQ31244_PCI_MEM_BASE	0x80000000
-//#define IQ31244_PCI_MEM_SIZE	0x04000000
-#define IQ31244_PCI_MEM_SIZE	0x08000000
-#define	IQ31244_PCI_IO_OFFSET	0x6e000000
-
 #ifndef __ASSEMBLY__
 extern void iq31244_map_io(void);
 #endif

include/asm-arm/arch-iop3xx/iq80321.h

@@ -7,8 +7,6 @@
 #ifndef _IQ80321_H_
 #define _IQ80321_H_
 
-#define IQ80321_RAMBASE		0xa0000000
-
 #define	IQ80321_FLASHBASE	0xf0000000	/* Flash */
 #define	IQ80321_FLASHSIZE	0x00800000
 #define	IQ80321_FLASHWIDTH	1
@@ -19,15 +17,6 @@
 #define IQ80321_ROTARY_SW	0xfe8d0000	/* Rotary Switch */
 #define IQ80321_BATT_STAT	0xfe8f0000	/* Battery Status */
 
-/*
- * IQ80321 PCI I/O and Mem space regions
- */
-#define IQ80321_PCI_IO_BASE	0x90000000
-#define IQ80321_PCI_IO_SIZE	0x00010000
-#define IQ80321_PCI_MEM_BASE	0x80000000
-#define IQ80321_PCI_MEM_SIZE	0x04000000
-#define	IQ80321_PCI_IO_OFFSET	0x6e000000
-
 #ifndef __ASSEMBLY__
 extern void iq80321_map_io(void);
 #endif