Commit cf15079c authored by Jeremy J. Peper's avatar Jeremy J. Peper Committed by Arnd Bergmann

ARM: mv78xx0: adjust init logic for ts-wxl to reflect single core dev

Original code was largely copy-pasted from the reference board code, adjust pcie initialiazation to reflect the TS-WXL using the single-core variant of this SoC.
Correct pcie_port_size to be a power of 2 as required.
Signed-off-by: default avatarJeremy J. Peper <jeremy@jeremypeper.com>
Reviewed-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent ec79ed5e
...@@ -125,16 +125,8 @@ static void __init wxl_init(void) ...@@ -125,16 +125,8 @@ static void __init wxl_init(void)
static int __init wxl_pci_init(void) static int __init wxl_pci_init(void)
{ {
if (machine_is_terastation_wxl()) { if (machine_is_terastation_wxl() && mv78xx0_core_index() == 0)
/* mv78xx0_pcie_init(1, 1);
* Assign the x16 PCIe slot on the board to CPU core
* #0, and let CPU core #1 have the four x1 slots.
*/
if (mv78xx0_core_index() == 0)
mv78xx0_pcie_init(0, 1);
else
mv78xx0_pcie_init(1, 0);
}
return 0; return 0;
} }
......
...@@ -42,7 +42,7 @@ void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) ...@@ -42,7 +42,7 @@ void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
u32 pcie_port_size[8] = { u32 pcie_port_size[8] = {
0, 0,
0x30000000, 0x20000000,
0x10000000, 0x10000000,
0x10000000, 0x10000000,
0x08000000, 0x08000000,
......
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