Commit cf61f5b0 authored by Shunli Wang's avatar Shunli Wang Committed by Mark Brown

ASoC: Mediatek: MT8183: set data align

This patch sets register and bit information about
data align for every memory interface.
Signed-off-by: default avatarShunli Wang <shunli.wang@mediatek.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 1628fc3f
...@@ -437,7 +437,9 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { ...@@ -437,7 +437,9 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
.enable_reg = AFE_DAC_CON0, .enable_reg = AFE_DAC_CON0,
.enable_shift = DL1_ON_SFT, .enable_shift = DL1_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE, .hd_reg = AFE_MEMIF_HD_MODE,
.hd_align_reg = AFE_MEMIF_HDALIGN,
.hd_shift = DL1_HD_SFT, .hd_shift = DL1_HD_SFT,
.hd_align_mshift = DL1_HD_ALIGN_MASK_SFT,
.agent_disable_reg = -1, .agent_disable_reg = -1,
.agent_disable_shift = -1, .agent_disable_shift = -1,
.msb_reg = -1, .msb_reg = -1,
...@@ -456,7 +458,9 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { ...@@ -456,7 +458,9 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
.enable_reg = AFE_DAC_CON0, .enable_reg = AFE_DAC_CON0,
.enable_shift = DL2_ON_SFT, .enable_shift = DL2_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE, .hd_reg = AFE_MEMIF_HD_MODE,
.hd_align_reg = AFE_MEMIF_HDALIGN,
.hd_shift = DL2_HD_SFT, .hd_shift = DL2_HD_SFT,
.hd_align_mshift = DL2_HD_ALIGN_MASK_SFT,
.agent_disable_reg = -1, .agent_disable_reg = -1,
.agent_disable_shift = -1, .agent_disable_shift = -1,
.msb_reg = -1, .msb_reg = -1,
...@@ -475,7 +479,9 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { ...@@ -475,7 +479,9 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
.enable_reg = AFE_DAC_CON0, .enable_reg = AFE_DAC_CON0,
.enable_shift = DL3_ON_SFT, .enable_shift = DL3_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE, .hd_reg = AFE_MEMIF_HD_MODE,
.hd_align_reg = AFE_MEMIF_HDALIGN,
.hd_shift = DL3_HD_SFT, .hd_shift = DL3_HD_SFT,
.hd_align_mshift = DL3_HD_ALIGN_MASK_SFT,
.agent_disable_reg = -1, .agent_disable_reg = -1,
.agent_disable_shift = -1, .agent_disable_shift = -1,
.msb_reg = -1, .msb_reg = -1,
...@@ -494,7 +500,9 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { ...@@ -494,7 +500,9 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
.enable_reg = AFE_DAC_CON0, .enable_reg = AFE_DAC_CON0,
.enable_shift = VUL2_ON_SFT, .enable_shift = VUL2_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE, .hd_reg = AFE_MEMIF_HD_MODE,
.hd_align_reg = AFE_MEMIF_HDALIGN,
.hd_shift = VUL2_HD_SFT, .hd_shift = VUL2_HD_SFT,
.hd_align_mshift = VUL2_HD_ALIGN_MASK_SFT,
.agent_disable_reg = -1, .agent_disable_reg = -1,
.agent_disable_shift = -1, .agent_disable_shift = -1,
.msb_reg = -1, .msb_reg = -1,
...@@ -513,7 +521,9 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { ...@@ -513,7 +521,9 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
.enable_reg = AFE_DAC_CON0, .enable_reg = AFE_DAC_CON0,
.enable_shift = AWB_ON_SFT, .enable_shift = AWB_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE, .hd_reg = AFE_MEMIF_HD_MODE,
.hd_align_reg = AFE_MEMIF_HDALIGN,
.hd_shift = AWB_HD_SFT, .hd_shift = AWB_HD_SFT,
.hd_align_mshift = AWB_HD_ALIGN_MASK_SFT,
.agent_disable_reg = -1, .agent_disable_reg = -1,
.agent_disable_shift = -1, .agent_disable_shift = -1,
.msb_reg = -1, .msb_reg = -1,
...@@ -532,7 +542,9 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { ...@@ -532,7 +542,9 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
.enable_reg = AFE_DAC_CON0, .enable_reg = AFE_DAC_CON0,
.enable_shift = AWB2_ON_SFT, .enable_shift = AWB2_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE, .hd_reg = AFE_MEMIF_HD_MODE,
.hd_align_reg = AFE_MEMIF_HDALIGN,
.hd_shift = AWB2_HD_SFT, .hd_shift = AWB2_HD_SFT,
.hd_align_mshift = AWB2_ALIGN_MASK_SFT,
.agent_disable_reg = -1, .agent_disable_reg = -1,
.agent_disable_shift = -1, .agent_disable_shift = -1,
.msb_reg = -1, .msb_reg = -1,
...@@ -551,7 +563,9 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { ...@@ -551,7 +563,9 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
.enable_reg = AFE_DAC_CON0, .enable_reg = AFE_DAC_CON0,
.enable_shift = VUL12_ON_SFT, .enable_shift = VUL12_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE, .hd_reg = AFE_MEMIF_HD_MODE,
.hd_align_reg = AFE_MEMIF_HDALIGN,
.hd_shift = VUL12_HD_SFT, .hd_shift = VUL12_HD_SFT,
.hd_align_mshift = VUL12_HD_ALIGN_MASK_SFT,
.agent_disable_reg = -1, .agent_disable_reg = -1,
.agent_disable_shift = -1, .agent_disable_shift = -1,
.msb_reg = -1, .msb_reg = -1,
...@@ -570,7 +584,9 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { ...@@ -570,7 +584,9 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
.enable_reg = AFE_DAC_CON0, .enable_reg = AFE_DAC_CON0,
.enable_shift = MOD_DAI_ON_SFT, .enable_shift = MOD_DAI_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE, .hd_reg = AFE_MEMIF_HD_MODE,
.hd_align_reg = AFE_MEMIF_HDALIGN,
.hd_shift = MOD_DAI_HD_SFT, .hd_shift = MOD_DAI_HD_SFT,
.hd_align_mshift = MOD_DAI_HD_ALIGN_MASK_SFT,
.agent_disable_reg = -1, .agent_disable_reg = -1,
.agent_disable_shift = -1, .agent_disable_shift = -1,
.msb_reg = -1, .msb_reg = -1,
...@@ -589,7 +605,9 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { ...@@ -589,7 +605,9 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
.enable_reg = -1, /* control in tdm for sync start */ .enable_reg = -1, /* control in tdm for sync start */
.enable_shift = -1, .enable_shift = -1,
.hd_reg = AFE_MEMIF_HD_MODE, .hd_reg = AFE_MEMIF_HD_MODE,
.hd_align_reg = AFE_MEMIF_HDALIGN,
.hd_shift = HDMI_HD_SFT, .hd_shift = HDMI_HD_SFT,
.hd_align_mshift = HDMI_HD_ALIGN_MASK_SFT,
.agent_disable_reg = -1, .agent_disable_reg = -1,
.agent_disable_shift = -1, .agent_disable_shift = -1,
.msb_reg = -1, .msb_reg = -1,
......
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